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The first value corresponds to the first rising transition after time zero. The numbers should represent one full clock period.","type":"text"}]}]}]},{"type":"tableRow","content":[{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[74.0]},"content":[{"type":"paragraph","content":[{"text":"source","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[686.0]},"content":[{"type":"paragraph","content":[{"text":"The query which specifies how to get a clock related point. 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clocks on ports clk1 and clk2 with a period of 8, a rising edge at 0, and a falling edge at 4:","type":"text"}]},{"type":"codeBlock","content":[{"text":"create_clock -period 8 clk1\ncreate_clock –period 8 –waveform {0 4} {clk2}","type":"text"}]},{"type":"paragraph","content":[{"text":"The following example creates a clock on port clk3 with a period of 7, a rising edge at 2, and a falling edge at 4:","type":"text"}]},{"type":"codeBlock","content":[{"text":"create_clock –period 7 –waveform {2 4} [get_ports {clk3}]","type":"text"}]},{"type":"panel","attrs":{"panelType":"warning"},"content":[{"type":"paragraph","content":[{"text":"Please note that virtual clocks are not handled by Impulse.","type":"text"}]}]},{"type":"paragraph"},{"type":"heading","attrs":{"level":2},"content":[{"text":"create_generated_clock","type":"text"}]},{"type":"paragraph","content":[{"text":"Creates a new clock signal from the clock waveform of a given pin in the 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frequency of the new clock by dividing the frequency of the source clock by this factor. The value must be greater or equal to 1. Default value is 1","type":"text"}]}]}]},{"type":"tableRow","content":[{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[74.0]},"content":[{"type":"paragraph","content":[{"text":"-duty_cycle","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[686.0]},"content":[{"type":"paragraph","content":[{"text":"Specifies the duty cycle (high pulse width) as a percentage of the clock period. The range must be between 1 and 99. Default value is 50.0","type":"text"}]}]}]},{"type":"tableRow","content":[{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[74.0]},"content":[{"type":"paragraph","content":[{"text":"-edge_shift","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[686.0]},"content":[{"type":"paragraph","content":[{"text":"Specifies how much each edge specified with the ","type":"text"},{"text":"-edges","type":"text","marks":[{"type":"code"}]},{"text":" option should be shifted.","type":"text"}]}]}]},{"type":"tableRow","content":[{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[74.0]},"content":[{"type":"paragraph","content":[{"text":"-edges","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[686.0]},"content":[{"type":"paragraph","content":[{"text":"Selects a list of edges from the source clock that form the edges of the derived clock. You must specify an odd number of edges. The last edge represents the first edge of the next clock period.","type":"text"}]},{"type":"panel","attrs":{"panelType":"warning"},"content":[{"type":"paragraph","content":[{"text":"You cannot specify this option with either the ","type":"text"},{"text":"-divide_by","type":"text","marks":[{"type":"code"}]},{"text":" or ","type":"text"},{"text":"-multiply_by","type":"text","marks":[{"type":"code"}]},{"text":" option.","type":"text"}]}]}]}]},{"type":"tableRow","content":[{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[74.0]},"content":[{"type":"paragraph","content":[{"text":"-invert","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[686.0]},"content":[{"type":"paragraph","content":[{"text":"Inverts the resulting waveform of the generated clock.","type":"text"}]}]}]},{"type":"tableRow","content":[{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[74.0]},"content":[{"type":"paragraph","content":[{"text":"-multiply_by","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[686.0]},"content":[{"type":"paragraph","content":[{"text":"Determines the frequency of the new clock by multiplying the frequency of the source clock with this factor. The value must be greater or equal to 1. Default value is 1","type":"text"}]}]}]},{"type":"tableRow","content":[{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[74.0]},"content":[{"type":"paragraph","content":[{"text":"-name","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[686.0]},"content":[{"type":"paragraph","content":[{"text":"Specifies the name of the generated clock. ","type":"text"}]}]}]},{"type":"tableRow","content":[{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[74.0]},"content":[{"type":"paragraph","content":[{"text":"-offset","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[686.0]},"content":[{"type":"paragraph","content":[{"text":"Specifies the offset for the rising edge.","type":"text"}]}]}]},{"type":"tableRow","content":[{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[74.0]},"content":[{"type":"paragraph","content":[{"text":"-phase","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[686.0]},"content":[{"type":"paragraph","content":[{"text":"Specifies the phase of the generated clock. The range must be from 0 to 359","type":"text"}]}]}]},{"type":"tableRow","content":[{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[74.0]},"content":[{"type":"paragraph","content":[{"text":"-source","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[686.0]},"content":[{"type":"paragraph","content":[{"text":"Specifies the name of the pin from which the clock must be derived. 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A valid timing starting point is an input port or a register. A valid argument can be: ","type":"text"},{"text":"get_ports","type":"text","marks":[{"type":"code"}]},{"text":" or ","type":"text"},{"text":"get_registers","type":"text","marks":[{"type":"code"}]}]}]}]},{"type":"tableRow","content":[{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[80.0]},"content":[{"type":"paragraph","content":[{"text":"to","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[680.0]},"content":[{"type":"paragraph","content":[{"text":"Specifies how to get a timing path ending points. A valid timing ending point is an output port or a register. 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