Impulse 23.3 Simulation

Owned by Fabrice NSONGO
Last updated: 21 Nov, 2023 by Samah
3 min read

Introduction

The aim of this document is to explain how to simulate a design dedicated to NanoXplore targets under Questa/Modelsim tools.

The needed minimum version is Modelsim 10.6d

Design simulation

Simulation

The user design may include NX primitives with files calling nxpackage as follow in a VHDL file:

library nx; use nx.nxpackage.all;

Consequently, the compilation script must include this package and all primitives architectures.

There is one file per variant so for instance, the file to compile is stored in each release in the following path:

impulse-<version_number>/share/modelsim/nxLibrary-<variant_name>.vhdp

For instance, for NG-MEDIUM or NG-MEDIUM-EMBEDDED target, with nxmap 22.1.0.1 release, the path is:

impulse-23.3.0.2/share/modelsim/nxLibrary-Medium.vhdp

Only components and entities are declared in the clear part.

Architecture models are private and encrypted.

Hereafter an example of TCL script to compile and simulate a design:

Netlist simulation

It can be useful to simulate a design with the output netlist generated after synthesis. Indeed, it give the ability to check NXmap synthesis tool mapped correctly the design into a flattened design containing only NX primitives even after optimizations.

Netlist generation

The netlist must be generated using NXmap tool in the NXmap flow as follows:

Output netlist can be in VHDL or verilog code.

Generate an output netlist after at least synthesizing step 2.

For instance, the netlist can be generated after the final routing step like the following example:

Simulation

Then, in the simulation script, netlist must be compiled instead of all design files as follows:

Backannoted simulation

Backannoted simulation is a simulation with the output netlist but taking account of timing delays between and inside NX primitives.

It can be useful in order to detect a timing violation in the design and its consequence.

Netlist and SDF generation

In addition of the netlist, a Standard Delay Format (SDF) output file must be generated using Impulse flow as follows:

Conditions get different voltage and temperature and must be in the following list:

  • bestcase: -40°C / VDD+10%

  • typical: 25°C / VDD-10%

  • worstcase: 125°C / VDD-10%

For instance, the netlist can be generated after the final routing step like the following example:

A SDF file describes each path with a minimum, a maximum and an optional typical delay time.

Simulation

Compiling an SDF file is necessary in order to proceed to a backannoted simulation.

There is one file per variant so for instance, the file to compile is stored in each release in the following path:

For NG-MEDIUM and NG-MEDIUM-EMBEDDED target, with Impulse 23.3.0.2 release, the path is:

Then, in the simulation script, netlist must be compiled instead of all design files and SDF option added linking the top instance in the simulation command as follows:

 

 

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