Impulse 23.3 Application Note : LVDS Input Common Mode

Owned by Fabrice NSONGO
Last updated: 03 Oct, 2023 by Kévin Chopier
3 min read

Introduction

Scope of the document

This document describes Low Voltage Differential Signaling (LVDS) input common mode voltage adaptation that can be used with NanoXplore NG-FPGA family.

NG-FPGA devices have LVDS compatible IO buffers without having support for the full range of ANSI/TIA/EIA-655 LVDS standard. In particular, boundary conditions (operating ranges near upper and lower limits) of input common mode voltage range are not supported in NG-FPGA devices.

LVDS Driver and Receiver Scheme

The following figure presents LVDS Driver and receiver connection scheme in which NG-FPGA used as a receiver. As the standard requires, the receiver end is terminated with 100 ohms differential termination resistors. In NG-FPGA IO pads with LVDS support, the On-Die Termination (ODT) can be used to implement the 100 ohms differential resistor. This latter is realized by connecting two 50 ohms resistors in series. This ODT mode is called as ‘differential termination mode’. In this case, a virtual common mode point is created between two resistors and the voltage at this point is named as the input-common mode voltage (VICM). VICM value is defined by the drive strength of the LVDS driver resulting in a floating voltage point. The typical value is 1.2V, whereas some commercial product may work with very low (≈0.2V) or very high (≈2.0V) common mode voltages.

NG-FPGA input buffers have VICM range support. The range depends on the FPGA variant. Please refer to the datasheet of your variant for lower an upper limit of the supported range.

LVDS Driver Receiver Schema when NG FPGA used as receiver.

NG-FPGA LVDS Input Common Mode Voltage Adaptation

In NG-FPGA devices, IO pads with LVDS support are located in Complex IO banks. In case where an LVDS driver communicating with VICM outside the supported voltage range has to be used with NG-FPGA, the single-ended ODT function of Complex IO Banks can be used to adapt this driver to NG-FPGA LVDS input as presented in the following figure.

Complex IO banks, besides having differential termination resistance support as shown in Figure 1, can also implement single-ended termination resistance to a fixed voltage point, VTT. Each Complex IO bank has its dedicated termination voltage pins to provide VTT. When two 50 ohms ODT resistors are connected to the fixed VTT point in single-ended mode, the NG-FPGA input buffer sees VTT value as VICM. Therefore, by using the scheme shown in Figure 2, one can transform VICM values outside the supported range of NG-FPGA devices to typical LVDS values (1.2V or 0.9V).

If one does not want to use the ODT function, the adaptation can be performed on PCB level by placing two 50 ohms resistors between signal traces and a fixed voltage point on board.

LVDS Driver - Receiver Schema where NG-FPGA is used at the receiver end.

The 100 ohms differential termination resistance is realized as two 50 ohms termination resistors connected to a fixed voltage point VTT.

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