Impulse Library guide NG-ULTRA

Owned by Kévin Chopier
Last updated: 20 Jun, 2023 by Israel Lopes (Unlicensed)
99 min read

Introduction

This document aims at giving guidelines on how to use the provided NX components in VHDL source code for NXmap3. Its purpose is to explain how to correctly instantiate the different supported NX components provided by NanoXplore for NXmap3 synthesis and implementation tools.

 

For each NX component, the reader will find a quick introduction and a description of both the generics and ports. He will also find a diagram of the component with an instantiation example in VHDL.

 

 

 

Clocks distribution and management

 

NX_BD

Description

The NX_BD component describes a Buffer Driver circuit that allows the user to direct the routing of a signal to the general routing or low-skew network.

 

Generics

system

mode string

default value “local_lowskew”

If mode is set to “local_lowskew”, the output signal is routed to local low skew network at TILE level.

If mode is set to “global_lowskew”, the output signal is routed to global low skew network of fabric.

 

Ports

Ports

Direction

Type

Description

I

input

std_logic

Input signal

O

output

std_logic

Output signal

 

 

Example

This documentation only provides the instantiation of the component.

 

BD_0 : NX_BD generic map ( system => “global_lowskew” port map ( I => BUF_IN , O => BUF_OUT );

 

 

 

NX_GCK_U

Description

The NX_GCK_U component describes a configurable ClocK Switch circuit that allows glitch free clock generation. It can be used to enable/disable the clock to part of the user’s logic – providing that the output signal will be glitch free – and the delay from the main clock to the generated one is insignificant.

 

NX_GCK_U can be configured into the following modes:

  • BYPASS: Input signal from lowskew network is copied on output still in lowskew network.

  • MUX: 2 input signals from lowskew network are MUXed with a control command from common network.

  • CKS: Input signal from lowskew network is copied or not, depending on control command from common network, on output still in lowskew network.

  • CSC: Input signal from common network is copied on output in lowskew network.

 

The NX_GCK_U can be used exclusively by instantiation. The current version of NXmap3 does not yet support inference for this device.

 

Generics

 

inv_in

 

type bit

default value ‘0’

 

This generic select wether to invert (inv_in = ‘1’) or not both clock inputs pins SI1 and SI2.

 

inv_out

 

type bit

default value ‘0’

 

This generic select wether to invert (inv_out = ‘1’) or not the clock output pin SO.

 

 

std_mode

 

type string

default value “BYPASS”

 

Select the configuration mode of the NX_GCK_U. NX_GCK_U can be configured into the following modes:

  • BYPASS, where the SO output pin copies the clock input SI1.

  • MUX, where the NX_GCK_U acts as a glitch free clock mux which allow to select with CMD pin either SI1 or SI2 clock signal to broadcast. In MUX mode, CMD=0 => SO=SI2 et CMD=1 => SO=SI1.

  • CKS, where the NX_GCK_U is configured as a clock switch controlled by CMD pin to gate the SI1 input clock to be broadcast or not on SO output. In CKS mode, CMD=0 => SO=0 et CMD=1 => SO=SI1.

  • CSC, where the NX_GCK_U is configured as common to system converter as the CMD input is copied on SO clock output. In CSC mode, SO=CMD.

 

 

Ports

Ports

Direction

Type

Description

Network

SI1

input

std_logic

First Input clock

Lowskew

SI2

input

std_logic

Second Input clock

Lowskew

CMD

Input

Std_logic

Command input

Common

SO

output

std_logic

Output clock

Lowskew

 

Examples

This documentation only provides the instantiation of the component.

 

GCK_0 : NX_GCK_U generic map ( std_mode => “MUX”, inv_in => ‘0’ , inv_out => ‘0’ ) port map ( SI1 => CK1 , SI2 => CK2 , CMD => ENABLE , SO => CKG -- SO <= SI1.CMD or SI2.not(CMD) ); GCK_1 : NX_GCK_U generic map ( std_mode => “MUX”, inv_in => ‘0’ , inv_out => ‘1’ ) port map ( SI1 => CK1 , SI2 => CK2 , CMD => ENABLE , SO => CKG -- SO <= not( SI1.CMD or SI2.not(CMD)) );

 

 

 

NX_CKS

Description

The NX_CKS component describes a ClocK Switch circuit that allows glitch free clock generation. It can be used to enable/disable the clock to part of the user’s logic – providing that the output signal will be glitch free – and the delay from the main clock to the generated one is insignificant. NX_CKS implements and automatically configures a NX_GCK_U primitive in CKS mode.

See Figure 1 for a detailed chronogram.

 

The NX_CKS can be used exclusively by instantiation. The current version of NXmap does not yet support inference for this device.

 

Figure 1: CKS chronograms

 

The blue internal signals are CMD signal sampled on rising edge (SPL1) and then sampled on falling edge (SPL0). SPL0 is the final enable.

Ports

Ports

Direction

Type

Description

CKI

input

std_logic

Input clock

CMD

input

std_logic

Command

CKO

output

std_logic

Output clock

 

Example

This documentation only provides the instantiation of the component.

 

CKS_0 : NX_CKS port map ( CKI => CK , CMD => ENABLE , CKO => CKG );

 

 

 

NX_CMUX

Description

The NX_CMUX component describes a Clock mux circuit that allows glitch free clock selection between two input clock signals. It can be used to enable/disable the clock to part of the user’s logic – providing that the output signal will be glitch free – and the delay from the main clock to the generated one is un-significant. NX_CMUX implements and automatically configures a NX_GCK_U primitive in MUX mode.

 

The NX_CMUX can be used exclusively by instantiation. The current version of NXmap does not yet support inference for this device.

 

 

Ports

Ports

Direction

Type

Description

CKI0

input

std_logic

First Input clock

CKI1

input

std_logic

Second Input clock

SEL

input

std_logic

Select input to choose wether CKO <= CKI0 (SEL=0) or CKO <= CKI1 (SEL=1)

CKO

output

std_logic

Output clock

 

Example

This documentation only provides the instantiation of the component.

 

 

 

 

 

NX_PLL_U

Description

The NX_PLL_U component describes a Phase Locked Loop circuit available in NG-ULTRA with an associated calibration delay module. The PLL just as the WaveForm Generators (WFG) is part of the ClocK Generator block (also called CKG). There are 7 CKG blocks in NG-ULTRA, 4 on in each corner of the FPGA die plus 2 on each side of the SoC and one at the center bottom of the FPGA die.

The calibration feature can be configured or bypassed using the concerned generic parameters.

Each CKG is composed of one PLL, a calibration module and ten WFG:

  • CKG[ 1;5;6;7 ] (CKG top) : 7 WFG_C + 3 WFG_R

  • CKG[ 2;4 ] (CKG bottom left - bottom right) : 6 WFG_C + 4 WFG_R

  • CKG[ 3 ] (CKG bottom middle) : 10 WFG_C

 

 

 

 

 

 

 

 

 

 

 

 

Figure 2: NG-ULTRA CKG block diagram

 

The next figure shows a block diagram of the NX_PLL_U and the user’s settings (in yellow).

Figure 3: Simplified NG-ULTRA PLL block diagram

 

Generics

 

location

 

type string

default value “”

 

This generic allows to define the NX_PLL_U location directly in the source code (instead of using the nxpython addPLLLocation method).

 

Example : location => “CKG2.PLL1”

 

use_pll

 

type bit

default value 0

 

Set to 1 to enable the PLL. When set to 0, the PLL is bypassed with Fvco = Frefo.

 

pll_odf

 

type bit_vector (1 downto 0)

default value others => ‘0’

 

Define the output division factor of the PLL (factors: 1, 2, 5 and 10).

 

pll_odf

Output Division factor

0

1

1

2

2

5

3

10

 

 

pll_lock

 

type bit_vector (1 downto 0)

default value others => ‘0’

 

Configure the frequency lock.

 

pll_lock value

PPM approx

0

20

1

40

2

60

3

80

4

100

5

200

6

400

7

600

8

800

9

1000

10

2000

11

4000

12

6000

13

8000

14

10000

15

20000

 

 

ref_intdiv

 

type bit_vector (4 downto 0)

default value others => ‘0’

 

The REFerence frequency can be divided by factors ranging from 1 to 32 before reaching the VCO input. This allows to give more flexibility of the PLL generated output frequency, and increase the PLL input frequency range.

 

REF input frequency range

ref_intdiv value

Vco input frequency

5 to 50 MHz

0

Fref

10 to 100 MHz

1

Fref / 2

15 to 150 MHz

2

Fref / 3

20 to 200 MHz

3

Fref / 4

…

...

…

150 MHz to 1,5 GHz

29

Fref / 30

155 MHz to 1,55 GHz

30

Fref / 31

160 MHz to 1,6 GHz

31

Fref / 32

 

For VCO expected at 400MHz, ref_intdiv value must be set to 8 with a REF input frequency range between 45 and 450 Mhz.

 

ref_osc_on

 

type bit

default value ‘0’

 

This generic configures the source of the PLL reference.

 

If ref_osc_on is set to ‘0’, the input reference of the pll is the REF input pin.

If set to ‘1’, the internal oscillator is used as reference of the PLL.

 

 

ext_fbk_on

 

type bit

default value ‘0’

 

When ‘0’, the internal feedback path is selected. The output of the FBK_INTDIV divider is used as feedback source. The VCO output frequency is divided by (fbk_intdiv + 1)

When ‘1’, the external feedback path is selected. This is particularly useful for “zero delay” clock generation.

 

 

fbk_intdiv

 

type bit_vector (6 downto 0)

default value others => ‘0’

 

Internal feedback divider of N+1 ratio (with division from 1 to 128).

 

 

fbk_delay_on

 

type bit

default value ‘0’

 

This generic configures whether the delay of the feedback path is active (‘1’) or not (‘0’).

 

 

fbk_delay

 

type bit_vector (5 downto 0)

default value others => ‘0’

 

The number of delay taps on the feedback path (internal or external) can be adjusted to meet the required phase on the VCO outputs. When using external feedback, it can be used to compensate the delay on the reference clock input to the REF pin of the PLL via the semi-dedicated clock input pin and associated direct routing.

The delay can be selected or not (see fbk_delay_on). When selected, it can be adjusted from 340 ps (fbk_delay = 0) to 6740 ps (fbk_delay = 63) by steps of 100 ps.

 

 

clk_outdiv1 : applies to CLK_DIV1

 

type bit_vector (2 downto 0)

default value others => ‘0’

 

This generic allows to define the divider value of the CLK_DIV1 output. There are 8 possible values: 3, 5, 7, 9, 11, 13, 15 and 17 (2*clk_outdiv1+3)

 

If clk_outdiv1 = 0 (default value)

CLK_DIV1 = Fpll/(2*0+3) = Fpll / 3

 

If clk_outdiv1 = 7

CLK_DIV1 = Fpll/(2*7+3) = Fpll / 17

 

 

clk_outdiv2 : applies to CLK_DIV2

 

type bit_vector (2 downto 0)

default value others => ‘0’

 

This generic allows to define the divider value of the CLK_DIV2 output. There are 8 possible values: 5, 7, 9, 11, 13, 15, 17 and 19 (2*clk_outdiv2+5)

 

If clk_outdiv2 = 0 (default value)

CLK_DIV2 = Fpll/(2*0+5) = Fpll / 5

 

If clk_outdiv2 = 7

CLK_DIV2 = Fpll/(2*7+5) = Fpll / 19

 

 

clk_outdiv3 : applies to CLK_DIV3

 

type bit_vector (2 downto 0)

default value others => ‘0’

 

This generic allows to define the divider value of the CLK_DIV3 output. There are 8 possible values: 7, 9, 11, 13, 15, 17, 19 and 21 (2*clk_outdiv3+7)

 

If clk_outdiv3 = 0 (default value)

CLK_DIV3 = Fpll/(2*0+5) = Fpll / 7

 

If clk_outdiv3 = 7

CLK_DIV3 = Fpll/(2*7+5) = Fpll / 21

 

 

clk_outdiv4 : applies to CLK_DIV4

 

type bit_vector (2 downto 0)

default value others => ‘0’

 

This generic allows to define the divider value of the CLK_DIV4 output. There are 8 possible values: 9, 11, 13, 15, 17, 19, 21 and 23 (2*clk_outdiv4+9)

 

If clk_outdiv4 = 0 (default value)

CLK_DIV4 = Fpll/(2*0+5) = Fpll / 9

 

If clk_outdiv4 = 7

CLK_DIV4 = Fpll/(2*7+5) = Fpll / 23

 

 

clk_outdivd* : applies to CLK_DIVD*

 

type bit_vector (3 downto 0)

default value others => ‘0’

 

This generic allows to define the divider value of the CLK_DIVD* output. There are 16 possible values:

 

clk_outdivd*

ratio

Fpll_div_dyn

(ex: Fpll = 800Mhz)

0

2

400

1

4

200

2

6

133.33

3

8

100

4

10

80

5

20

40

6

40

20

7

60

13.33

8

80

10

9

100

8

10

200

4

11

400

2

12

600

1.33

13

800

1

14

1000

0.8

15

2000

0.4

* clk_outdivd1/2/3/4/5 respectively apply to CLK_DIVD1/2/3/4/5

 

 

use_cal

 

type bit

default value ‘0’

 

When set to 0, the calibration module is bypassed. When set to 1, the calibration module is activated with cal_div and cal_delay generics used to define divide and delay values of the calibration engine.

 

clk_cal_sel

 

type bit_vector (1 downto 0)

default value “01”

 

Select the clock used for internal calibration.

 

cal_div

 

type bit_vector (3 downto 0)

default value “0111”

 

Set the division factor of the calibration engine.

 

 

cal_delay

 

type bit_vector (5 downto 0)

default value “011011”

 

Set the delay value of the calibration engine.

 

 

Notes about user’s adjustable delays on NG-ULTRA:

 

The PLL has a user’s selectable and adjustable delay line (no delay or 0 to 63 x 100 ps +/- 5% delay taps) on the feedback path. A similar delay chain is available in each WFGs. Finally, the IO banks have input, output and tri-state command 64-tap delay chains.

All the delay chain taps are calibrated with the same automatic process and hardware resources.

 

The procedure is transparent to the user.

 

The delays calibration system uses the PLL 400 MHz oscillator output as reference clock to calibrate all delays: feedback path in the PLL itself, WFG delays and calibration delay in same CKG), and IO delays in the neighboring complex IO banks:

 

  • CKG1 oscillator calibrates the delays in CKG1 (PLL + CAL+ WFGs)

    • Banks 11 to 13

  • CKG2 oscillator calibrates the delays in CKG2 (PLL + CAL + WFGs)

    • Banks 2 to 3

  • CKG3 oscillator calibrates the delays in CKG3 (PLL + CAL + WFGs)

  • CKG4 oscillator calibrates the delays in CKG4 (PLL + CAL + WFGs)

    • Banks 4 to 5

  • CKG5 oscillator calibrates the delays in CKG5 (PLL + CAL+ WFGs)

Banks 8 to 10

  • CKG6 oscillator calibrates the delays in CKG6 (PLL + CAL+ WFGs)

    • Banks 8 to 10

  • CKG7 oscillator calibrates the delays in CKG7 (PLL + CAL+ WFGs)

    • Banks 11 to 13

 

 

The calibration procedure takes about 10 µs at startup. The “CAL_LOCKED” output goes high when the delay calibration process is complete. Can be used as status bit.

 

 

 

Ports

Ports

Direction

Type

Description

 

REF

 

 

In

 

std_logic

Reference clock input

Connectivity: semi-dedicated clock inputs, clock trees (low skew network)

 

FBK

 

 

In

 

std_logic

External FeedBack input

Connectivity: semi-dedicated clock inputs, clock trees (low skew network)

 

R

 

 

In

 

std_logic

Active high Reset input. Must be activated when REF input frequency changes to force a re-locking process of the PLL

ARST_CAL

In

std_logic

Active high asynchronous reset input of the calibration module

CAL_CLK

In

std_logic

Clock input of the calibration module.

EXT_CAL_LOCKED

In

sdt_logic

Input of the calibration module coming from the fabric. Indicates the calibration is locked

EXT_CAL1/2/3/4/5

In

sdt_logic

Input of the calibration module coming from the fabric. Indicates the calibration value send by fabric

 

VCO

 

 

Out

 

std_logic

 

VCO output:

- Fvco = REF * 2 * (fbk_intdiv+1) / (ref_intdiv+1) with use_pll = 1

- Fvco = Frefo when use_pll = 0

 

 

REFO

 

Out

 

std_logic

Output of the REFerence divider. The division factor is set by the generic “ref_intdiv”

 

 

LDFO

 

Out

 

std_logic

Output of the FBK_INTDIV divider. The division factor is set by the generic ‘fbk_intdiv”

 

 

CLK_DIV1

 

Out

 

std_logic

This output delivers a divided (by 2N+3) PLL frequency or REF frequency (in case PLL is bypassed). The division factor is set by the generic “clk_outdiv1”

 

 

CLK_DIV2

 

Out

 

std_logic

This output delivers a divided (by 2N+5) PLL frequency or REF frequency (in case PLL is bypassed). The division factor is set by the generic “clk_outdiv2”

 

 

CLK_DIV3

 

Out

 

std_logic

This output delivers a divided (by 2N+7) PLL frequency or REF frequency (in case PLL is bypassed). The division factor is set by the generic “clk_outdiv3”

 

 

CLK_DIV4

 

Out

 

std_logic

This output delivers a divided (by 2N+9) PLL frequency or REF frequency (in case PLL is bypassed). The division factor is set by the generic “clk_outdiv4”

 

 

CLK_DIVD1

 

Out

 

std_logic

This output delivers a dynamically divided (by N+2) PLL frequency or REF frequency (in case PLL is bypassed). The division factor is set by the generic “clk_outdivd1”

 

CLK_DIVD2

 

Out

 

std_logic

This output delivers a dynamically divided (by N+2) PLL frequency or REF frequency (in case PLL is bypassed). The division factor is set by the generic “clk_outdivd2”

 

CLK_DIVD3

 

Out

 

std_logic

This output delivers a dynamically divided (by N+2) PLL frequency or REF frequency (in case PLL is bypassed). The division factor is set by the generic “clk_outdivd3”

 

CLK_DIVD4

 

Out

 

std_logic

This output delivers a dynamically divided (by N+2) PLL frequency or REF frequency (in case PLL is bypassed). The division factor is set by the generic “clk_outdivd4”

 

CLK_DIVD5

 

Out

 

std_logic

This output delivers a dynamically divided (by N+2) PLL frequency or REF frequency (in case PLL is bypassed). The division factor is set by the generic “clk_outdivd5”

 

OSC

 

 

Out

 

std_logic

Internal 400 MHz oscillator

Connectivity: WFG inputs, delay calibration engine

 

PLL_LOCKED

 

 

Out

 

std_logic

High when PLL is locked synchronously (fine grain)

Connectivity: RDY inputs of WFGs, fabric…

 

PLL_LOCKEDA

 

 

Out

 

std_logic

High when PLL is locked asynchronously (coarse grain)

Connectivity: RDY inputs of WFGs, fabric…

CLK_CAL_DIV

Out

std_logic

Divided Clock of the calibration module sent to fabric

 

CAL_LOCKED

 

 

Out

 

std_logic

High when the automatic calibration procedure of the current FPGA quarte area is complete

Connectivity: fabric

 

CAL1/2/3/4/5

Out

std_logic

Calibration value sent to fabric

 

Instantiation Example

This documentation only provides the instantiation of the component.

 

Simulation

The NX_PLL VHDL simulation model is included in the NxLibrary (NxPackage.vhd). It allows to simulate any one of the possible NX_PLL configurations.

 

 

 

NX_WFG_U

Description

The NX_WFG_U component is used to access the low skew lines and clock trees on NG-ULTRA. The NX_WFG_U is very similar to the NX_WFG_L of NG-LARGE. The difference is that the NX_WFG_U doesn’t have a RDY pin, only a R pin which can receive any external reset signal from the design and be internally combined with three other different sources of synchronization (coming from PLL lock output signals if one or several of the associated generics (reset_on_pll_lock_n, reset_on_pll_locka_n and reset_on_cal_lock_n) is set to 1. The NX_WFG_U also provides a full set of additional generic parameters.

Among the main WFG features:

  • User’s selectable clock inversion

  • Programmable delay line (0 to 64 taps)

  • Waveform generation by using a 2 to 16-tap user’s defined pattern

  • Waveform generation by using a user’s defined divider up top 1024 and a phase shifting

  • Includes synchronization with other WFG using pattern, in the same ClocK Generator

 

 

 

 

 

 

 

 

 

 

Figure 4: NX_WFG_U diagram

Generics

 

location

 

type string

default value “” (no location constraint)

 

This generic allows to define the NX_WFG_L location directly in the source code (with the addWFGLocation method)

 

Example : location => “CKG2.WFG_C2”,

 

delay

type integer

default value 0

This generic represents the delay line tap count. The value must be in range [0:63] for a tap count in range [1:64].

 

delay_on

type bit

default value ‘0’

This generic configures whether the generated clock is delayed (‘1’) or not (‘0’).

 

mode

type integer range 0 to 2

default value 0

This generic configures whether the generated clock is using the WFG divider ratio mode (2), the WFG pattern mode (1) or the bypass mode (0).

 

 

pattern_end

type integer

default value 0

This generic is used only when mode is set to 1.

This generic configures the last useful index of the sampling pattern. The value must be in range [0:15]. When set to 1 only the 2 first bits of the pattern are used to sample the input clock.

 

pattern

type bit_vector(0 to 15)

default value b”0000000000000000”

This generic is used only when mode is set to 1.

This generic configures the sampling pattern. The pattern is temporal which means the first bit considered if left most one.

For example, with a pattern set to b”1000000000000000” and a pattern_end set to 2, only the first 3 bits of the pattern are considered (“100”) and the input and output clocks chronograms are:

Figure 5: WFG chronograms

 

div_ratio

type integer range 0 to 1023

default value 0

This generic is used only when mode is set to 2.

This generic configures the divider ratio. The output clock is divided by (div_ratio+1).

 

div_phase

type bit

default value ‘0’

This generic is used only when mode is set to 2.

This generic configures the phase. The output clock is shifted by 180° if div_phase is enabled (‘1’) or not shifted if div_phase is disabled (‘0’).

 

reset_on_pll_lock_n

type bit

default value ‘0’

Use asynchronous synchronization source from PLL lock (PLL_LOCKED pin of NX_PLL_U) to feed the reset input of the WFG. Active when set to 1.

 

reset_on_pll_locka_n

type bit

default value ‘0’

Use asynchronous synchronization source from PLL lock analog (PLL_LOCKEDA pin of NX_PLL_U) to feed the reset input of the WFG. Active when set to 1.

 

reset_on_cal_lock_n

type bit

default value ‘0’

Use asynchronous synchronization source from calibration module lock of the PLL (CAL_LOCKED pin of NX_PLL_U) to feed the reset input of the WFG. Active when set to 1.

 

wfg_edge

type bit

default value ‘0’

This generic configures whether the input clock is inverted (‘1’) or not (‘0’). When sampling the input clock, this generic configures whether the sampling is done on rising edge (‘0’) or falling edge (‘1’).

 

 

 

 

 

 

 

 

Ports

Ports

Direction

Type

Description

SI

input

std_logic

Synchronization input (connected to the synchronization output of the master WFG)

ZI

input

std_logic

Input clock (connected to PLL VCO or D1, D2 or D3 output)

R

Input

std_logic

Active High Reset. Can be fed by any signal coming from outside the CKG.

SO

output

std_logic

Synchronization output (Master WFG SO output is connected to all slave WFGs SI inputs)

ZO

output

std_logic

Generated clock (connected to clock tree)

 

When sampling the input clock, the synchronization input must be connected either to another WFG (using pattern) synchronization output or the synchronization output of the WFG itself.

 

Example

This documentation only provides the instantiation of the component.

 

 

 

Simulation

The NX_WFG_U VHDL simulation model is included in the NxLibrary (NxPackage.vhd). It allows to simulate any one of the possible NX_WFG_U configurations.

 

 

 

 

Core logic

NX_CY (!)

(!) : Important note : on nxmap3, the NX_CY primitive includes only the dedicated arithmetic logic, excluding the Functional Element LUTs and FFs – unlike on nxmap2, where the NX_CY primitive included the FE logic shown in dashed lines.

 

Description

The NX_ADD component describes a 4-bit adder and carry look ahead circuit. It’s available on the FEs having arithmetic logic capabilities.

The NX_ADD is composed of 4 stages numbered from 1 to 4 where 1 represents the LSB.

 

 

Figure 6: NX_ADD diagram

Generics

add_carry

type integer range 0 to 2

default value 0

This generic represents the way the CI (carry in) port is connected: 0 is for low, 1 for high and 2 for propagate which means it is connected to the previous NX_CY CO (carry out) port.

 

Ports

Ports

Direction

Type

Description

A[1:4]

input

std_logic

A input of each stage

BI[1:4]

input

std_logic

B input of each stage

CI

input

std_logic

Carry input

CO

output

std_logic

Carry output

S[1:4]

output

std_logic

Output of each stage

Example

This documentation only provides the instantiation of the component..

 

 

NX_LUT

Description

The NX_LUT component describes a 4-input LUT as part of a functional element (FE) as shown in the following diagram:

 

 

Figure 7: NX_LUT diagram

Generics

lut_table

type bit_vector(15 downto 0)

default value b“0000000000000000”

This generic represents the truth table of the associated LUT. The string representing the truth table is MSB ordered (“b(15), b(14),...b(1), b(0)”) and b(15) to b(0) are defined as in the following table:

 

I4

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

I3

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

I2

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

I1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

O

b(15)

b(14)

b(13)

b(12)

b(11)

b(10)

b(9)

b(8)

b(7)

b(6)

b(5)

b(4)

b(3)

b(2)

b(1)

b(0)

 

Lut_table examples for common 4-input functions:

  • I4 and I3 and I2 and I1 => lut_table = b“1000000000000000” (or x”8000”)

  • I4 or I3 or I2 or I1 => lut_table = b“1111111111111110” (or x”FFFE”)

  • (I4 and I3) xor (I2 and I1) => lut_table = x”0111 1000 1000 1000” (or x”7888”)

 

Ports

Ports

Direction

Type

Description

I[1:4]

input

std_logic

LUT inputs

O

output

std_logic

Output

 

Example

This documentation only provides the instantiation of the component.

 

 

NX_DFF

Description

The NX_DFF component describes a DFF of the functional elements as shown in the following diagram:

Figure 8: NX_DFF diagram

 

Generics

dff_ctxt

type std_logic

default value ‘U’

This generic represents the initial value of the associated DFF. The initial value is set by bitstream. The available values are: ‘U’ for undefined (no value set in bitstream), ‘0’ for low and ‘1’ for high.

 

dff_edge

type bit

default value ‘0’

This generic represents the front polarity of the clock of the associated DFF. ‘0’ is for rising edge and ‘1’ for falling edge.

 

dff_init

type bit

default value ‘0’

This generic represents whether the DFF considers the R (reset) input. ‘0’ is for ignore and ‘1’ for using connected net.

 

dff_load

type bit

default value ‘0’

This generic represents whether the DFF considers the L (load) input. ‘0’ is for ignore and ‘1’ for using connected net.

 

dff_sync

type bit

default value ‘0’

This generic represents whether the DFF reset is synchronous or asynchronous. ‘0’ is for asynchronous and ‘1’ for synchronous.

 

dff_type

type bit

default value 0

This generic represents whether the reset must initialize the DFF to 0 or 1. dff_type is set to ‘0’ for reset initializing the DFF to 0, dff_type is set to ‘1’ for reset initializing the DFF to 1. dff_type can also be set to 2 to configure set/reset on signal.

 

Ports

Ports

Direction

Type

Description

I

input

std_logic

Input

CK

input

std_logic

Clock

L

input

std_logic

Load

R

input

std_logic

Reset, active high

O

output

std_logic

Output

 

Example

This documentation only provides the instantiation of the component.

 

 

NX_FIFO_U

Description

 

The NX_FIFO_U component provides a combination of two Register File Blocks circuit used as a base component for dedicated NX IPs defined for FIFO configuration of the RF with CDC (clock domain crossing) features: DPREG, XFIFO_64x18 (extended number of words) and 2 for XFIFO_32x36 (extended word size). Note that dedicated hard IPs are available for specific FIFO configurations : NX_XFIFO_64x18 and NX_XFIFO_32x36

 

 

 

 

Generics

wck_edge

type bit

default value ‘0’

This generic represents the front polarity of the WCK clock. ‘0’ is for rising edge and ‘1’ for falling edge.

 

rck_edge

type bit

default value ‘0’

This generic represents the front polarity of the RCK clock. ‘0’ is for rising edge and ‘1’ for falling edge.

 

use_write_arst

type bit

default value ‘0’

This generic enables the use of asynchronous reset on write interface if set to 1.

 

use_read_arst

type bit

default value ‘0’

This generic enables the use of asynchronous reset on read interface if set to 1.

 

read_addr_inv

type bit_vector(6 downto 0)

default value “0000000”

 

mode

type integer

default value 0

This generic defines the desired FIFO configuration among: 0 for DPREG, 1 for XFIFO_64x18 (extended number of words) and 2 for XFIFO_32x36 (extended word size).

 

Ports

Ports

Direction

Type

Description

RCK

input

std_logic

Read clock

WCK

input

std_logic

Write clock

I1 to I36

input

std_logic

Write data (2x18 input bits)

O1 to O36

output

std_logic

Read Data (2x18 output bits)

WRSTI

input

std_logic

Reset from the write clock domain. Active High

RRSTI

input

std_logic

Reset from the read clock domain. Active High

RAI1 to RAI7

input

std_logic

Read pointer from read clock domain

RAO1 to RAO7

output

std_logic

Read pointer to write clock domain

WAI1 to WAI7

input

std_logic

Write pointer from write clock domain

WAO1 to WAO7

output

std_logic

Write pointer to read clock domain

WE

input

std_logic

Write enable

WEA

input

std_logic

Write enable all (we in all registers)

WEQ1 to WEQ2

output

std_logic

Comparison of read/write pointers in write clock domain

REQ1 to REQ2

output

std_logic

Comparison of read/write pointers in read clock domain

 

NX_FIFO_DPREG

Description

 

The NX_FIFO_DPREG is a wrapper component around NX_FIFO_U to have bus interfaces instead of bit to bit signals and defining a 32x18 DPREG configuration based on RF implementation.

 

 

Generics

wck_edge

type bit

default value ‘0’

This generic represents the front polarity of the WCK clock. ‘0’ is for rising edge and ‘1’ for falling edge.

 

rck_edge

type bit

default value ‘0’

This generic represents the front polarity of the RCK clock. ‘0’ is for rising edge and ‘1’ for falling edge.

 

use_write_arst

type bit

default value ‘0’

This generic enables the use of asynchronous reset on write interface if set to 1.

 

use_read_arst

type bit

default value ‘0’

This generic enables the use of asynchronous reset on read interface if set to 1.

 

read_addr_inv

type bit_vector(5 downto 0)

default value “000000”

 

 

Ports

Ports

Direction

Type

Description

RCK

input

std_logic

Read clock

WCK

input

std_logic

Write clock

I

input

std_logic_vector (17 downto 0)

Write data

O

output

std_logic_vector (17 downto 0)

Read Data

WRSTI

input

std_logic

Reset from the write clock domain. Active High

RRSTI

input

std_logic

Reset from the read clock domain. Active High

RAI

input

std_logic_vector (5 downto 0)

Read pointer from read clock domain

RAO

output

std_logic_vector (5 downto 0)

Read pointer to write clock domain

WAI

input

std_logic_vector (5 downto 0)

Write pointer from write clock domain

WAO

output

std_logic_vector (5 downto 0)

Write pointer to read clock domain

WE

input

std_logic

Write enable

WEA

input

std_logic

Write enable all (we in all registers)

WEQ

output

std_logic

Comparison of read/write pointers in write clock domain

REQ

output

std_logic

Comparison of read/write pointers in read clock domain

 

NX_XFIFO_64x18

Description

 

The NX_XFIFO_64x18 provides a direct hard IP configuration for a memory based on register file elements made of 64 words of 18 bits using the NX_FIFO_U component.

 

 

 

Generics

wck_edge

type bit

default value ‘0’

This generic represents the front polarity of the WCK clock. ‘0’ is for rising edge and ‘1’ for falling edge.

 

rck_edge

type bit

default value ‘0’

This generic represents the front polarity of the RCK clock. ‘0’ is for rising edge and ‘1’ for falling edge.

 

use_write_arst

type bit

default value ‘0’

This generic enables the use of asynchronous reset on write interface if set to 1.

 

use_read_arst

type bit

default value ‘0’

This generic enables the use of asynchronous reset on read interface if set to 1.

 

read_addr_inv

type bit_vector(6 downto 0)

default value “0000000”

 

Ports

Ports

Direction

Type

Description

RCK

input

std_logic

Read clock

WCK

input

std_logic

Write clock

I

input

std_logic_vector (17 downto 0)

Write data bus

O

output

std_logic_vector (17 downto 0)

Read Data

WRSTI

input

std_logic

Reset from the write clock domain. Active High

RRSTI

input

std_logic

Reset from the read clock domain. Active High

RAI

input

std_logic_vector (6 downto 0)

Read pointer from read clock domain

RAO

output

std_logic_vector (6 downto 0)

Read pointer to write clock domain

WAI

input

std_logic_vector (6 downto 0)

Write pointer from write clock domain

WAO

output

std_logic_vector (17 downto 0)

Write pointer to read clock domain

WE

input

std_logic

Write enable

WEA

input

std_logic

Write enable all (we in all registers)

WEQ

output

std_logic_vector (1 downto 0)

Comparison of read/write pointers in write clock domain

REQ

output

std_logic_vector (1 downto 0)

Comparison of read/write pointers in read clock domain

 

NX_XFIFO_32x36

Description

 

The NX_XFIFO_32x36 provides a direct hard IP configuration for a memory based on register file elements made of 32 words of 36 bits using the NX_FIFO_U component.

 

 

 

Generics

wck_edge

type bit

default value ‘0’

This generic represents the front polarity of the WCK clock. ‘0’ is for rising edge and ‘1’ for falling edge.

 

rck_edge

type bit

default value ‘0’

This generic represents the front polarity of the RCK clock. ‘0’ is for rising edge and ‘1’ for falling edge.

 

use_write_arst

type bit

default value ‘0’

This generic enables the use of asynchronous reset on write interface if set to 1.

 

use_read_arst

type bit

default value ‘0’

This generic enables the use of asynchronous reset on read interface if set to 1.

 

read_addr_inv

type bit_vector(6 downto 0)

default value “0000000”

 

Ports

Ports

Direction

Type

Description

RCK

input

std_logic

Read clock

WCK

input

std_logic

Write clock

I

input

std_logic_vector (35 downto 0)

Write data bus

O

output

std_logic_vector (35 downto 0)

Read Data

WRSTI

input

std_logic

Reset from the write clock domain. Active High

RRSTI

input

std_logic

Reset from the read clock domain. Active High

RAI

input

std_logic_vector (5 downto 0)

Read pointer from read clock domain

RAO

output

std_logic_vector (5 downto 0)

Read pointer to write clock domain

WAI

input

std_logic_vector (5 downto 0)

Write pointer from write clock domain

WAO

output

std_logic_vector (5 downto 0)

Write pointer to read clock domain

WE

input

std_logic

Write enable

WEA

input

std_logic

Write enable all (we in all registers)

WEQ

output

std_logic

Comparison of read/write pointers in write clock domain

REQ

output

std_logic

Comparison of read/write pointers in read clock domain

 

 

NX_RFB_U

Description

 

Each TILE of NG-Ultra implements two Simple Dual Port memory of 32 words of 18-bit (one port is dedicated to write, the second port is dedicated to read) which can be combined to form deeper or larger memories.

 

The NX_RFB_U component provides a Register File Block circuit which combine the interfaces of two Simple Dual Port memory of 32 words of 18-bit, and which is used as a base component for dedicated NX IPs defined for each possible configuration of the RF: DPREG, SPREG, XRF_64x18 (Extended RF using both 32x18 RF for extended word size memory), XRF_32x36 (Extended RF using both 32x18 RF for extended bit length memory) and XRF_2R_1W (configuration as a RF with 2 read ports and 1 write port).

 

 

The nxmap nxLibrary-Ultra.vhdp defines several dedicated NX IP models, instantiating NX_RFB_U component, for each of the above configurations.

 

Figure 9: 32x18 RF implemented in a TILE of NG-Ultra

 

The Register_File block is made of:

  • 32 FEs

  • One 32 x 18-bit Simple Dual Port RAM

 

Associated FE usage :

 

If the Register_File is not used, all the 32 FEs are free to be used to implement user’s logic

 

  • If the Register_File is used, up to 30 inputs will reach the 32 x 18 RAM array by crossing LUTs, and 2 additional LUTs will be used for internal configuration purpose

    • 1 LUT for Write_Enable (with potential 4-input decoder)

    • 1 LUT for Write_Enable_all (with potential 4-input decoder)

    • 5 LUTs for Write_Address

    • 5 LUTs for Read_Address

    • 18 LUTs for Data_In

    • 2 additional LUTs for RF internal configuration

 

Using the whole RAM array (32 x 18) requires using 32 LUTs of the same tile section.

The LUTs can implement optional customer logic, for example

  • Implement simple decoding functions for Write_Enable or Write_Enable_all

  • Address/Data multiplexers to implement time multiplexed two write ports and/or two read ports (not yet supported by NXmap)

(see NXmap related notes for more details)

 

  • If the Register_File is used and configured with optional output pipeline registers, those registers can be implemented with FE Flip-Flops of the same tile section (Up to 18 FFs for Data_out)

  • If the Register_File is partially used (for example as 32 x 10 SDP RAM), the remaining 8 FEs will stay free to implement other unrelated logic functions)

 

 

NXmap support:

The current version of NXmap supports the implementation of simple decoders on the Write_Enable and Read_Enable commands paths (the Register_File must be instantiated).

LUTs are used as transparent for data inputs as well as read and write addresses (both inference and instantiation).

Future versions of NXmap will support higher flexibility such as multiplexers and other simple combinatorial function on the data and address input paths.

 

 

Generics

wck_edge

type bit

default value ‘0’

This generic represents the front polarity of the WCK clock. ‘0’ is for rising edge and ‘1’ for falling edge.

 

mem_ctxt

type string

default value “”

This generic represents the initial value of the RFB. The initial value is set by bitstream. The string contains a list of all complete bit words separated by coma.

When a word size is less than 18 bits or when number of words is less than 32, an error occurs.

When a word size exceeds 18 bits or when the number of words exceeds 32, an error occurs.

 

mode

type integer

default value 0

This generic defines the desired RF configuration: 0 for DPREG, 1 for SPREG, 2 for XRF_64x18, 3 for XRF_32x36 and 4 for XRF_2R_1W.

 

Ports

Ports

Direction

Type

Description

WCK

input

std_logic

Write clock

I1 to I36

input

std_logic

Data input (2x18 input bits)

O1 to O36

output

std_logic

Data output (2x18 output bits)

RA1 to RA10

input

std_logic

Read address (2x5 input bits)

WA1 to WA6

input

std_logic

Write address

WE

input

std_logic

Write enable

WEA

input

std_logic

Write enable all (we in all registers)

 

Instantiation Example

This documentation only provides the instantiation of the component.

 

NX_XRFB_64x18

Description

 

The NX_XRFB_64x18 implements a configured DPREG of 64 words of 18 bits with write clock edge configuration, using NX_RFB_U component, and providing compact vector interfaces for user convenience.

 

Generics

wck_edge

type bit

default value ‘0’

This generic represents the front polarity of the WCK clock. ‘0’ is for rising edge and ‘1’ for falling edge.

 

mem_ctxt

type string

default value “”

This generic represents the initial value of the NX_XRFB_64x18. The initial value is set by bitstream. The string contains a list of all complete bit words separated by coma.

When a word size is less than 18 bits or when number of words is less than 64, an error occurs.

When a word size exceeds 18 bits or when the number of words exceeds 64, an error occurs.

 

Ports

Ports

Direction

Type

Description

WCK

input

std_logic

Write clock

I[17:0]

input

std_logic_vector

Data input

O[17:0]

output

std_logic_vector

Data output

RA[5:0]

input

std_logic_vector

Read address

WA[5:0]

input

std_logic_vector

Write address

WE

input

std_logic

Write enable

WEA

input

std_logic

Write enable all registers

 

Instantiation Example

This documentation only provides the instantiation of the component.

 

NX_XRFB_32x36

Description

 

The NX_XRFB_32x36 implements a configured DPREG of 32 words of 36 bits (combining both Register files of a TILE) with write clock edge configuration, using NX_RFB_U component, and providing compact vector interfaces for user convenience.

 

Generics

wck_edge

type bit

default value ‘0’

This generic represents the front polarity of the WCK clock. ‘0’ is for rising edge and ‘1’ for falling edge.

 

mem_ctxt

type string

default value “”

This generic represents the initial value of the NX_XRFB_32x36. The initial value is set by bitstream. The string contains a list of all complete bit words separated by coma.

When a word size is less than 36 bits or when number of words is less than 32, an error occurs.

When a word size exceeds 36 bits or when the number of words exceeds 32, an error occurs.

 

Ports

Ports

Direction

Type

Description

WCK

input

std_logic

Write clock

I[35:0]

input

std_logic_vector

Data input

O[35:0]

output

std_logic_vector

Data output

RA[4:0]

input

std_logic_vector

Read address

WA[4:0]

input

std_logic_vector

Write address

WE

input

std_logic

Write enable

WEA

input

std_logic

Write enable all registers

 

NX_XRFB_2R_1W

Description

 

The NX_XRFB_2R_1W implements a Register File configured with two read ports of 18 bits each and one write port of 18 bits with write clock edge configuration, using NX_RFB_U component, and providing compact vector interfaces for user convenience.

 

Generics

wck_edge

type bit

default value ‘0’

This generic represents the front polarity of the WCK clock. ‘0’ is for rising edge and ‘1’ for falling edge.

 

mem_ctxt

type string

default value “”

This generic represents the initial value of the NX_XRFB_2R_1W. The initial value is set by bitstream. The string contains a list of all complete bit words separated by coma.

When a word size is less than 18 bits or when number of words is less than 32, an error occurs.

When a word size exceeds 18 bits or when the number of words exceeds 32, an error occurs.

 

Ports

Ports

Direction

Type

Description

WCK

input

std_logic

Write clock

I[17:0]

input

std_logic_vector

Data input write port

A0[17:0]

output

std_logic_vector

Data output first read port

B0[17:0]

output

std_logic_vector

Data output second read port

ARA[4:0]

input

std_logic_vector

Read address for first port

BRA[4:0]

input

std_logic_vector

Read address for second port

WA[4:0]

input

std_logic_vector

Write address

WE

input

std_logic

Write enable

WEA

input

std_logic

Write enable all registers

 

NX_RFBSP_U_WRAP

Description

 

The NX_RFBSP_U_WRAP implements a 32x18 Register File configured with a single write/read port.

 

Generics

wck_edge

type bit

default value ‘0’

This generic represents the front polarity of the WCK clock. ‘0’ is for rising edge and ‘1’ for falling edge.

 

mem_ctxt

type string

default value “”

This generic represents the initial value of the NX_RFBSP_U_WRAP. The initial value is set by bitstream. The string contains a list of all complete bit words separated by coma.

When a word size is less than 18 bits or when number of words is less than 32, an error occurs.

When a word size exceeds 18 bits or when the number of words exceeds 32, an error occurs.

 

Ports

Ports

Direction

Type

Description

WCK

input

std_logic

Write clock

I[17:0]

input

std_logic_vector

Data input write port

0[17:0]

output

std_logic_vector

Data output first read port

WA[4:0]

input

std_logic_vector

Write address

WE

input

std_logic

Write enable

WEA

input

std_logic

Write enable all registers

 

NX_CDC_U_2DFF

Description

The NX_CDC_U_2DFF component describes a CDC (Clock Domain Crossing) module that transmits data between two clock domains CK0 and CK1. The data provided on ports A and B in source clock domain are synchronized in destination clock domain with two pipe registers.

 

Generics

ck0_edge

type bit

default value ‘0’

This generic represents the front polarity of the CK1 clock. ‘0’ is for rising edge and ‘1’ for falling edge.

 

ck1_edge

type bit

default value ‘0’

This generic represents the front polarity of the CK2 clock. ‘0’ is for rising edge and ‘1’ for falling edge.

 

ack_sel

type bit

default value ‘0’

This generic enables clock for port A used for clock domain crossing when set to ‘1’.

 

bck_sel

type bit

default value ‘0’

This generic enables clock for port B used for clock domain crossing when set to ‘1’.

 

use_adest_arst

type bit

default value ‘0’

This generic allows to use destination reset connected to ADRSTO output when set to ‘1’ in order to reset the data destination pipe registers.

 

use_bdest_arst

type bit

default value ‘0’

This generic allows to use destination reset connected to BDRSTO output when set to ‘1’.

 

Ports

Ports

Direction

Type

Description

CK1

input

std_logic

Reference clock 0

CK2

input

std_logic

Reference clock 1

ADRSTI

input

std_logic

Asynchronous reset related to port A used for destination synchronization pipe registers. Active high.

ADRSTO

output

std_logic

Asynchronous destination reset related to port A synchronized in destination clock domain. Active high.

AI

intput

std_logic_vector (5 downto 0)

Data input port A on source clock domain

AO

output

std_logic_vector (5 downto 0)

Data output port A on destination clock domain

BDRSTI

input

std_logic

Asynchronous destination reset related to port B used for destination synchronization pipe registers. Active high.

BDRSTO

output

std_logic

Asynchronous destination reset related to port B synchronized in destination clock domain. Active high.

BI

intput

std_logic_vector (5 downto 0)

Data input port B on source clock domain

BO

output

std_logic_vector (5 downto 0)

Data output port B on destination clock domain

 

NX_CDC_U_3DFF

Description

The NX_CDC_U_3DFF component describes a CDC (Clock Domain Crossing) module that transmits data between two clock domains CK0 and CK1. The data provided on ports A and B are registered in source clock domain with one pipe register and the synchronization of these data is done in destination clock domain with two pipe registers.

 

Generics

ck0_edge

type bit

default value ‘0’

This generic represents the front polarity of the CK1 clock. ‘0’ is for rising edge and ‘1’ for falling edge.

 

ck1_edge

type bit

default value ‘0’

This generic represents the front polarity of the CK2 clock. ‘0’ is for rising edge and ‘1’ for falling edge.

 

ack_sel

type bit

default value ‘0’

This generic enables clock for port A used for clock domain crossing when set to ‘1’.

 

bck_sel

type bit

default value ‘0’

This generic enables clock for port B used for clock domain crossing when set to ‘1’.

 

use_asrc_arst

type bit

default value ‘0’

This generic allows to use source reset connected to ASRSTO input when set to ‘1’ in order to reset the data source pipe register.

 

use_adest_arst

type bit

default value ‘0’

This generic allows to use destination reset connected to ADRSTO output when set to ‘1’ in order to reset the data destination pipe registers.

 

use_bsrc_arst

type bit

default value ‘0’

This generic allows to use source reset connected to ASRSTO input when set to ‘1’ in order to reset the data source pipe register.

 

use_bdest_arst

type bit

default value ‘0’

This generic allows to use destination reset connected to BDRSTO output when set to ‘1’ in order to reset the data destination pipe registers.

 

Ports

Ports

Direction

Type

Description

CK1

input

std_logic

Reference clock 0

CK2

input

std_logic

Reference clock 1

ASRSTI

input

std_logic

Asynchronous reset related to port A used for source pipe register. Active high.

ADRSTI

input

std_logic

Asynchronous reset related to port A used for destination synchronization pipe registers. Active high.

ASRSTO

output

std_logic

Asynchronous source reset related to port A synchronized in destination clock domain. Active high.

ADRSTO

output

std_logic

Asynchronous destination reset related to port A synchronized in destination clock domain. Active high.

AI

intput

std_logic_vector (5 downto 0)

Data input port A on source clock domain

AO

output

std_logic_vector (5 downto 0)

Data output port A on destination clock domain

BSRSTI

input

std_logic

Asynchronous reset related to port B used for source pipe register. Active high.

BDRSTI

input

std_logic

Asynchronous reset related to port B used for destination synchronization pipe registers. Active high.

BSRSTO

output

std_logic

Asynchronous source reset related to port B synchronized in destination clock domain. Active high.

BDRSTO

output

std_logic

Asynchronous destination reset related to port B synchronized in destination clock domain. Active high.

BI

intput

std_logic_vector (5 downto 0)

Data input port B on source clock domain

BO

output

std_logic_vector (5 downto 0)

Data output port B on destination clock domain

 

NX_CDC_U_BIN2GRAY

Description

The NX_CDC_U_BIN2GRAY component describes a hard IP that can be used before NX_CDC_U_2DFF and NX_CDC_U_3DFF clock domain crossing modules in order to translate the input data in ports A and B from binary to gray representation.

 

Ports

Ports

Direction

Type

Description

AI

intput

std_logic_vector (5 downto 0)

Data input port A on binary representation

AO

output

std_logic_vector (5 downto 0)

Data output port A on gray representation

BI

intput

std_logic_vector (5 downto 0)

Data input port B on binary representation

BO

output

std_logic_vector (5 downto 0)

Data output port B on gray representation

 

 

NX_CDC_U_GRAY2BIN

Description

The NX_CDC_U_GRAY2BIN component describes a hard IP that can be used before NX_CDC_U_2DFF and NX_CDC_U_3DFF clock domain crossing modules in order to translate the input data in ports A and B from gray to binary representation.

 

Ports

Ports

Direction

Type

Description

AI

intput

std_logic_vector (5 downto 0)

Data input port A on gray representation

AO

output

std_logic_vector (5 downto 0)

Data output port A on binary representation

BI

intput

std_logic_vector (5 downto 0)

Data input port B on gray representation

BO

output

std_logic_vector (5 downto 0)

Data output port B on binary representation

 

 

NX_XCDC_U

Description

The NX_XCDC_U component implements a fully external CDC (Clock Domain Crossing) module that transmits data between two clock domains CK1 and CK2 for 4 data ports A, B, C and D. The data provided on ports A, B, C and D are registered in source clock domain with one pipe register and the synchronization of these data is done in destination clock domain with two pipe registers.

 

Generics

ck0_edge

type bit

default value ‘0’

This generic represents the front polarity of the CK1 clock. ‘0’ is for rising edge and ‘1’ for falling edge.

 

ck1_edge

type bit

default value ‘0’

This generic represents the front polarity of the CK2 clock. ‘0’ is for rising edge and ‘1’ for falling edge.

 

ack_sel

type bit

default value ‘0’

This generic enables clock for port A used for clock domain crossing when set to ‘1’.

 

bck_sel

type bit

default value ‘0’

This generic enables clock for port B used for clock domain crossing when set to ‘1’.

 

cck_sel

type bit

default value ‘0’

This generic enables clock for port C used for clock domain crossing when set to ‘1’.

 

dck_sel

type bit

default value ‘0’

This generic enables clock for port D used for clock domain crossing when set to ‘1’.

 

use_asrc_arst

type bit

default value ‘0’

This generic allows to use source reset connected to ASRSTO input when set to ‘1’ in order to reset the data source pipe register.

 

use_adest_arst

type bit

default value ‘0’

This generic allows to use destination reset connected to ADRSTO output when set to ‘1’ in order to reset the data destination pipe registers.

 

use_bsrc_arst

type bit

default value ‘0’

This generic allows to use source reset connected to ASRSTO input when set to ‘1’ in order to reset the data source pipe register.

 

use_bdest_arst

type bit

default value ‘0’

This generic allows to use destination reset connected to BDRSTO output when set to ‘1’ in order to reset the data destination pipe registers.

 

use_csrc_arst

type bit

default value ‘0’

This generic allows to use source reset connected to CSRSTO input when set to ‘1’ in order to reset the data source pipe register.

 

use_cdest_arst

type bit

default value ‘0’

This generic allows to use destination reset connected to CDRSTO output when set to ‘1’ in order to reset the data destination pipe registers.

 

use_dsrc_arst

type bit

default value ‘0’

This generic allows to use source reset connected to DSRSTO input when set to ‘1’ in order to reset the data source pipe register.

 

use_ddest_arst

type bit

default value ‘0’

This generic allows to use destination reset connected to DDRSTO output when set to ‘1’ in order to reset the data destination pipe registers.

 

Ports

Ports

Direction

Type

Description

CK1

input

std_logic

Reference clock 0

CK2

input

std_logic

Reference clock 1

ASRSTI

input

std_logic

Asynchronous reset related to port A used for source pipe register. Active high.

ADRSTI

input

std_logic

Asynchronous reset related to port A used for destination synchronization pipe registers. Active high.

ASRSTO

output

std_logic

Asynchronous source reset related to port A synchronized in destination clock domain. Active high.

ADRSTO

output

std_logic

Asynchronous destination reset related to port A synchronized in destination clock domain. Active high.

AI

intput

std_logic_vector (5 downto 0)

Data input port A on source clock domain

AO

output

std_logic_vector (5 downto 0)

Data output port A on destination clock domain

BSRSTI

input

std_logic

Asynchronous reset related to port B used for source pipe register. Active high.

BDRSTI

input

std_logic

Asynchronous reset related to port B used for destination synchronization pipe registers. Active high.

BSRSTO

output

std_logic

Asynchronous source reset related to port B synchronized in destination clock domain. Active high.

BDRSTO

output

std_logic

Asynchronous destination reset related to port B synchronized in destination clock domain. Active high.

BI

intput

std_logic_vector (5 downto 0)

Data input port B on source clock domain

BO

output

std_logic_vector (5 downto 0)

Data output port B on destination clock domain

CSRSTI

input

std_logic

Asynchronous reset related to port C used for source pipe register. Active high.

CDRSTI

input

std_logic

Asynchronous reset related to port C used for destination synchronization pipe registers. Active high.

CSRSTO

output

std_logic

Asynchronous source reset related to port C synchronized in destination clock domain. Active high.

CDRSTO

output

std_logic

Asynchronous destination reset related to port C synchronized in destination clock domain. Active high.

CI

intput

std_logic_vector (5 downto 0)

Data input port C on source clock domain

CO

output

std_logic_vector (5 downto 0)

Data output port C on destination clock domain

DSRSTI

input

std_logic

Asynchronous reset related to port D used for source pipe register. Active high.

DDRSTI

input

std_logic

Asynchronous reset related to port D used for destination synchronization pipe registers. Active high.

DSRSTO

output

std_logic

Asynchronous source reset related to port D synchronized in destination clock domain. Active high.

DDRSTO

output

std_logic

Asynchronous destination reset related to port D synchronized in destination clock domain. Active high.

DI

intput

std_logic_vector (5 downto 0)

Data input port D on source clock domain

DO

output

std_logic_vector (5 downto 0)

Data output port D on destination clock domain



NX_DSP_U

Description

The NX_DSP_U component describes a Digital Signal Processor circuit that allows implementation of arithmetic computations such as multiply, add/subtract.

The NX_DSP_U interface is very similar to the NX_DSP_L interface available on NG-LARGE, with the following differences :

  • CO43 output usedon NG-ULTRA instead of CO37 used on NG-LARGE

  • CONCAT bloc is computed by A & B operand order instead of B & A

  • Substraction is computed with 42 bits long instead of 36

  • Addition can be computed on 42 bits long (but still on 36 bits too)

  • Operands X and Y are inverted in ALU.

 

Figure 10: DSP simplified block diagram

 

The NX_DSP_U registers can be reset using two dedicated input pins:

  • the reset R pin which will reset all registers (input, internal and output registers) except the cascaded output registers PR_CZ and PR_CCO.

  • the reset RZ pin which will reset only the cascaded output registers PR_CZ and PR_CCO.

  • the write enable WE pin which will reset all registers (input, internal and cascaded registers) except the output registers PR_Z, PR_OVF and PR_CO.

  • the write enable WEZ pin which will reset only the output registers PR_Z, PR_OVF and PR_CO.

 



Generics

std_mode

type string

default value “”

This generic represents the predefined operating mode of the DSP. When empty the operating mode is defined by the 4 raw_config generics.

The available predefined modes are:

  • “ADD_42” → 42 bits addition

  • “SUB_42” → 42 bits substraction

  • “SMUL_18” → 18 bits signed multiplication

  • “UMUL_18” → 18 bits unsigned multiplication

  • “UMUL24x18_1DSP” → 24x18 bits unsigned multiplication using 1 DSP

  • “UMADD18_1DSP” → 24x18 bits unsigned multiplication and addition using 1 DSP

  • “UMACC18_1DSP” → 18 bits unsigned multiplication and accumulation using 1 DSP

  • “UAMADD18_1DSP” → 18 bits unsigned multiplication and addition with pre-adder

operations using 1 DSP

“ADD84_1DSP_2CYCLES” → 84 bits addition on 2 cycles using 1 DSP

 

When using one of these predefined modes, the 4 raw_config generics are defined as follow:

 

std_mode

Raw config0

Raw config1

Raw config2

Raw config3

ADD_42

000000000000001001000000000

000000000000000000000000

00000000000000

000

SUB_42

000000000000001001000000000

000000000000000000000000

00000000000000

001

SMUL_18

000000000000000000000000001

000000000000000000000000

00000000000000

000

UMUL_18

000000000000000000000000000

000000000000000000000000

00000000000000

000

UMUL24x18_1DSP

000000000000000000000000000

000000010000000000010001

00010000000011

000

UMADD18_1DSP

000000000000001000000100000

000000010110001100010001

00010011001111

000

UMACC18_1DSP

000000000000001000101100000

000000010110001100010001

00010011001111

000

UAMADD18_1DSP

000000000000001000000110010

000000010010111100010011

00010101101111

000

ADD84_1DSP_2CYCLES

000010000000001011000000000

000000010001001100010001

00010000011111

000

 

 

raw_config0

type bit_vector(26 downto 0)

default value b“000000000000000000000000000”

This generic configures the following fields:

Name

Index

Description

INV_WE

26

Invert write enable on input/internal registers:

‘0’ : do not invert

‘1’ : invert

INV_WEZ

25

Invert write enable on cascaded output register:

‘0’ : do not invert

‘1’ : invert

INV_RST

24

Invert reset on input/internal registers:

‘0’ : do not invert

‘1’ : invert

INV_RSTZ

23

Invert reset on cascaded output register:

‘0’ : do not invert

‘1’ : invert

MUX_CCO

22

Carry out MUX

‘0’ : Select CO43

‘1’ : Select CO57

ALU_DYNAMIC_OP

21:20

ALU Dynamic Operation

‘00’: static operation

‘x1’: dynamic control from C operand

‘10’: dynamic control from D operand

SATURATION_RANK

19:14

MSB position for saturation and overflow

Signed : “100000” for range -2**31 to (2**31)-1

Unsigned : “100000” for range 0 to (2**32)-1

Max value = “110111” (55)

ENABLE_SATURATION

13

‘0’: disable, ‘1’: enable

MUX_Z

12

Selection for Z output

‘0’ : PR_Y

‘1’ : ALU

MUX_CCI

11

Carry cascade in MUX

‘0’ : CCYI cascade input

‘1’ : CCYO cascade output

MUX_CI

10

Carry in MUX

‘0’ : CYI input

‘1’ : CCYI cascade input

MUX_Y

9

Y operand MUX

‘0’ : MULT

‘1’ : Concat (B, A)

MUX_CZ

8

Selection for cascaded CZ output

‘0’ : ALU

‘1’ : PR_Y

MUX_X

7:5

X operand MUX

“000” : D[7:0] & C[33:0] (sign extended to 56-bit)

“001” : C (sign extended to 56-bit)

“010” : CZI[39:0] & C[15:0] (concat)

“011” : CZI

“100” : CZI (6-bit right shifted)

“101” : CZI (12-bit right shifted)

“110” : CZI (17-bit right shifted)

“111” : CZI (18-bit right shifted)

MUX_P

4

Pre-adder/ B MUX (to multiplier)

‘0’ : B (sign extended)

‘1’ : Pre-adder

MUX_B

3

B input MUX

‘0’ : Select B input port

‘1’ : Select CBI input

MUX_A

2

A input MUX.

‘0’ : Select A input port

‘1’ : Select CAI input

PRE_ADDER_OP

1

Pre-adder operation

‘0’ : add (B + D)

‘1’ : subtract (B - D)

SIGNED_MODE

0

‘0’ : unsigned, ‘1’: signed

 

raw_config1

type bit_vector(23 downto 0)

default value b“000000000000000000000000”

This generic configures the following fields:

Name

Index

Description

RESERVED

23:20

“0000”

PR_OV_MUX

19

ALU overflow pipe register

‘0’ : no pipeline

‘1’ : pipeline

PR_CO_MUX

18

Carry out pipe depth

‘0’ : no pipeline

‘1’ : pipeline

PR_CCO_MUX

17

Carry cascade out pipe depth

‘0’ : no pipeline

‘1’ : pipeline

PR_Z_MUX

16

Z output pipe depth

‘0’ : no pipeline

‘1’ : pipeline

PR_CZ_MUX

15

Carry z pipe depth

‘0’ : no pipeline

‘1’ : pipeline

PR_Y_MUX

14

Y operand pipe depth

‘0’ : no pipeline

‘1’ : pipeline

PR_X_MUX

13

X operand pipe depth

‘0’ : no pipeline

‘1’ : pipeline

PR_CI_MUX

12

Carry in pipe depth

‘0’ : no pipeline

‘1’ : pipeline

PR_MULT_MUX

11

Multiplier out pipe depth

‘0’ : no pipeline

‘1’ : pipeline

PR_P_MUX

10

Pre-adder pipe depth

‘0’ : no pipeline

‘1’ : pipeline

PR_D_MUX

9

D input pipe depth

‘0’ : no pipeline

‘1’ : pipeline

PR_C_MUX

8

C input pipe depth

‘0’ : no pipeline

‘1’ : pipeline

PR_B_CASCADE_MUX

7:6

Cascaded B input pipe depth

B input pipe depth

Cascaded A input pipe depth

A input pipe depth

“00” : no pipeline

“01” : 1 level pipeline register

“11” : 2 levels pipeline

PR_B_MUX

5:4

PR_A_CASCADE_MUX

3:2

PR_A_MUX

1:0

 

raw_config2

type bit_vector(13 downto 0)

default value b“00000000000000000000”

This generic configures the reset of the pipe registers through the following fields:

Name

Index

Description

ENABLE_PR_OV_RST

13

ALU overflow pipe reset (‘0’ : disable, ‘1’ : enable)

ENABLE_PR_CO_RST

12

Carry out pipe reset (‘0’ : disable, ‘1’ : enable)

ENABLE_PR_CCO_RST

11

Carry Cascade out pipe reset (‘0’ : disable, ‘1’ : enable)

ENABLE_PR_Z_RST

10

Z output pipe reset (‘0’ : disable, ‘1’ : enable)

ENABLE_PR_CZ_RST

9

CZ operand pipe reset (‘0’ : disable, ‘1’ : enable)

ENABLE_PR_MULT_RST

8

Multiplier out pipe reset (‘0’ : disable, ‘1’ : enable)

ENABLE_PR_Y_RST

7

Y operand pipe reset (‘0’ : disable, ‘1’ : enable)

ENABLE_PR_X_RST

6

X operand pipe reset (‘0’ : disable, ‘1’ : enable)

ENABLE_PR_P_RST

5

Pre-adder pipe reset (‘0’ : disable, ‘1’ : enable)

ENABLE_PR_CI_RST

4

Carry in pipe reset (‘0’ : disable, ‘1’ : enable)

ENABLE_PR_D_RST

3

D input pipe reset (‘0’ : disable, ‘1’ : enable)

ENABLE_PR_C_RST

2

C input pipe reset (‘0’ : disable, ‘1’ : enable)

ENABLE_PR_B_RST

1

B input pipe reset (‘0’ : disable, ‘1’ : enable)

ENABLE_PR_A_RST

0

A input pipe reset (‘0’ : disable, ‘1’ : enable)

 

raw_config3

type bit_vector(2 downto 0)

default value b“000”

This generic configures the ALU features through following fields:

Name

Index

Description

ALU_OP

2:0

ALU operation using internal X and Y operands along with internal C carry

"000" : x+y+c

"001" : x-y-c

"010" : x-y+c-1

"011" : x+y-c+1

"100" : -x-y-c-1

"101" : -x+y+c-1

"110" : -x+y-c

"111" : -x-y+c-2

 

The DSP provides the following operations:

DSP modes

Configuration

Equation

Addition operations

ADD42

1 DSP

Z[42:0] = X[41:0] + Y[41:0]

ADD84

2 DSP

Z[84:0] = X[83:0] + Y[83:0]

ADD84

1 DSP 2 cycles

Z[84:0] = X[83:0] + Y[83:0]

Multiplication operations

UMUL24x18

1 DSP

Z[41:0] = X[23:0] * Y[17:0]

SMUL24x18

1 DSP

Z[40:0] = X[23:0] * Y[17:0]

UMUL24x32

2 DSP

Z[55:0] = X[23:0] * Y[31:0]

UMUL24x32

1 DSP 2 cycles

Z[55:0] = X[23:0] * Y[31:0]

SMUL24x32

2 DSP

Z[54:0] = X[23:0] * Y[31:0]

SMUL24x32

1 DSP 2 cycles

Z[54:0] = X[23:0] * Y[31:0]

UMUL24x36

2 DSP

Z[59:0] = X[23:0] * Y[35:0]

UMUL24x36

1 DSP 2 cycles

Z[59:0] = X[23:0] * Y[35:0]

SMUL24x35

2 DSP

Z[57:0] = X[23:0] * Y[34:0]

SMUL24x35

1 DSP 2 cycles

Z[57:0] = X[23:0] * Y[34:0]

UMUL48x36

4 DSP

Z[83:0] = X[47:0] * Y[35:0]

UMUL48x36

1 DSP 4 cycles

Z[83:0] = X[47:0] * Y[35:0]

SMUL47x35

4 DSP

Z[80:0] = X[46:0] * Y[34:0]

SMUL47x35

1 DSP 4 cycles

Z[80:0] = X[46:0] * Y[34:0]

Multiplication and addition operations

UMADD18

1 DSP

Z[42:0] = A[23:0] * B[17:0] + C[41:0]

SMADD18

1 DSP

Z[41:0] = A[23:0] * B[17:0] + C[40:0]

UMADD24

2 DSP

Z[55:0] = A[23:0] * B[31:0] + C[55:0]

UMADD24

1 DSP 2 cycles

Z[55:0] = A[23:0] * B[31:0] + C[55:0]

SMADD24

2 DSP

Z[54:0] = A[23:0] * B[31:0] + C[54:0]

SMADD24

1 DSP 2 cycles

Z[54:0] = A[23:0] * B[31:0] + C[54:0]

Multiplication and accumulation operations

UMACC18

1 DSP

Z[55:0] += X[23:0] * Y[17:0]

SMACC18

1 DSP

Z[55:0] += X[23:0] * Y[17:0]

Multiplication and addition with pre-adder operations

UAMADD18

1 DSP

Z[43:0] = A[23:0] * (B [17:0]+D[17:0]) + C[35:0]

SAMADD18

1 DSP

Z[42:0] = A[23:0] * (B [17:0]+D[17:0]) + C[35:0]

 

Ports

Ports

Direction

Type

Description

A1 to A24

input

std_logic

24-bit A input

B1 to B18

input

std_logic

18-bit B input

C1 to C36

input

std_logic

36-bit C input

CAI1 to CAI24

input

std_logic

24-bit Cascaded A input

CAO1 to CAO24

output

std_logic

24-bit Cascaded A output

CBI1to CBI18

input

std_logic

18-bit Cascaded B input

CBO1 to CBO18

output

std_logic

18-bit Cascaded B output

CCI

input

std_logic

Cascaded Carry input

CCO

output

std_logic

Cascaded Carry output

CI

input

std_logic

Carry input

CK

input

std_logic

Clock (works on rising edges)

CO

output

std_logic

Carry output

CO43

output

std_logic

Carry output bit 43

CO57

output

std_logic

Carry output bit 57

RESERVED

Output

std_logic

 

CZI1 to CZI56

input

std_logic

56-bit Cascaded Z input

CZO1 to CZO56

output

std_logic

56-bit Cascaded Z output

D1 to D18

input

std_logic

18-bit D input

OVF

output

std_logic

Overflow output flag

R

input

std_logic

Reset for all pipeline registers except cascaded output register PR_CZ (active high)

RZ

input

std_logic

Reset for cascaded output register PR_CZ only (active high)

WE

input

std_logic

Write enable for all registers except cascaded output register PR_CZ:

‘0’: all DSP internal registers are frozen, ‘1’: normal operation

WEZ

input

std_logic

Write enable for cascaded output register PR_CZ:

‘0’: DSP cascaded output register PR_CZ is frozen, ‘1’: normal operation

Z1 to Z56

output

std_logic

56-bit Z output

Instantiation Example

This documentation only provides the instantiation of the component.

 

 

Simulation

The NX_DSP_U VHDL simulation model is included in the NxLibrary (NxPackage). It allows to simulate any one of the possible NX_DSP_U configurations.

 

 

 

Use Models

DSPs can be chained to create operations with greater operands.

Addition

Figure 11: DSP 84 bits addition

 

Multiplication

Figure 12: DSP 24x32 bits unsigned multiplication

 

Figure 13: DSP 24x36 bits unsigned multiplication

 

 

 

 

 

 

 

 

 

Figure 14: DSP 48x36 bits unsigned multiplication

 

 

 

 

Figure 15: DSP 47x35 bits signed multiplication



Multiplication and Addition

 

Figure 16: DSP 24x32 bits multiplication then 56 bits addition



NX_DSP_U_SPLIT

The NX_DSP_U_SPLIT is an alternate primitive for using DSP blocks. It can be instantiated as many times as required in your design.

For user’s convenience, the generics are split, and can be modified separately. The input and output busses are grouped.

The following is the declaration of the component NX_DSP_U_SPLIT, included in the nxLibrary-Ultra.vhdp package.

component NX_DSP_U_SPLIT

generic (

-------------------------------------------------------------------------

-- Generic declaration to define the "raw_config0" (cfg_mode). Defines :

-------------------------------------------------------------------------

SIGNED_MODE : bit := '0';

INV_WE : bit := '0';

INV_WEZ : bit := '0';

INV_RST: bit := '0';

INV_RSTZ : bit := '0';

ALU_DYNAMIC_OP : bit_vector(1 downto 0) := B"00"; -- '00' for Static,

-- '-1' for Dynamic control from C

-- '10' for Dynamic control from D

SATURATION_RANK : bit_vector(5 downto 0) := B"000000"; -- Weight of useful MSB on Z and CZO result

-- (to define saturation and overflow)

ENABLE_SATURATION : bit := '0'; -- '0' for Disable, '1' for Enable

MUX_CCO : bit := '0'; -- '0' for CCO = ALU(42), '1' for CCO = ALU(56)

MUX_Z : bit := '0'; -- Select Z output. '0' for Y, '1' Saturation / ALU

MUX_CZ : bit := '0'; -- Select MUX_X input. '0' for CZI, '1' for CZO

MUX_Y : bit := '0'; -- Select ALU's Y input. '0' for MULT output, '1' for (B & A)

MUX_X : bit_vector(2 downto 0) := B"000"; -- Select MUX_X operation

-- "000" for c[33:0]&d[41:34],

-- "001" for C

-- "010" for MUX_X[39:0]&C[15:0]

-- "011" for MUX_X

-- "100" for MUX_X >> 6

-- "101" for MUX_X >> 12

-- "110" for MUX_X >> 17

-- "111" for MUX_X >> 18

MUX_CCI : bit := '0'; -- Select '1' input of CI mux. '0' for CCI, '1' for CO_feddback

MUX_CI : bit := '0'; -- Select input carry of ALU. '0' for CI, '1' for CCI/CO_feedback mux

MUX_P : bit := '0'; -- '0' for PRE_ADDER, '0' for B input

MUX_B : bit := '0'; -- '0' = B input, '1' = CBI input

MUX_A : bit := '0'; -- '0' = A input, '1' = CAI input

PRE_ADDER_OP : bit := '0'; -- '0' = Add, '1' = Sub

-------------------------------------------------------------------------

-- Generic declaration to define the "raw_config1" (cfg_pipe_mux)

-------------------------------------------------------------------------

PR_WE_MUX : bit := '0'; -- '0' for No pipe reg, '1' for 1 pipe reg

PR_WEZ_MUX : bit := '0'; -- '0' for No pipe reg, '1' for 1 pipe reg

PR_RST_MUX : bit := '0'; -- '0' for No pipe reg, '1' for 1 pipe reg

PR_RSTZ_MUX : bit := '0'; -- '0' for No pipe reg, '1' for 1 pipe reg

PR_OV_MUX : bit := '0'; -- '0' for No pipe reg, '1' for 1 pipe reg

PR_CO_MUX : bit := '0'; -- Registered carry out (CO42 & CO56)

PR_CCO_MUX : bit := '0'; -- Registered cascade carry out

PR_Z_MUX : bit := '0'; -- Registered output

PR_CZ_MUX : bit := '0'; -- Registered Cascade output

PR_Y_MUX : bit := '0'; -- '0' for No pipe reg, '1' for 1 pipe reg

PR_X_MUX : bit := '0'; -- '0' for No pipe reg, '1' for 1 pipe reg

PR_CI_MUX : bit := '0'; -- '0' for No pipe reg, '1' for 1 pipe reg

PR_MULT_MUX : bit := '0'; -- No pipe reg -- Register inside MULT

PR_P_MUX : bit := '0'; -- '0' for No pipe reg, '1' for 1 pipe reg (Pre-adder)

PR_D_MUX : bit := '0'; -- '0' for No pipe reg, '1' for 1 pipe reg

PR_C_MUX : bit := '0'; -- '0' for No pipe reg, '1' for 1 pipe reg

PR_B_CASCADE_MUX : bit_vector(1 downto 0) := "00"; -- Number of pipe reg levels for CAO output. "-0" for 0 level, "01" for 1 level, "11" for 2 levels

PR_B_MUX : bit_vector(1 downto 0) := "00"; -- Number of pipe reg levels on B input. "-0" for 0 level, "01" for 1 level, "11" for 2 levels

PR_A_CASCADE_MUX : bit_vector(1 downto 0) := "00"; -- Number of pipe reg levels for CAO output. "-0" for 0 level, "01" for 1 level, "11" for 2 levels

PR_A_MUX : bit_vector(1 downto 0) := "00"; -- Number of pipe reg levels on A input. "-0" for 0 level, "01" for 1 level, "11" for 2 levels

-------------------------------------------------------------------------

-- Generic declaration to define the "raw_config2" (cfg_pipe_rst)

-------------------------------------------------------------------------

ENABLE_PR_OV_RST : bit := '1'; -- '0' for Disable, '1' for Enable

ENABLE_PR_CO_RST : bit := '1'; -- '0' for Disable, '1' for Enable

ENABLE_PR_CCO_RST : bit := '1'; -- '0' for Disable, '1' for Enable

ENABLE_PR_Z_RST : bit := '1'; -- '0' for Disable, '1' for Enable

ENABLE_PR_CZ_RST : bit := '1'; -- '0' for Disable, '1' for Enable

ENABLE_PR_Y_RST : bit := '1'; -- '0' for Disable, '1' for Enable

ENABLE_PR_X_RST : bit := '1'; -- '0' for Disable, '1' for Enable

ENABLE_PR_CI_RST : bit := '1'; -- '0' for Disable, '1' for Enable

ENABLE_PR_MULT_RST : bit := '1'; -- '0' for Disable, '1' for Enable

ENABLE_PR_P_RST : bit := '1'; -- '0' for Disable, '1' for Enable

ENABLE_PR_D_RST : bit := '1'; -- '0' for Disable, '1' for Enable

ENABLE_PR_C_RST : bit := '1'; -- '0' for Disable, '1' for Enable

ENABLE_PR_B_RST : bit := '1'; -- '0' for Disable, '1' for Enable

ENABLE_PR_A_RST : bit := '1'; -- '0' for Disable, '1' for Enable

-- PR_CZ_INIT : bit_vector(5 downto 0) := B"000000"; -- Value of CZ's pipe register on reset

 

 

-------------------------------------------------------------------------

-- Constants declaration to define the "cfg_pipe_rst" -- raw_config3(6 downto 0)

-------------------------------------------------------------------------

ALU_OP : bit_vector(2 downto 0) := B"000"; -- ALU operation

-- x+y+c = "000"

-- x-y-c = "001"

-- x-y+c-1 = "010"

-- x+y-c+1 = "011"

-- -x-y-c-1 = "100"

-- -x+y+c-1 = "101"

-- -x+y-c = "110"

-- -x-y+c-2 = "111"

);

port(

CK : IN std_logic;

R : IN std_logic;

RZ : IN std_logic;

WE : IN std_logic;

WEZ : IN std_logic;

CI : IN std_logic;

A : IN std_logic_vector(23 downto 0);

B : IN std_logic_vector(17 downto 0);

C : IN std_logic_vector(35 downto 0);

D : IN std_logic_vector(17 downto 0);

CAI : IN std_logic_vector(23 downto 0);

CBI : IN std_logic_vector(17 downto 0);

CZI : IN std_logic_vector(55 downto 0);

CCI : IN std_logic;

 

Z : out std_logic_vector(55 downto 0);

CO42 : OUT std_logic;

CO56 : OUT std_logic;

OVF : OUT std_logic;

CAO : OUT std_logic_vector(23 downto 0);

CBO : OUT std_logic_vector(17 downto 0);

CZO : OUT std_logic_vector(55 downto 0);

CCO : OUT std_logic

);

end component

 

 

NX_DSP_U_WRAP

Description

The NX_DSP_U_WRAP component provides a wrapper around NX_DSPU IP for user convenience, concatening bits into vector interfaces. The generics are the same as NX_DSP_U, check the associated section for detail explanations.

 

Ports

Ports

Direction

Type

Description

A

input

std_logic_vector (23 downto 0)

24-bit A input

B

input

std_logic_vector (17 downto 0)

18-bit B input

C

input

std_logic_vector (35 downto 0)

36-bit C input

CAI

input

std_logic_vector (23 downto 0)

24-bit Cascaded A input

CAO

output

std_logic_vector (23 downto 0)

24-bit Cascaded A output

CBI

input

std_logic_vector (17 downto 0)

18-bit Cascaded B input

CBO

output

std_logic_vector (17 downto 0)

18-bit Cascaded B output

CCI

input

std_logic

Cascaded Carry input

CCO

output

std_logic

Cascaded Carry output

CI

input

std_logic

Carry input

CK

input

std_logic

Clock (works on rising edges)

CO43

output

std_logic

Carry output bit 43

CO57

output

std_logic

Carry output bit 57

CZI

input

std_logic_vector (55 downto 0)

56-bit Cascaded Z input

CZO

output

std_logic_vector (55 downto 0)

56-bit Cascaded Z output

D

input

std_logic_vector (17 downto 0)

18-bit D input

OVF

output

std_logic

Overflow output flag

R

input

std_logic

Reset for pipeline registers except Z output register (active high)

RZ

input

std_logic

Reset for Z output register only(active high)

WE

input

std_logic

Write enable for internal registers:

‘0’: all DSP internal registers are frozen, ‘1’: normal operation

WEZ

input

std_logic

Write enable for output registers:

‘0’: all DSP output registers are frozen, ‘1’: normal operation

Z

output

std_logic_vector (55 downto 0)

56-bit Z output

 

ADD84_2DSP

Description

The ADD84_2DSP component provides a wrapper around NX_DSP_U_WRAP IP fully configured to offer an addition between two 84-bit operands using two DSP.

 

Generics

piped

type boolean

default value “true”

This generic enables by default the use of pipeline registers inside all DSP.

 

Ports

Ports

Direction

Type

Description

X

input

std_logic_vector (83 downto 0)

84-bit X first operand

Y

input

std_logic_vector (83 downto 0)

84-bit Y second operand

Z

output

std_logic_vector (84 downto 0)

85-bit Z result

clk

input

std_logic

Clock (works on rising edges)

rst

input

std_logic

 

 

 

 

 

 

Reset for pipeline registers & Z output registers for both DSP (active high)

 

SMUL47x35_4DSP

Description

The SMUL47x35_4DSP component provides a wrapper around NX_DSP_U_WRAP IP fully configured to offer a signed multiplication between two operands of 47 and 35-bit using four DSP.

 

Generics

piped

type boolean

default value “true”

This generic enables by default the use of pipeline registers inside the four DSP.

 

Ports

Ports

Direction

Type

Description

A

input

std_logic_vector (46 downto 0)

47-bit A first operand

B

input

std_logic_vector (34 downto 0)

35-bit B second operand

Z

output

std_logic_vector (80 downto 0)

81-bit Z result

clk

input

std_logic

Clock (works on rising edges)

rst

input

std_logic

 

 

 

 

 

 

Reset for pipeline registers & Z output registers for both DSP (active high)

 

UMADD24_2DSP

Description

The UMADD_2DSP component provides a wrapper around NX_DSP_U_WRAP IP fully configured to offer an unsigned multiplication with addition based on a 24-bit operand and using two DSP.

 

Generics

piped

type boolean

default value “true”

This generic enables by default the use of pipeline registers inside all DSP.

 

Ports

Ports

Direction

Type

Description

A

input

std_logic_vector (23 downto 0)

24-bit A first operand

B

input

std_logic_vector (31 downto 0)

32-bit B second operand

C

input

std_logic_vector (55 downto 0)

56-bit C second operand

Z

output

std_logic_vector (55 downto 0)

56-bit Z result

clk

input

std_logic

Clock (works on rising edges)

rst

input

std_logic

 

 

 

 

 

 

Reset for pipeline registers & Z output registers for both DSP (active high)

UMUL24x32_1DSP_2CYCLES

Description

The UMUL24x32_1DSP_2CYCLES component provides a wrapper around NX_DSP_U_WRAP IP fully configured to offer an unsigned 24x32 multiplication using one DSP with cascade interface during 2 cycles.

 

Generics

piped

type boolean

default value “true”

This generic enables by default the use of pipeline registers inside all DSP.

 

Ports

Ports

Direction

Type

Description

A

input

std_logic_vector (23 downto 0)

24-bit A first operand

B

input

std_logic_vector (15 downto 0)

16-bit B second operand

Z

output

std_logic_vector (55 downto 0)

56-bit Z result

clk

input

std_logic

Clock (works on rising edges)

rst

input

std_logic

 

 

 

 

 

 

Reset for pipeline registers & Z output registers for both DSP (active high)

 

UMUL24x32_2DSP

Description

The UMUL24x32_2DSP component provides a wrapper around NX_DSP_U_WRAP IP fully configured to offer an unsigned 24x32 multiplication using two DSP.

 

Generics

piped

type boolean

default value “true”

This generic enables by default the use of pipeline registers inside all DSP.

 

Ports

Ports

Direction

Type

Description

A

input

std_logic_vector (23 downto 0)

24-bit A first operand

B

input

std_logic_vector (31 downto 0)

32-bit B second operand

Z

output

std_logic_vector (55 downto 0)

56-bit Z result

clk

input

std_logic

Clock (works on rising edges)

rst

input

std_logic

 

 

 

 

 

 

Reset for pipeline registers & Z output registers for both DSP (active high)

UMUL24x36_1DSP_2CYCLES

Description

The UMUL24x36_1DSP_2CYCLES component provides a wrapper around NX_DSP_U_WRAP IP fully configured to offer an unsigned 24x36 multiplication using one DSP with cascade interface during 2 cycles.

 

Generics

piped

type boolean

default value “true”

This generic enables by default the use of pipeline registers inside all DSP.

 

Ports

Ports

Direction

Type

Description

A

input

std_logic_vector (23 downto 0)

24-bit A first operand

B

input

std_logic_vector (17 downto 0)

18-bit B second operand

Z

output

std_logic_vector (59 downto 0)

60-bit Z result

clk

input

std_logic

Clock (works on rising edges)

rst

input

std_logic

 

 

 

 

 

 

Reset for pipeline registers & Z output registers for both DSP (active high)

 

UMUL24x36_2DSP

Description

The UMUL24x36_2DSP component provides a wrapper around NX_DSP_U_WRAP IP fully configured to offer an unsigned 24x36 multiplication using two DSP.

 

Generics

piped

type boolean

default value “true”

This generic enables by default the use of pipeline registers inside all DSP.

 

Ports

Ports

Direction

Type

Description

A

input

std_logic_vector (23 downto 0)

24-bit A first operand

B

input

std_logic_vector (35 downto 0)

36-bit B second operand

Z

output

std_logic_vector (59 downto 0)

60-bit Z result

clk

input

std_logic

Clock (works on rising edges)

rst

input

std_logic

 

 

 

 

 

 

Reset for pipeline registers & Z output registers for both DSP (active high)

UMUL48x36_1DSP_4CYCLES

Description

The UMUL48x36_1DSP_4CYCLES component provides a wrapper around NX_DSP_U_WRAP IP fully configured to offer an unsigned 48x36 multiplication using one DSP with cascade interface during 4 cycles.

 

Generics

piped

type boolean

default value “true”

This generic enables by default the use of pipeline registers inside all DSP.

 

Ports

Ports

Direction

Type

Description

A

input

std_logic_vector (23 downto 0)

24-bit A first operand

B

input

std_logic_vector (17 downto 0)

18-bit B second operand

Z

output

std_logic_vector (83 downto 0)

84-bit Z result

clk

input

std_logic

Clock (works on rising edges)

rst

input

std_logic

 

 

 

 

 

 

Reset for pipeline registers & Z output registers for both DSP (active high)

 

UMUL48x36_4DSP

Description

The UMUL48x36_2DSP component provides a wrapper around NX_DSP_U_WRAP IP fully configured to offer an unsigned 48x36 multiplication using four DSP.

 

Generics

piped

type boolean

default value “true”

This generic enables by default the use of pipeline registers inside all DSP.

 

Ports

Ports

Direction

Type

Description

A

input

std_logic_vector (47 downto 0)

48-bit A first operand

B

input

std_logic_vector (35 downto 0)

36-bit B second operand

Z

output

std_logic_vector (83 downto 0)

84-bit Z result

clk

input

std_logic

Clock (works on rising edges)

rst

input

std_logic

 

 

 

 

 

 

Reset for pipeline registers & Z output registers for both DSP (active high)



NX_RAM

Description

The NX_RAM component describes a synchronous True Dual Port Random Access Memory circuit of 48 Kbits available in NG-MEDIUM. The circuit supports Error Code Correction (ECC, also called EDAC – Error Detection and Correction).

The 48K-bit memory array can be simultaneously read or written by two access ports (A and B).

 

When used without EDAC, the external RAM block configuration can be set independently for the two access ports. As an example, the port A can be configured for 48Kx1, while the port B can be organized as 4Kx12.

Data inputs, addresses, control signals, clock inputs and data outputs are independent for each ports. The clocks can be synchronous or asynchronous.

 

However, simultaneous write access on both ports at the same physical address, or write access simultaneous with a read access at the same physical address are not allowed.

 

 

Figure 17: RAM diagram



Memory ports configurations

Optional input and output behavior and pipeline registers:

By default, the RAM block do not use pipeline registers. The output delivers a valid data Taccess_time after the clock edge that samples the read address (ACS = ‘1’ and AWE = ‘0’) or BCS = ‘1’ and BWE = ‘0’).

NX_RAM outputs behavior during write :

During write cycles (ACS = ‘1’ and AWE = ‘1’) or (BCS = ‘1’ and BWE = ‘1’), the RAM block output remains with the anterior value (NO_CHANGE mode)

In addition, reading from one port while simultaneously writing to the other port at the same memory location is not allowed.

During write cycles (ACS = ‘1’ and AWE = ‘1’) or (BCS = ‘1’ and BWE = ‘1’), the RAM block output remains with the anterior value.

However, to improve the design performance (in terms of clock frequency), the user can optionally insert two levels of pipeline registers.

  • The output pipeline allows to support higher frequencies, and reduces the apparent memory access time, at the cost of one clock cycle delay.

  • The input pipeline register level also improves the supported frequency, and reduces the apparent memory setup delay, at the cost of one additional clock cycle delay.

  • The optional input and output registers can be synchronously reset by activating the AR (A port) and/or BR (B port) inputs (active high).

In addition, the polarity of the block RAM clock as well as the one of the register clocks can be modified by the user (see NX_RAM raw_config0).

 

No ECC modes

The NO_ECC configuration mode is set by generics (raw_config1(15:12) = “0000”.

The memory is internally organized as a 2K x 24-bit array. The memory is True Dual Port. It can be simultaneously access by 2 ports (respectively called port A and port B).

Each port can access the array in several formats. Each port can have an independent configuration (address and data width), with independent data input, addresses, control signals, data output and clock. The two clocks can be synchronous or asynchronous.

The possible configuration ratios on each port can be defined either with the “std_mode” or the “raw_config1 generic. Among the available NX_RAM configurations :

 

“std_mode” values

NG-ULTRA

“raw_config1” equivalent

 

 

 

NO ECC

Ports width

 

 

"NOECC_48kx1"

0000 000 000 000 000

"NOECC_24kx2"

0000 001 001 001 001

"NOECC_16kx3"

0000 110 110 110 110

"NOECC_12kx4"

0000 010 010 010 010

"NOECC_8kx6"

0000 111 111 111 111

"NOECC_6kx8"

0000 011 011 011 011

"NOECC_4kx12"

0000 100 100 100 100

"NOECC_2kx24"

0000 101 101 101 101

"FAST_2kx18"

0011 100 100 100 100

"SLOW_2kx18"

1101 100 100 100 100

 

 

In addition, the user can define several different NX_RAM configurations by directly assigning the “raw_config1” generic value, and assign the optional input and output pipeline registers with “raw_config0” generic.

However, it’s strongly recommended to select the same width for input and output data width on a same port. As an example, port A could be configured as NO ECC 2kx24, while port B could be configured as NO ECC 4kx12, with the following “raw_config1” setting :

raw_config1 => “0000” & “100” & “101” & “100” & “101”;

More on input and output data width

The input data width and output data width for both ports A and B can be set by setting generic values if the RAM block is instantiated (raw_config1(11:0)).

The figure 8 shows the physical memory organization and the dada/address lines to be used to access the array contents (output data is shown for port A only).

 

Figure 18: NX_RAM organization (No ECC)

2K x 24 :

Internally, the RAM blocks are physically organized as 2K x 24-bit array. The addresses AA11 .. AA1 (or BA11 .. BA1) are used to access the 24-bit data. AI24 .. AI1 (or BI24 .. BI1) data input lines are used for write operations. A024 .. AO1 (or BO24 .. BO1) are used or data read.

4K x 12 and other organizations : 6K x 8, 12K x4, 24K x 2 and 48K x 1 (16K x 3 and 8K x 6 also supported on NG-LARGE) :

When organized as 4K x 12, the addresses AA11 .. AA1 (or BA11 .. BA1) are used to access the 24-bit data word, an additional address bit (AA12 or BA12) is used to index the lower or higher 12-bit sub words. In addition, during write, the data inputs AI12 .. AI1 (or BI12 .. BI1) are used to write the lower 12 bits, and AI24 .. AI13 (or BI24 .. BI13) are used to write the higher 12 bits. For reading, AO12 .. AO1 (or BO12 .. BO1) are used to read both lower and higher 12 bits.

As a consequence, for data write, the data input bus must be replicated one or more times on the RAM block input data pins. The following figure shows a summary for the 6 possible configurations. Only port A is shown. The rules are obviously the same for port B.

Figure 19: Address and data connections (No ECC)

 

Note that a similar scheme can be applied to the configurations 16K x 3 and 8K x 6.

  • In 16K x 3 configuration, the 3-bit data input must be replicated 8 times

  • In 8K x 6 configuration, the 3-bit data input must be replicated 4 times

 

 

ECC modes

When used with ECC, the user array size is restricted to 2K x 18. The 6 remaining bits of each internal address of 24-bit words are used to store the ECC signature of each 18-bit data.

 

During the write cycles, the ECC encoder generates a 6-bit signature for each 18-bit data to be written. The resulting 24-bit words is then stored into the specified address.

 

During read cycles, the ECC decoder can detect and correct any single bit error, or detect any double bit error.

Figure 20: RAM organization (ECC FAST or SLOW)

 

The physical connections of address and input/output data lines is shown in the next figure.

Figure 21: Address and data connections (ECC FAST or SLOW)

 

ECC data correction in FAST mode

  • If a single bit error is found, it will be automatically detected and corrected at the RAM output port. The flags ACOR or BCOR are set during the read cycle to signal the error detection and correction. However, the internal memory array remains corrupt.

  • If a double bit error is detected, it can’t be corrected, and the flags AERR or BERR are asserted.

ECC data correction in SLOW mode

  • This mode is also called Read Repair Mode (RRM).

  • If a single bit error is found, it will be automatically detected and corrected at the RAM output port, and the memory content is automatically updated with the corrected value. The flags ACOR or BCOR are set during the user’s read cycle to signal the error detection and correction.

  • If a double bit error is detected, it can’t be corrected, but the flags AERR or BERR are asserted.

  • In order to correct a possible error during a read access, the read cycle becomes a read modify write, where the write half cycle is transparent to the user. For this, the NG-MEDIUM RAM blocks use a doubled internal frequency. This internal clock is generated by using an exclusive OR, between the main clock (CKA or CKB) and the 90° shifted clock (ACKD or BCKD) required to support the ECC SLOW mode.

  • Using ACKD and/or BCKD in ECC SLOW mode is mandatory. It must be a 90° phase shifted version of the main clock input (ACK and/or BCK). ACKD and BCKD can each be generated with ACK and BCK by using PLL and WFGs.

  • In this mode, the internal RAM block works a frequency that is double of the user’s clock. The maximum user’s clock frequency is then reduced by a factor of 2, approximately.

 

Generics

mcka_edge

type bit

default value ‘0’

This generic represents the front polarity of the clock associated to the first port of the memory. ‘0’ is for rising edge and ‘1’ for falling edge.

 

mckb_edge

type bit

default value ‘0’

This generic represents the front polarity of the clock associated to the second port of the memory. ‘0’ is for rising edge and ‘1’ for falling edge.

 

pcka_edge

type bit

default value ‘0’

This generic represents the front polarity of the clock associated to the pipeline registers of the first port. ‘0’ is for rising edge and ‘1’ for falling edge.

 

pckb_edge

type bit

default value ‘0’

This generic represents the front polarity of the clock associated to the pipeline registers of the second port. ‘0’ is for rising edge and ‘1’ for falling edge.

pipe_ia

type bit

default value ‘0’

When set to ‘1’, this generic allows to insert a pipeline register at the inputs of the A port (addresses, data inputs, ACS and AWE), when the “std_mode” generic is used. If “std_mode” is not used, the user must use the “raw_config0(3:0)” generic.

 

pipe_ib

type bit

default value ‘0’

When set to ‘1’, this generic allows to insert a pipeline register at the inputs of the B port (addresses, data inputs, BCS and BWE), when the “std_mode” generic is used. If “std_mode” is not used, the user must use the “raw_config0(3:0)” generic.

 

pipe_oa

type bit

default value ‘0’

When set to ‘1’, this generic allows to insert a pipeline register at the outputs of the A port (data outputs), when the “std_mode” generic is used. If “std_mode” is not used, the user must use the “raw_config0(3:0)” generic.

 

pipe_ob

type bit

default value ‘0’

When set to ‘1’, this generic allows to insert a pipeline register at the outputs of the B port (data outputs), when the “std_mode” generic is used. If “std_mode” is not used, the user must use the “raw_config0(3:0)” generic.

 

mem_ctxt

type string

default value “”

This generic represents the initial value of the RAM. The initial value can be optionally set by bitstream. The string contains a list of all complete bit words separated by coma.

When a word size is less than the RAM data size or when number of words is less than RAM word count, an error occurs.

When a word size exceeds RAM data size or when the number of words exceeds the RAM word count, an error occurs.

 

constant MEM_INIT_0 : string := (

"001100001110010000001111,000000000000000000001110,000001001110000000001101,000000001100000000001100," &

"000000000000000000001011,000000000000000000001010,000000000000000000001001,000000000000000000001000," &

" 512 lines of 4 x 24-bit values “ &

"000000000000000000000000,000000000000000000000000,000000000000000000000000,000000000000000000000000," &

"000000000000000000000000,000000000000000000000000,000000000000000000000000,000000000000000000000000," &

"000000111000000110000110,000111100110001110000011,010011011100001010001110,110001110010010001111000,"

);

The “MEM_INIT_0” constant has been declared in a user’s package can be assigned to the “mem_ctxt” NX_RAM generic.

 

std_mode

type string

default value “”

This generic represents the predefined operating mode of the RAM. When “std_mode” is assigned, the “raw_config0” and raw_config1” generics are ignored. When empty the operating mode is defined by the 2 raw_config generics.

 

When using one of these predefined modes, the 3 raw_config generics are defined as follow:

  • raw_config0(3 downto 0) → pipe_ia & pipe_ib, pipe_oa, pipe_ob

  • raw_config1

    • FAST_2kx18 ”0011100100100100”

    • SLOW_2kx18 ”1101100100100100”

 

  • NOECC_8kx6 ”0000110110110110”

  • NOECC_16kx3 ”0000111111111111”

  • NOECC_2kx24 ”0000101101101101”

  • NOECC_4kx12 ”0000100100100100”

  • NOECC_6kx8 ”0000011011011011”

  • NOECC_12kx4 ”0000010010010010”

  • NOECC_24kx2 ”0000001001001001”

  • NOECC_48kx1 ”0000000000000000”

 

 

raw_config0

type bit_vector(3 downto 0)

default value b“0000”

This generic configures the optional pipeline registers on input and outputs of A and B ports:

Name

Index

Description

PB_OUT_PR_MUX

3

Port B output optional pipeline register.

‘0’: no register

‘1’: Pipe register is used

 

PA_OUT_PR_MUX

2

Port A output optional pipeline register.

‘0’: no register

‘1’: Pipe register is used

PB_IN_PR_MUX

1

Port B input optional pipeline register.

‘0’: no register

‘1’: Pipe register is used

PA_IN_PR_MUX

0

Port A input optional pipeline register.

‘0’: no register

‘1’: Pipe register is used

 

raw_config1

type bit_vector(15 downto 0)

default value b“0000000000000000”

This generic configures the following fields:

Name

Index

Description

PB_ECC_RRM

15

ECC Read Repair Mode on port B

PA_ECC_RRM

14

ECC Read Repair Mode on port A

PX_ECC_FAST

13

Fast mode ECC. Must be low if PB_ECC_RRM and PA_ECC_RRM are set to ‘1’

PX_ECC

12

Enable ECC

PB_OUT_WIDTH

11:9

B port output width

PA_OUT_WIDTH

8:6

A port output width

PB_IN_WIDTH

5:3

B port input width

PA_IN_WIDTH

2:0

A port input width

Input / output widths values depend on PX_ECC:

  • PX_ECC = 0 (ECC desactivated)

    • 000: 1-bit width

    • 001: 2-bit width

    • 010: 4-bit width

    • 011: 8-bit width

    • 100: 12-bit width

    • 101: 24-bit width

    • 110: 3-bit width

    • 111: 6-bit width

 

  • Px_ECC = 1 (all ECC modes)

    • 100: width is 18 bits

    • other values are reserved

 

The bits raw_config1(15 downto 12) are used to define the NO_ECC, ECC_FAST or ECC_SLOW modes. The following table shows the possible configuration values.

 

15

14

13

12

Comment

0

0

0

0

Normal mode (NO ECC)

0

0

0

1

Invalid configuration

0

0

1

0

Invalid configuration

0

0

1

1

ECC FAST mode (no read repair)

0

1

0

0

Invalid configuration

0

1

0

1

ECC SLOW (read repair enabled on port A)

0

1

1

0

Invalid configuration

0

1

1

1

Invalid configuration

1

0

0

0

Invalid configuration

1

0

0

1

ECC SLOW (read repair enabled on port B)

1

0

1

0

Invalid configuration

1

0

1

1

Invalid configuration

1

1

0

0

Invalid configuration

1

1

0

1

ECC SLOW (read repair enabled on both ports)

1

1

1

0

Invalid configuration

1

1

1

1

Invalid configuration

 

raw_l_enable

type bit

default value b’0’

This generic defines the FPGA family currently targeted. ‘0’ for NG-MEDIUM, ‘1’ for NG-LARGE (additional configuration modes)

 

raw_l_extend

type bit_vector(3 downto 0)

default value b“0000”

Extended modes for NG-LARGE (scrubbing, test, …).

 

raw_u_enable

type bit

default value b’0’

This generic defines the FPGA family currently targeted. ‘0’ for NG-MEDIUM, ‘1’ for NG-ULTRA (additional configuration modes)

 

raw_u_extend

type bit_vector(7 downto 0)

default value b“0000000”

Extended modes for NG-ULTRA (scrubbing, test, …).

 

 

Ports

Ports

Direction

Type

Description

ACK

input

std_logic

A port memory main clock

ACKC

input

std_logic

A port memory clock clone. Must be connected to the same clock source as ACK

ACKD

input

std_logic

A port memory 90° shifted clock. ACKD must be used when Read Repair Mode is selected on this port. It allows to internally generate a double frequency for the memory matrix, to allow read modify write during a single user’s clock cycle.

ACKR

input

std_logic

A port register clock. ACKR must be fed by a valid clock (typically ACK), if the optional input or output pipeline registers are used.

BCK

input

std_logic

B port memory main clock.

BCKC

input

std_logic

B port memory clock clone. Same comments as for ACKC

BCKD

input

std_logic

B port memory 90° shifted clock. Just as ACKD, BCKD is used when Read Repair Mode is selected on B port.

BCKR

input

std_logic

B port register clock. BCKR must be fed by a valid clock (typically BCK), if the optional input or output pipeline registers are used.

AI1 to AI24

input

std_logic

A port input data. See notes on data input width for proper operation.

BI1 to BI24

input

std_logic

B port input data. See notes on data input width for proper operation.

ACOR

output

std_logic

Goes high for one clock cycle when an error has been detected and corrected on port A

AERR

output

std_logic

Goes high for one clock cycle when an uncorrectable error has been found on port A

BCOR

output

std_logic

Goes high for one clock cycle when an error has been detected and corrected on port A

BERR

output

std_logic

Goes high for one clock cycle when an uncorrectable error has been found on port A

AO1 to AO24

output

std_logic

A port output data. See notes on data output width for proper operation

BO1 to BO24

output

std_logic

B port output data. See notes on data output width for proper operation

AA1 to AA16

input

std_logic

A port address. See notes on physical and logical addresses for proper operation

ACS

input

std_logic

A port chip select (active high)

AWE

input

std_logic

A port write enable (active high)

AR

input

std_logic

A port registers reset (active high)

BA1 to BA16

input

std_logic

B port address. See notes on physical and logical addresses for proper operation

BCS

input

std_logic

B port chip select (active high)

BWE

input

std_logic

B port write enable (active high)

BR

input

std_logic

B port registers reset (active high)

 

The ACKC port must be connected and is a clone of the memory clock (ACK).

When using one of the SLOW modes, ACKD port must be connected to a clock which is a 90° shifted version of ACK. ACKD can be generated with ACK by using 2 WFGs in the same CKG block.

The ACKR input clock is used only for the optional input and output pipeline registers. AR is the input for synchronous reset of those registers.

The BCKC and BCKD ports must be connected as described for ACKC and ACKD. BR is the synchronous reset of the optional input and output registers on port B.

 

Instantiation Example

 

Simulation

The NX_RAM VHDL simulation model is included in the NxLibrary (NxPackage.vhd). It allows to simulate any one of the possible configurations, including with ECC in FAST or SLOW modes.

NX_RAM_WRAP

Description

The NX_RAM_WRAP provides an alternate way to instantiate NX_RAM. It uses the same generics as NX_RAM, and the ports are grouped as busses whenever possible.

 

Generics

std_mode : string := "";

mcka_edge : bit := '0';

mckb_edge : bit := '0';

pcka_edge : bit := '0';

pckb_edge : bit := '0';

pipe_ia : bit := '0';

pipe_ib : bit := '0';

pipe_oa : bit := '0';

pipe_ob : bit := '0';

mem_ctxt : string := "";

raw_config0 : bit_vector( 3 downto 0) := B"0000";

raw_config1 : bit_vector(15 downto 0) := B"0000000000000000"

raw_l_enable : bit := ‘0’;

raw_l_extend : bit_vector(3 downto 0) := B"0000"

raw_u_enable : bit := ‘0’;

raw_u_extend : bit_vector(7 downto 0) := B"00000000"

 

Please, refer to the NX_RAM chapter for more detailed information.

 

Ports

 

Ports

Direction

Type

Description

ACK

input

std_logic

A port memory main clock

ACKD

input

std_logic

A port memory 90° shifted clock. ACKD must be used when Read Repair Mode is selected on this port. It allows to internally generate a double frequency for the memory matrix, to allow read modify write during a single user’s clock cycle.

ACKR

input

std_logic

A port register clock. ACKR must be fed by a valid clock (typically ACK), if the optional input or output pipeline registers are used.

BCK

input

std_logic

B port memory main clock.

BCKD

input

std_logic

B port memory 90° shifted clock. Just as ACKD, BCKD is used when Read Repair Mode is selected on B port.

BCKR

input

std_logic

B port register clock. BCKR must be fed by a valid clock (typically BCK), if the optional input or output pipeline registers are used.

AI(23:0)

input

std_logic_vector

A port input data. See notes on data input width for proper operation.

BI(23:0)

input

std_logic_vector

B port input data. See notes on data input width for proper operation.

ACOR

output

std_logic

Goes high for one clock cycle when an error has been detected and corrected on port A

AERR

output

std_logic

Goes high for one clock cycle when an uncorrectable error has been found on port A

BCOR

output

std_logic

Goes high for one clock cycle when an error has been detected and corrected on port A

BERR

output

std_logic

Goes high for one clock cycle when an uncorrectable error has been found on port A

AO(23:0)

output

std_logic_vector

A port output data. See notes on data output width for proper operation

BO(23:0)

output

std_logic_vector

B port output data. See notes on data output width for proper operation

AA(15:0)

input

std_logic_vector

A port address. See notes on physical and logical addresses for proper operation

ACS

input

std_logic

A port chip select (active high)

AWE

input

std_logic

A port write enable (active high)

AR

input

std_logic

A port registers reset (active high)

BA(15:0)

input

std_logic_vector

B port address. See notes on physical and logical addresses for proper operation

BCS

input

std_logic

B port chip select (active high)

BWE

input

std_logic

B port write enable (active high)

BR

input

std_logic

B port registers reset (active high)

 

 

 

Instantiation Example

 

Simulation

The NX_RAM VHDL simulation model is included in the NxLibrary (NxPackage.vhd). It allows to simulate any one of the possible configurations, including with ECC in FAST or SLOW modes.

 

SOC

NX_SOC_INTERFACE_WRAP

Description

The NX_SOC_INTERFACE_WRAP component describes the complete set of signals transiting between the System-On-Chip (SOC) and the fabric of NG-Ultra. Through this hard IP, the fabric is connected to the network interconnect of the SoC and can receive/send data requests from/to various functions of the SoC.

 

 

Generics

 

bsm_config

type bit_vector(31 downto 0)

default value B"00000000000000000000000000000000"

This generic specifies the configuration for the bitstream functionalities.

 

ahb_config

type bit_vector(31 downto 0)

default value B"00000000000000000000000000000000"

This generic specifies the configuration for the ahb interface.

 

Ports

Clock, reset and config signals

The following array list the clock, reset and config (interruptions, trigger, hold) signals exchanged between the fabric and the SOC.

 

Ports

Direction

Type

Description

fabric_lowskew_o

Output

std_logic_vector (1 downto 0)

dahlia_rstn_fpga_out_i / dahlia_clk_fpga_i going to fabric

fabric_lowskew_i

Input

std_logic_vector (18 downto 2)

10 FPGA clocks (dahlia_clk_fpga_nic_o) send by fabric

18 => fpga_ddr0

17 => llpp3_s

16 => llpp2_s

15 => llpp1_s

14 => llpp0_s

13 => fpga_apb

12 => axi_s2

11 => axi_s1

10 => axi_m2

9 => axi_m1

8 => dma_hs_5

7 => dma_hs_4

6 => dma_hs_3

5 => dma_hs_2

4 => dma_hs_1

3 => dma_hs_0

2 => qos_pclk

fabric_enable_TMR_i

Input

std_logic_vector(3 downto 0)

Control bits to enable signals going from SoC to Fabric. Default value set to 1 for each bit

fabric_fpga_nic_rstn_i

Input

std_logic_vector (9 downto 0)

10 FPGA resets (dahlia_fpga_pmrstn_o) send by fabric

Same mapping than fabric_lowskew_i

fabric_fpga_pmrstn_i

Input

std_logic

Power monitoring reset. Active low

fabric_fpga_sysrstn_i

Input

std_logic

System reset. Active low

fabric_fpga_trigger_in_o

Output

std_logic_vector (7 downto 0)

Trigger in bus

fabric_fpga_trigger_out_i

Input

std_logic_vector (7 downto 0)

Trigger out bus

fabric_fpga_interrupt_in_i

Input

std_logic_vector (119 downto 0)

Interrupt bus

fabric_sysc_hold_on_debug_i

Input

std_logic

Hold

fabric_fpga_events60_i

Input

std_logic_vector (59 downto 0)

Fpga event bus

fabric_spw_interrupts_toggle_o

Output

std_logic_vector(2 downto 0)

Spacewire interruption toggle

fabric_spw_interrupts_o

Output

std_logic_vector(2 downto 0)

Spacewire interruption

fabric_flash_irq_toggle_o

Output

std_logic

Flash interruption toggle

fabric_flash_irq_o

Output

std_logic

Flash interruption

 

 

AXI Master requests

The Network interconnect of the SoC (NIC) handles different protocols for different interfaces, including two set of AXI master interfaces connected to the fabric.

 

Ports

Direction

Type

fabric_fpga_dma_hs_rstn_i

Input

std_logic_vector (5 downto 0)

fabric_fpga_arready_axi_m*_o

Output

std_logic

fabric_fpga_awready_axi_m*_o

Output

std_logic

fabric_fpga_bid_axi_m*_o

Output

std_logic_vector (4 downto 0)

fabric_fpga_bresp_axi_m*_o

Output

std_logic_vector (1 downto 0)

fabric_fpga_bvalid_axi_m*_o

Output

std_logic

fabric_fpga_dma_ack_m*_o

Output

std_logic_vector (5 downto 0)

fabric_fpga_dma_finish_m*_o

Output

std_logic_vector (5 downto 0)

fabric_fpga_rdata_axi_m*_o

Output

out std_logic_vector (127 downto 0)

fabric_fpga_rid_axi_m*_o

Output

out std_logic_vector (4 downto 0)

fabric_fpga_rlast_axi_m*_o

Output

std_logic

fabric_fpga_rresp_axi_m*_o

Output

std_logic_vector (1 downto 0)

fabric_fpga_rvalid_axi_m*_o

Output

std_logic

fabric_fpga_wready_axi_m*_o

Output

std_logic

fabric_fpga_araddr_axi_m*_i

Input

std_logic_vector (39 downto 0)

fabric_fpga_arburst_axi_m*_i

Input

std_logic_vector (1 downto 0)

fabric_fpga_arcache_axi_m*_i

Input

std_logic_vector (3 downto 0)

fabric_fpga_arid_axi_m*_i

Input

std_logic_vector (4 downto 0)

fabric_fpga_arlen_axi_m*_i

Input

std_logic_vector (7 downto 0)

fabric_fpga_arlock_axi_m*_i

Input

std_logic

fabric_fpga_arprot_axi_m*_i

Input

std_logic_vector (2 downto 0)

fabric_fpga_arqos_axi_m*_i

Input

std_logic_vector (3 downto 0)

fabric_fpga_arsize_axi_m*_i

Input

std_logic_vector (2 downto 0)

fabric_fpga_arvalid_axi_m*_i

Input

std_logic

fabric_fpga_awaddr_axi_m*_i

Input

std_logic_vector (39 downto 0)

fabric_fpga_awburst_axi_m*_i

Input

std_logic_vector (1 downto 0)

fabric_fpga_awcache_axi_m*_i

Input

std_logic_vector (3 downto 0)

fabric_fpga_awid_axi_m*_i

Input

std_logic_vector (4 downto 0)

fabric_fpga_awlen_axi_m*_i

Input

std_logic_vector (7 downto 0)

fabric_fpga_awlock_axi_m*_i

Input

std_logic

fabric_fpga_awprot_axi_m*_i

Input

std_logic_vector (2 downto 0)

fabric_fpga_awqos_axi_m*_i

Input

std_logic_vector (3 downto 0)

fabric_fpga_awsize_axi_m*_i

Input

std_logic_vector (2 downto 0)

fabric_fpga_awvalid_axi_m*_i

Input

std_logic

fabric_fpga_bready_axi_m*_i

Input

std_logic

fabric_fpga_dma_last_m*_i

Input

std_logic_vector (5 downto 0)

fabric_fpga_dma_req_m*_i

Input

std_logic_vector (5 downto 0)

fabric_fpga_dma_single_m*_i

Input

std_logic_vector (5 downto 0)

fabric_fpga_rready_axi_m*_i

Input

std_logic

fabric_fpga_wdata_axi_m*_i

Input

std_logic_vector (127 downto 0)

fabric_fpga_wlast_axi_m*_i

Input

std_logic

fabric_fpga_wstrb_axi_m*_i

Input

std_logic_vector (15 downto 0)

fabric_fpga_wvalid_axi_m*_i

Input

std_logic

* : valid for M1 and M2 AXI Master requests

 

AXI Slave requests

The Network interconnect of the SoC (NIC) handles different protocols for different interfaces, including two set of AXI slave interfaces connected to the fabric.

 

Ports

Direction

Type

fabric_fpga_araddr_axi_s*_o

Output

std_logic_vector (39 downto 0)

fabric_fpga_arburst_axi_s*_o

Output

std_logic_vector (1 downto 0)

fabric_fpga_arcache_axi_s*_o

Output

std_logic_vector (3 downto 0)

fabric_fpga_arid_axi_s*_o

Output

std_logic_vector (11 downto 0)

fabric_fpga_arlen_axi_s*_o

Output

std_logic_vector (7 downto 0)

fabric_fpga_arlock_axi_s*_o

Output

std_logic

fabric_fpga_arprot_axi_s*_o

Output

std_logic_vector (2 downto 0)

fabric_fpga_arqos_axi_s*_o

Output

out std_logic_vector (3 downto 0)

fabric_fpga_arregion_axi_s*_o

Output

std_logic_vector (3 downto 0)

fabric_fpga_arsize_axi_s*_o

Output

std_logic_vector (2 downto 0)

fabric_fpga_arvalid_axi_s*_o

Output

std_logic

fabric_fpga_awaddr_axi_s*_o

Output

std_logic_vector (39 downto 0)

fabric_fpga_awburst_axi_s*_o

Output

std_logic_vector (1 downto 0)

fabric_fpga_awcache_axi_s*_o

Output

std_logic_vector (3 downto 0)

fabric_fpga_awid_axi_s*_o

Output

std_logic_vector (11 downto 0)

fabric_fpga_awlen_axi_s*_o

Output

std_logic_vector (7 downto 0)

fabric_fpga_awlock_axi_s*_o

Output

std_logic

fabric_fpga_awprot_axi_s*_o

Output

std_logic_vector (2 downto 0)

fabric_fpga_awqos_axi_s*_o

Output

std_logic_vector (3 downto 0)

fabric_fpga_awregion_axi_s*_o

Output

std_logic_vector (3 downto 0)

fabric_fpga_awsize_axi_s*_o

Output

std_logic_vector (2 downto 0)

fabric_fpga_bready_axi_s*_o

Output

std_logic

fabric_fpga_rready_axi_s*_o

Output

std_logic

fabric_fpga_wdata_axi_s*_o

Output

std_logic_vector (127 downto 0)

fabric_fpga_wlast_axi_s*_o

Output

std_logic

fabric_fpga_wstrb_axi_s*_o

Output

std_logic_vector (15 downto 0)

fabric_fpga_wvalid_axi_s*_o

Output

std_logic

fabric_fpga_awvalid_axi_s*_o

Output

std_logic

fabric_fpga_arready_axi_s*_i

Input

std_logic

fabric_fpga_awready_axi_s*_i

Input

std_logic

fabric_fpga_bid_axi_s*_i

Input

std_logic_vector (11 downto 0)

fabric_fpga_bresp_axi_s*_i

Input

std_logic_vector (1 downto 0)

fabric_fpga_bvalid_axi_s*_i

Input

std_logic

fabric_fpga_rdata_axi_s*_i

Input

std_logic_vector (127 downto 0)

fabric_fpga_rid_axi_s*_i

Input

std_logic_vector (11 downto 0)

fabric_fpga_rlast_axi_s*_i

Input

std_logic

fabric_fpga_rresp_axi_s*_i

Input

std_logic_vector (1 downto 0)

fabric_fpga_rvalid_axi_s*_i

Input

std_logic

fabric_fpga_wready_axi_s*_i

Input

std_logic

* : valid for S1 and S2 slave requests

 

 

DDR request

The Network interconnect of the SoC (NIC) handles different protocols for different interfaces, including a FPGA DDR interface through which the fabric can send requests to the DDR controller in the SoC.

 

Ports

Direction

Type

fabric_fpga_ddr0_arready_o

Output

std_logic

fabric_fpga_ddr0_awready_o

Output

std_logic

fabric_fpga_ddr0_bid_o

Output

std_logic_vector (4 downto 0)

fabric_fpga_ddr0_bresp_o

Output

std_logic_vector (1 downto 0)

fabric_fpga_ddr0_bvalid_o

Output

std_logic

fabric_fpga_ddr0_rdata_o

Output

out std_logic_vector (127 downto 0)

fabric_fpga_ddr0_rid_o

Output

out std_logic_vector (4 downto 0)

fabric_fpga_ddr0_rlast_o

Output

std_logic

fabric_fpga_ddr0_rresp_o

Output

std_logic_vector (1 downto 0)

fabric_fpga_ddr0_rvalid_o

Output

std_logic

fabric_fpga_ddr0_wready_o

Output

std_logic

fabric_fpga_ddr0_araddr_i

Input

std_logic_vector (39 downto 0)

fabric_fpga_ddr0_arburst_i

Input

std_logic_vector (1 downto 0)

fabric_fpga_ddr0_arcache_i

Input

std_logic_vector (3 downto 0)

fabric_fpga_ddr0_arid_i

Input

std_logic_vector (4 downto 0)

fabric_fpga_ddr0_arlen_i

Input

std_logic_vector (7 downto 0)

fabric_fpga_ddr0_arlock_i

Input

std_logic

fabric_fpga_ddr0_arprot_i

Input

std_logic_vector (2 downto 0)

fabric_fpga_ddr0_arqos_i

Input

std_logic_vector (3 downto 0)

fabric_fpga_ddr0_arsize_i

Input

std_logic_vector (2 downto 0)

fabric_fpga_ddr0_arvalid_i

Input

std_logic

fabric_fpga_ddr0_awaddr_i

Input

std_logic_vector (39 downto 0)

fabric_fpga_ddr0_awburst_i

Input

std_logic_vector (1 downto 0)

fabric_fpga_ddr0_awcache_i

Input

std_logic_vector (3 downto 0)

fabric_fpga_ddr0_awid_i

Input

std_logic_vector (4 downto 0)

fabric_fpga_ddr0_awlen_i

Input

std_logic_vector (7 downto 0)

fabric_fpga_ddr0_awlock_i

Input

std_logic

fabric_fpga_ddr0_awprot_i

Input

std_logic_vector (2 downto 0)

fabric_fpga_ddr0_awqos_i

Input

std_logic_vector (3 downto 0)

fabric_fpga_ddr0_awsize_i

Input

std_logic_vector (2 downto 0)

fabric_fpga_ddr0_awvalid_i

Input

std_logic

fabric_fpga_ddr0_bready_i

Input

std_logic

fabric_fpga_ddr0_rready_i

Input

std_logic

fabric_fpga_ddr0_wdata_i

Input

std_logic_vector (127 downto 0)

fabric_fpga_ddr0_wlast_i

Input

std_logic

fabric_fpga_ddr0_wstrb_i

Input

std_logic_vector (15 downto 0)

fabric_fpga_ddr0_wvalid_i

Input

std_logic

 

 

LLPP requests

The Network interconnect of the SoC (NIC) handles different protocols for different interfaces, including four Low Latency Parallel Port (LLPP) interfaces through which R52 cores of the SoC can send requests directly to the fabric.

 

Ports

Direction

Type

fabric_llpp*_araddr_s_o

Output

std_logic_vector (31 downto 0)

fabric_llpp*_arburst_s_o

Output

std_logic_vector (1 downto 0)

fabric_llpp*_arcache_s_o

Output

std_logic_vector (3 downto 0)

fabric_llpp*_arid_s_o

Output

std_logic_vector (11 downto 0)

fabric_llpp*_arlen_s_o

Output

std_logic_vector (7 downto 0)

fabric_llpp*_arlock_s_o

Output

std_logic

fabric_llpp*_arprot_s_o

Output

std_logic_vector (2 downto 0)

fabric_llpp*_arqos_s1_o

Output

std_logic_vector (3 downto 0)

fabric_llpp*_arsize_s_o

Output

std_logic_vector (2 downto 0)

fabric_llpp*_arvalid_s_o

Output

std_logic

fabric_llpp*_awaddr_s_o

Output

std_logic_vector (31 downto 0)

fabric_llpp*_awburst_s_o

Output

std_logic_vector (1 downto 0)

fabric_llpp*_awcache_s_o

Output

std_logic_vector (3 downto 0)

fabric_llpp*_awid_s_o

Output

std_logic_vector (11 downto 0)

fabric_llpp*_awlen_s_o

Output

std_logic_vector (7 downto 0)

fabric_llpp*_awlock_s_o

Output

std_logic

fabric_llpp*_awprot_s_o

Output

std_logic_vector (2 downto 0)

fabric_llpp*_awqos_s_o

Output

std_logic_vector (3 downto 0)

fabric_llpp*_awsize_s_o

Output

std_logic_vector (2 downto 0)

fabric_llpp*_awvalid_s_o

Output

std_logic

fabric_llpp*_bready_s_o

Output

std_logic

fabric_llpp*_rready_s_o

Output

std_logic

fabric_llpp*_wdata_s_o

Output

std_logic_vector (31 downto 0)

fabric_llpp*_wlast_s_o

Output

std_logic

fabric_llpp*_wstrb_s_o

Output

std_logic_vector (3 downto 0)

fabric_llpp*_wvalid_s_o

Output

std_logic

fabric_llpp*_arready_s_i

Input

std_logic

fabric_llpp*_awready_s_i

Input

std_logic

fabric_llpp*_bid_s_i

Input

std_logic_vector (11 downto 0)

fabric_llpp*_bresp_s_i

Input

std_logic_vector (1 downto 0)

fabric_llpp*_bvalid_s_i

Input

std_logic

fabric_llpp*_rdata_s_i

Input

out std_logic_vector (31 downto 0)

fabric_llpp*_rid_s_i

Input

out std_logic_vector (11 downto 0)

fabric_llpp*_rlast_s_i

Input

std_logic

fabric_llpp*_rresp_s_i

Input

std_logic_vector (1 downto 0)

fabric_llpp*_rvalid_s_i

Input

std_logic

fabric_llpp*_wready_s_i

Input

std_logic

* : valid for llpp0, llpp1, llpp2 and llpp3 requests

 

 

Debug and quality of service

The SoC provides several services and error management & monitoring functionalities which are connected to the NIC and can be available through the fabric with the following interface.

 

Ports

Direction

Type

fabric_qos_pprdata_o

Output

std_logic_vector (31 downto 0)

fabric_qos_ppready_o

Output

std_logic

fabric_qos_ppslverr_o

Output

std_logic

fabric_qos_ppaddr_i

Input

std_logic_vector (31 downto 0)

fabric_qos_ppenable_i

Input

std_logic

fabric_qos_ppwdata_i

Input

std_logic_vector (31 downto 0)

fabric_qos_ppwrite_i

Input

std_logic

fabric_qos_presetn_i

Input

std_logic

fabric_qos_psel_i

Input

std_logic

fabric_tnd_hssl_flushin_o

Output

std_logic

fabric_tnd_hssl_trigin_o

Output

std_logic

fabric_tnd_fpga_apb_master_paddr_o

Output

std_logic_vector (31 downto 0)

fabric_tnd_fpga_apb_master_penable_o

Output

std_logic

fabric_tnd_fpga_apb_master_psel_o

Output

std_logic

fabric_tnd_fpga_apb_master_pwdata_o

Output

std_logic_vector (31 downto 0)

fabric_tnd_fpga_apb_master_pwrite_o

Output

std_logic

fabric_tnd_fpga_atb_master_afvalid_o

Output

std_logic

fabric_tnd_fpga_atb_master_atready_o

Output

std_logic

fabric_tnd_fpga_atb_master_syncreq_o

Output

std_logic

fabric_tnd_hssl_apb_master_paddr_o

Output

std_logic_vector (31 downto 0)

fabric_tnd_hssl_apb_master_penable_o

Output

std_logic

fabric_tnd_hssl_apb_master_psel_o

Output

std_logic

fabric_tnd_hssl_apb_master_pwdata_o

Output

std_logic_vector (31 downto 0)

fabric_tnd_hssl_apb_master_pwrite_o

Output

std_logic

fabric_tnd_hssl_atb_master_afready_o

Output

std_logic

fabric_tnd_hssl_atb_master_atbytes_o

Output

std_logic_vector (3 downto 0)

fabric_tnd_hssl_atb_master_atdata_o

Output

std_logic_vector (127 downto 0)

fabric_tnd_hssl_atb_master_atid_o

Output

std_logic_vector (6 downto 0)

fabric_tnd_hssl_atb_master_atvalid_o

Output

std_logic

fabric_tnd_trace_clk_traceoutportintf_o

Output

std_logic

fabric_tnd_trace_ctl_traceoutportintf_o

Output

std_logic

fabric_tnd_trace_data_traceoutportintf_o

Output

std_logic_vector (31 downto 0)

fabric_tsvalue_tsgen_fpga_o

Output

std_logic_vector (63 downto 0)

fabric_tnd_fpga_apb_master_prdata_i

Input

std_logic_vector (31 downto 0)

fabric_tnd_fpga_apb_master_pready_i

Input

std_logic

fabric_tnd_fpga_apb_master_pslverr_i

Input

std_logic

fabric_tnd_fpga_atb_master_afready_i

Input

std_logic

fabric_tnd_fpga_atb_master_atbytes_i

Input

std_logic_vector (3 downto 0)

fabric_tnd_fpga_atb_master_atdata_i

Input

std_logic_vector (127 downto 0)

fabric_tnd_fpga_atb_master_atid_i

Input

std_logic_vector (6 downto 0)

fabric_tnd_fpga_atb_master_atvalid_i

Input

std_logic

fabric_tnd_hssl_apb_master_prdata_i

Input

std_logic_vector (31 downto 0)

fabric_tnd_hssl_apb_master_pready_i

Input

std_logic

fabric_tnd_hssl_apb_master_pslverr_i

Input

std_logic

fabric_tnd_hssl_atb_master_afvalid_i

Input

std_logic

fabric_tnd_hssl_atb_master_atready_i

Input

std_logic

fabric_tnd_hssl_atb_master_syncreq_i

Input

std_logic

fabric_watchdog0_signal_0_o

Output

std_logic

fabric_watchdog0_signal_1_o

Output

std_logic

fabric_watchdog1_signal_0_o

Output

std_logic

fabric_watchdog1_signal_1_o

Output

std_logic

fabric_watchdog2_signal_0_o

Output

std_logic

fabric_watchdog2_signal_1_o

Output

std_logic

fabric_watchdog3_signal_0_o

Output

std_logic

fabric_watchdog3_signal_1_o

Output

std_logic

fabric_tst_pll_lock_o

Output

std_logic_vector (6 downto 0)

fabric_soc_mon_sensor_alarm_o

Output

std_logic

fabric_erom_fpga_cpu0_dbgen_i

Input

std_logic

fabric_erom_fpga_cpu0_hiden_i

Input

std_logic

fabric_erom_fpga_cpu0_hniden_i

Input

std_logic

fabric_erom_fpga_cpu0_niden_i

Input

std_logic

fabric_erom_fpga_cpu1_dbgen_i

Input

std_logic

fabric_erom_fpga_cpu1_hiden_i

Input

std_logic

fabric_erom_fpga_cpu1_hniden_i

Input

std_logic

fabric_erom_fpga_cpu1_niden_i

Input

std_logic

fabric_erom_fpga_cpu2_dbgen_i

Input

std_logic

fabric_erom_fpga_cpu2_hiden_i

Input

std_logic

fabric_erom_fpga_cpu2_hniden_i

Input

std_logic

fabric_erom_fpga_cpu2_niden_i

Input

std_logic

fabric_erom_fpga_cpu3_dbgen_i

Input

std_logic

fabric_erom_fpga_cpu3_hiden_i

Input

std_logic

fabric_erom_fpga_cpu3_hniden_i

Input

std_logic

fabric_erom_fpga_cpu3_niden_i

Input

std_logic

fabric_erom_fpga_cs_dbgen_i

Input

std_logic

fabric_erom_fpga_cs_niden_i

Input

std_logic

fabric_erom_fpga_cs_deviceen_i

Input

std_logic

fabric_erom_fpga_cs_rst_n_i

Input

std_logic

fabric_erom_fpga_debug_en_i

Input

std_logic

 

SERVICE

NX_SERVICE_U_WRAP

Description

The NX_SERVICE_U_WRAP component describes the complete set of signals transiting between the Service bank) and the fabric of NG-Ultra.

Generics

 

bsm_config

type bit_vector(31 downto 0)

default value B"00000000000000000000000000000000"

This generic specifies the configuration for the bitstream functionalities.

 

ahb_config

type bit_vector(31 downto 0)

default value B"00000000000000000000000000000000"

This generic specifies the configuration for the ahb interface.

 

Ports

Lowskew

Ports

Direction

Type

Description

fabric_lowskew_o3                  

Output

std_logic

clk_bsm

fabric_lowskew_o4                

Output

std_logic

tck

fabric_lowskew_o5             

Output

std_logic

clk_otp_out

fabric_lowskew_o6               

Output

std_logic

user_0

fabric_lowskew_i20        

Input

std_logic

otp_clk

fabric_lowskew_i21        

Input

std_logic

user_clk

fabric_lowskew_i22

Input

std_logic

otp_user_clk

fabric_lowskew_i23

Input

std_logic

clk_mrepair

BSM

Ports

Direction

Type

fabric_ahb_direct_data_o              

Output

std_logic_vector(31 downto 0)

fabric_io_out_o                       

Output

std_logic_vector(24 downto 0)

fabric_user_data_o                    

Output

std_logic_vector(31 downto 0)

fabric_user_write_cycle_o             

Output

std_logic

fabric_user_read_cycle_o              

Output

std_logic

fabric_cfg_fabric_user_flag_o         

Output

std_logic

fabric_cfg_fabric_user_unmask_o       

Output

std_logic

fabric_parusr_data_o                  

Output

std_logic_vector(15 downto 0)

fabric_parusr_data_val_o              

Output

std_logic

fabric_jtag_trst_n_o                  

Output

std_logic

fabric_jtag_tms_o                     

Output

std_logic

fabric_jtag_tdi_o                     

Output

std_logic

fabric_jtag_usr1_o                    

Output

std_logic

fabric_jtag_usr2_o                    

Output

std_logic

fabric_direct_data_o                  

Output

std_logic

fabric_status_cold_start_o            

Output

std_logic

fabric_flag_trigger_o                 

Output

std_logic

fabric_flag_error_o                   

Output

std_logic

fabric_flag_ready_o                   

Output

std_logic

fabric_ahb_direct_data_i         

Input

std_logic_vector(31 downto 0)

fabric_io_in_i                   

Input

std_logic

fabric_io_oe_i                   

Input

std_logic

fabric_user_data_i               

Input

std_logic_vector(31 downto 0)

fabric_parusr_cs_i               

Input

std_logic

fabric_parusr_type_i             

Input

std_logic_vector(1 downto 0)

fabric_parusr_data_i             

Input

std_logic_vector(15 downto 0)

fabric_jtag_tdo_usr1_i           

Input

std_logic

fabric_jtag_tdo_usr2_i           

Input

std_logic

fabric_direct_data_i             

Input

std_logic_vector(31 downto 0)

Debug

Ports

Direction

Type

fabric_otp_apb_ready_o                

Output

std_logic

fabric_otp_apb_rdata_o                

Output

std_logic_vector(31 downto 0)

fabric_otp_security_ack_o             

Output

std_logic

fabric_otp_security_bist_end1_o       

Output

std_logic

fabric_otp_security_bist_end2_o       

Output

std_logic

fabric_otp_security_bist_bad_o        

Output

std_logic

fabric_otp_security_bist_fail1_o      

Output

std_logic_vector(7 downto 0)

fabric_otp_security_bist_fail2_o      

Output

std_logic_vector(6 downto 0)

fabric_otp_security_scanout_o         

Output

std_logic_vector(3 downto 0)

fabric_debug_lifecycle_o              

Output

std_logic_vector(3 downto 0)

fabric_debug_fsm_state_o              

Output

std_logic_vector(2 downto 0)

fabric_debug_rst_soft_o               

Output

std_logic

fabric_debug_error_o                  

Output

std_logic

fabric_debug_otp_manager_read_otp_o   

Output

std_logic

fabric_debug_otp_manager_read_done_o  

Output

std_logic

fabric_debug_direct_permission_write_o

Output

std_logic_vector(3 downto 0)

fabric_debug_direct_permission_read_o 

Output

std_logic_vector(3 downto 0)

fabric_debug_frame_use_encryption_o   

Output

std_logic

fabric_debug_frame_permission_frame_o 

Output

std_logic_vector(3 downto 0)

fabric_debug_key_correct_o            

Output

std_logic

fabric_debug_otpmgmt_state_o          

Output

std_logic_vector(2 downto 0)

fabric_debug_otpapb_state_o           

Output

std_logic_vector(2 downto 0)

fabric_debug_otpboot_state_o          

Output

std_logic_vector(2 downto 0)

fabric_debug_otp_reload_err_o         

Output

std_logic

fabric_debug_cpt_retry_o              

Output

std_logic

fabric_debug_bsec_core_status_o       

Output

std_logic_vector(31 downto 0)

fabric_debug_otpboot_curr_addr_o      

Output

std_logic

fabric_debug_access_reg_data_ready_o  

Output

std_logic

fabric_debug_security_error_read_o    

Output

std_logic

fabric_debug_security_boot_done_o     

Output

std_logic

fabric_debug_lock_reg_o               

Output

std_logic

fabric_otp_rstn_i                

Input

std_logic

fabric_otp_apb_addr_i            

Input

std_logic_vector(31 downto 0)

fabric_otp_apb_write_i           

Input

std_logic

fabric_otp_apb_sel_i             

Input

std_logic

fabric_otp_apb_enable_i          

Input

std_logic

fabric_otp_apb_wdata_i           

Input

std_logic_vector(31 downto 0)

fabric_otp_cfg_fabric_apb_en_i   

Input

std_logic

fabric_otp_cfg_loader_read_en_i  

Input

std_logic

fabric_otp_cfg_loader_write_en_i 

Input

std_logic

fabric_otp_cfg_clk_otpm_disable_i

Input

std_logic

fabric_otp_cfg_clk_fab_en_i      

Input

std_logic

fabric_otp_security_rbact1_i     

Input

std_logic

fabric_otp_security_rbact2_i     

Input

std_logic

fabric_otp_security_bistmode_i   

Input

std_logic

fabric_otp_security_force_pdn1_i 

Input

std_logic

fabric_otp_security_scanin_i     

Input

std_logic_vector(4 downto 0)

fabric_otp_security_testmode_i   

Input

std_logic

fabric_otp_security_scanenable_i 

Input

std_logic

OTP User

Ports

Direction

Type

fabric_otp_user_bistmode_i      

Input

std_logic

fabric_otp_user_disturbcheck_i  

Input

std_logic

fabric_otp_user_eccbypass_i     

Input

std_logic

fabric_otp_user_pdn_i           

Input

std_logic

fabric_otp_user_prog_i          

Input

std_logic

fabric_otp_user_rbact1_i        

Input

std_logic

fabric_otp_user_rbact2_i        

Input

std_logic

fabric_otp_user_read_i          

Input

std_logic

fabric_otp_user_redbypass_i     

Input

std_logic

fabric_otp_user_suppadd_i       

Input

std_logic

fabric_otp_user_tm_i            

Input

std_logic

fabric_otp_user_tst_scanenable_i

Input

std_logic

fabric_otp_user_wordlock_i      

Input

std_logic

fabric_otp_user_add_i           

Input

std_logic_vector(6 downto 0)

fabric_otp_user_configreg_i     

Input

std_logic_vector(31 downto 0)

fabric_otp_user_din_i           

Input

std_logic_vector(38 downto 0)

fabric_otp_user_prgwidth_i      

Input

std_logic_vector(2 downto 0)

fabric_otp_user_tst_scanin_i    

Input

std_logic_vector(4 downto 0)

fabric_otp_user_ack_o        

Output

std_logic

fabric_otp_user_bbad_o       

Output

std_logic

fabric_otp_user_bend1_o      

Output

std_logic

fabric_otp_user_bend2_o      

Output

std_logic

fabric_otp_user_calibrated_o 

Output

std_logic

fabric_otp_user_ded_o        

Output

std_logic

fabric_otp_user_disturbed_o  

Output

std_logic

fabric_otp_user_locked_o     

Output

std_logic

fabric_otp_user_progfail_o   

Output

std_logic

fabric_otp_user_pwok_o       

Output

std_logic

fabric_otp_user_sec_o        

Output

std_logic

fabric_otp_user_bist1fail_o  

Output

std_logic_vector(7 downto 0)

fabric_otp_user_bist2fail_o  

Output

std_logic_vector(6 downto 0)

fabric_otp_user_dout_o       

Output

std_logic_vector(40 downto 0)

fabric_otp_user_flagstate_o  

Output

std_logic_vector(3 downto 0)

fabric_otp_user_startword_o  

Output

std_logic_vector(15 downto 0)

fabric_otp_user_tst_scanout_o

Output

std_logic_vector(4 downto 0)

fabric_otp_user_wlromout_o   

Output

std_logic_vector(9 downto 0)

Mrepair OTP

Ports

Direction

Type

fabric_mrepair_fuse_pdn_i            

Input

std_logic

fabric_mrepair_fuse_bistmode_i       

Input

std_logic

fabric_mrepair_fuse_tm_i             

Input

std_logic

fabric_mrepair_fuse_add_i            

Input

std_logic_vector(6 downto 0)

fabric_mrepair_fuse_din_i            

Input

std_logic_vector(38 downto 0)

fabric_mrepair_fuse_read_i           

Input

std_logic

fabric_mrepair_fuse_prog_i           

Input

std_logic

fabric_mrepair_fuse_rbact1_i         

Input

std_logic

fabric_mrepair_fuse_rbact2_i         

Input

std_logic

fabric_mrepair_fuse_tstscanenable_i  

Input

std_logic

fabric_mrepair_fuse_tst_scanin_i     

Input

std_logic_vector(4 downto 0)

fabric_mrepair_fuse_eccbypass_i      

Input

std_logic

fabric_mrepair_fuse_wordlock_i       

Input

std_logic

fabric_mrepair_fuse_suppadd_i        

Input

std_logic

fabric_mrepair_fuse_redbypass_i      

Input

std_logic

fabric_mrepair_fuse_prgwidth_i       

Input

std_logic_vector(2 downto 0)

fabric_mrepair_fuse_configreg_i      

Input

std_logic_vector(31 downto 0)

fabric_mrepair_fuse_disturbchecked_i 

Input

std_logic

fabric_data_shift_en_i               

Input

std_logic

fabric_mrepair_fuse_disturbed_o                        

Output

std_logic

fabric_mrepair_fuse_wlromout_o                         

Output

std_logic_vector(9 downto 0)

fabric_mrepair_fuse_pwok_o                             

Output

std_logic

fabric_mrepair_fuse_dout_o                             

Output

std_logic_vector(40 downto 0)

fabric_mrepair_fuse_startword_o                        

Output

std_logic_vector(15 downto 0)

fabric_mrepair_fuse_ack_o                              

Output

std_logic

fabric_mrepair_fuse_sec_o                              

Output

std_logic

fabric_mrepair_fuse_ded_o                              

Output

std_logic

fabric_mrepair_fuse_progfail_o                         

Output

std_logic

fabric_mrepair_fuse_locked_o                           

Output

std_logic

fabric_mrepair_fuse_bist1fail_o                        

Output

std_logic_vector(7 downto 0)

fabric_mrepair_fuse_bist2fail_o                        

Output

std_logic_vector(6 downto 0)

fabric_mrepair_fuse_bend1_o                            

Output

std_logic

fabric_mrepair_fuse_bend2_o                            

Output

std_logic

fabric_mrepair_fuse_bbad_o                             

Output

std_logic

fabric_mrepair_fuse_tstscanout_o                       

Output

std_logic_vector(4 downto 0)

fabric_mrepair_fuse_flagstate_o                        

Output

std_logic_vector(3 downto 0)

fabric_mrepair_fuse_calibrated_o                       

Output

std_logic

fabric_fuse_status_o                                   

Output

std_logic_vector(2 downto 0)

fabric_mrepair_fuse_prg_block_space_read_error_flag_q_o

Output

std_logic

fabric_mrepair_fuse_ready_o                            

Output

std_logic

Mrepair

Ports

Direction

Type

fabric_data_to_bist_o             

Output

std_logic_vector(23 downto 0)

fabric_shift_en_to_bist_o         

Output

std_logic_vector(23 downto 0)

fabric_sif_load_en_to_bist_o      

Output

std_logic_vector(23 downto 0)

fabric_sif_update_en_to_bist_o    

Output

std_logic_vector(23 downto 0)

fabric_sif_reg_en_to_bist_o       

Output

std_logic_vector(119 downto 0)

fabric_system_data_from_mem_bist_o

Output

std_logic_vector(23 downto 0)

fabric_data_to_system_o           

Output

std_logic

fabric_chip_status_o              

Output

std_logic_vector(71 downto 0)

fabric_global_chip_status_o       

Output

std_logic_vector(2 downto 0)

fabric_pd_ready_o                 

Output

std_logic_vector(23 downto 0)

fabric_system_dataready_o         

Output

std_logic

fabric_decoder_init_ready_o       

Output

std_logic

fabric_data_from_bist_i         

Input

std_logic_vector(23 downto 0)

fabric_system_data_to_mem_bist_i

Input

std_logic_vector(23 downto 0)

fabric_shift_en_i               

Input

std_logic_vector(23 downto 0)

fabric_sif_load_en_i            

Input

std_logic_vector(23 downto 0)

fabric_sif_update_en_i          

Input

std_logic_vector(23 downto 0)

fabric_sif_reg_en_i             

Input

std_logic_vector(119 downto 0)

fabric_tst_atpg_mrepair_i       

Input

std_logic

fabric_data_from_system_i       

Input

std_logic

fabric_end_encoding_i           

Input

std_logic

fabric_pd_active_i              

Input

std_logic_vector(23 downto 0)

fabric_mrepair_mode_i                

Input

std_logic_vector(3 downto 0)

I/O elements

NX_IOB

Description

The NX_IOB component describes a bidirectional port of the design. The behavior is:

 

O <= IO

IO <= I when C = ‘1’

 

Termination is active when T = ‘1’.

 

The NX_IOB can be instantiated anywhere in the design hierarchy. It allows to define buried ports (no signal appears in the ports list).

 

 

 

Figure 22: IOB diagram

 

Generics

Note that the generic assigned to this primitive can be overridden by the addPad or addPads methods in the script file.

 

location

type string

default value Undefined (no default value)

This generic specifies the position of the physical pad in the IO ring. Check the NanoXplore_NG-ULTRA-Datasheet_v1.0_first_draft.pdf document to get the full list of the pads that can be set for location.

Example :

location => “IO_B2_D01_P_SWDO“

 

standard

type string

default value Undefined (no default value)

This generic specifies the electrical standard of the IO, including its power supply and output current drive. The list of the possible values is:

 

Standard value

LVCMOS

SSTL

HSTL

POD

LVDS

 

Example :

standard => “LVCMOS“

 

drive

type string

default value Undefined (no default value)

This generic specifies the electrical standard of the IO, including its power supply and output current drive. The list of the possible values is:

 

drive value

2mA

4mA

8mA

16mA

I

II

 

Example :

drive => “8mA“

 

differential

type string (“true” or “false”)

default value Undefined (no default value)

This generic specifies if the IO uses a differential standard.

Example :

differential => ”true”

 

slewRate

type string (“Slow”, “Medium” or “Fast”)

default value Undefined (no default value)

This generic specifies slewrate of the output buffer.

Example :

slewRate => ”Fast”

 

termination

type string (value in ohms – range depends on variant and bank voltage)

default value ”” (no termination)

This generic specifies the value of the input impedance resistors. It’s specified in Ohms.

Example :

termination => ”50”

 

terminationReference

type string => “floating” or “VT”

default value Undefined (no default value)

This generic specifies if the input termination resistors are floating or connected to the VT voltage reference. Can be useful for some differential input cases.

Example :

termination => ”floating”

 

turbo

type string => “true” or “false”

default value “false”

This generic specifies if the input buffer is in turbo mode. Example :

turbo => ”true”

 

weakTermination

type string => “None”, “PullUp”, “PullDown” or “Keeper”

default value Undefined (no default value)

This generic specifies if the input pad is using weak termination impedance.

Example :

weakTermination => ”PullUp”

 

inputDelayOn

type string => “true” or “false”

default value Undefined (no default value)

This generic enables/disables delay when the pad is configured as an input.

Example :

inputDelayOn => ”true”

 

inputDelayLine

type string => “0” to “63” (“” – empty string to bypass the delay line)

default value Undefined (no default value)

This generic specifies the number of 160 ps delay taps used on the input path.

Example :

inputDelayLine => ”27”

 

outputDelayOn

type string => “true” or “false”

default value Undefined (no default value)

This generic enables/disables delay when the pad is configured as an output.

Example :

outputDelayOn => ”true”

 

outputDelayLine

type string => “0” to “63” (“” – empty string to bypass the delay line)

default value Undefined (no default value)

This generic specifies the number of 160 ps delay taps used on the output path.

Example :

outputDelayLine => ”35”

 

inputSignalSlope

type string => “decimal value in V/ns” (range 0.5 to 20)

default value Undefined (no default value)

This generic has no effect on the implementation process, but it’s used by the timing analyzer. The value must be specified in Volts/ns.

Example :

inputSignalSlope => ”8”

 

outputCapacity

type string “integer_value in pF” (range 0 to 40)

default value Undefined (no default value)

This generic has no effect on the implementation process, but it’s used by the timing analyzer. The value must be specified in ps.

Example :

outputCapacity => ”15”

 

dynDrive

type string

default value Undefined (no default value)

This generic specifies the electrical standard of the IO for dynamic configuration, including its power supply and output current drive. The list of the possible values is:

 

drive value

2mA

4mA

8mA

16mA

I

II

 

Example :

dynDrive => “8mA“

 

dynTerm

type string (value in ohms )

default value ”” (no termination)

This generic specifies the value of the input impedance resistors through dynamic configuration. It’s specified in Ohms.

Example :

dynTerm => ”50”

 

locked

type bit => ‘0’ or ‘1’

default value ‘0’

This generic specifies if the “location” on the instantiated NX_IOB is done in the instantiation (locked => ‘1’) or in the Nxpython script fine (locked => ‘0’).

Example :

location => ”IO_B2_D01_P_SWDO”,

locked => ‘1’

 

Ports

Ports

Direction

Type

Description

I

Input

std_logic

From FPGA fabric

C

Input

std_logic

Tristate control

‘0’: High impedance

‘1’: Enable output

T

Input

std_logic

Termination control

‘0’: No calibration

‘1’: calibration activated

O

output

std_logic

To FPGA fabric

IO

inout

std_logic

External pad

 

Example

This documentation only provides the instantiation of the component.

 

IOB_0 : NX_IOB

generic map(

location => “IO_B2_D01_P_SWDO”,

standard => “LVCMOS“,

drive => “8mA“,

differential => “LVCMOS“,

slewRate => “Fast”,

termination => “50”,

terminationReference => “floating”,

turbo => “true”,

weakTermination => “PullUp”,

inputDelayLine => “10”,

outputDelayLine => “17”,

outputCapacity => “15”,

locked => ‘1’

)

port map (

I => fromFPGAcore

, O => toFPGAcore

, C => enable

, T => ’0’

, IO => open -- A signal name is not required on the external

-- signal

-- The pad will take the name of the instance

);

 

NX_IOB_I

Description

The NX_IOB_I component describes an input port of the design. The behavior is:

 

O <= IO

 

Termination is active when T = ‘1’.

 

The NX_IOB can be instantiated anywhere in the design hierarchy. It allows to define buried ports (no signal appears in the ports list).

 

 

Figure 23: IOB_I diagram

 

Generics

Note that the generic assigned to this primitive can be overridden by the addPad or addPads methods used in nxpython script file.

 

location

type string

default value Undefined (no default value)

This generic specifies the position of the physical pad in the IO ring. Check the NanoXplore_NG-ULTRA-Datasheet_v1.0_first_draft.pdf document to get the full list of the pads that can be set for location.

Example :

location => “IO_B2_D01_P_SWDO“

 

standard

type string

default value Undefined (no default value)

This generic specifies the electrical standard of the IO, including its power supply and output current drive. The list of the possible values is:

 

Standard value

LVCMOS

SSTL

HSTL

POD

LVDS

 

Example :

standard => “LVCMOS“

 

drive

type string

default value Undefined (no default value)

This generic specifies the electrical standard of the IO, including its power supply and output current drive. The list of the possible values is:

 

drive value

2mA

4mA

8mA

16mA

I

II

 

Example :

drive => “8mA“

 

differential

type string (“true” or “false”)

default value Undefined (no default value)

This generic specifies if the IO uses a differential standard.

Example :

differential => ”true”

 

slewRate

type string (“Slow”, “Medium” or “Fast”)

default value Undefined (no default value)

This generic specifies slewrate of the output buffer.

Example :

slewRate => ”Fast”

 

termination

type string (value in ohms – range depends on variant and bank voltage)

default value ”” (no termination)

This generic specifies the value of the input impedance resistors. It’s specified in Ohm.

Example :

termination => ”50”

 

terminationReference

type string => “floating” or “VT”

default value Undefined (no default value)

This generic specifies if the input termination resistors are floating or connected to the VT voltage reference. Can be useful for some differential input cases.

Example :

termination => ”floating”

 

turbo

type string => “true” or “false”

default value “false”

This generic specifies if the input buffer is in turbo mode. Example :

turbo => ”true”

 

weakTermination

type string => “None”, “PullUp”, “PullDown” or “Keeper”

default value Undefined (no default value)

This generic specifies if the input pad is using weak termination impedance.

Example :

weakTermination => ”PullUp”

 

inputDelayOn

type string => “true” or “false”

default value Undefined (no default value)

This generic enables/disables delay when the pad is configured as an input.

Example :

inputDelayOn => ”true”

 

inputDelayLine

type string => “0” to “63” (“” – empty string to bypass the delay line)

default value Undefined (no default value)

This generic specifies the number of 160 ps delay taps used on the input path.

Example :

inputDelayLine => ”27”

 

outputDelayOn

type string => “true” or “false”

default value Undefined (no default value)

This generic enables/disables delay when the pad is configured as an output.

Example :

outputDelayOn => ”true”

 

outputDelayLine

type string => “0” to “63” (“” – empty string to bypass the delay line)

default value Undefined (no default value)

This generic specifies the number of 160 ps delay taps used on the output path.

Example :

outputDelayLine => ”35”

 

inputSignalSlope

type string => “decimal value in V/ns” (range 0.5 to 20)

default value Undefined (no default value)

This generic has no effect on the implementation process, but it’s used by the timing analyzer. The value must be specified in Volts/ns.

Example :

inputSignalSlope => ”8”

 

outputCapacity

type string “integer_value in pF” (range 0 to 40)

default value Undefined (no default value)

This generic has no effect on the implementation process, but it’s used by the timing analyzer. The value must be specified in ps.

Example :

outpuCapacity => ”15”

 

locked

type bit => ‘0’ or ‘1’

default value ‘0’

This generic specifies if the “location” on the instantiated NX_IOB is done in the instantiation (locked => ‘1’) or in the Nxpython script fine (locked => ‘0’).

Example :

location => ”IO_B2_D01_P_SWDO”,

locked => ‘1’

 

Ports

Ports

Direction

Type

Description

C

Input

Std_logic

Not used. Must be left “open” or unconnected

T

Input

std_logic

Termination control

‘0’ : No termination

‘1’ : Input termination activated

O

output

std_logic

From FPGA fabric

IO

Input

std_logic

External pad

 

Example

This documentation only provides the instantiation of the component.

 

NX_IOB_O

Description

The NX_IOB_O component describes an output port of the design. The behavior is:

 

IO <= I when C = ‘1’ else ‘Z’

 

Termination is active when T = ‘1’.

 

The NX_IOB can be instantiated anywhere in the design hierarchy. It allows to define buried ports (no signal appears in the ports list).

 

 

Figure 24: IOB_O diagram

 

Generics

Note that the generic assigned to this primitive can be overridden by the addPad or addPads methods in the script file.

 

location

type string

default value Undefined (no default value)

This generic specifies the position of the physical pad in the IO ring. Check the NanoXplore_NG-ULTRA-Datasheet_v1.0_first_draft.pdf document to get the full list of the pads that can be set for location.

Example :

location => “IO_B2_D01_P_SWDO“

 

standard

type string

default value Undefined (no default value)

This generic specifies the electrical standard of the IO, including its power supply and output current drive. The list of the possible values is:

 

Standard value

LVCMOS

SSTL

HSTL

POD

LVDS

 

Example :

standard => “LVCMOS“

 

drive

type string

default value Undefined (no default value)

This generic specifies the electrical standard of the IO, including its power supply and output current drive. The list of the possible values is:

 

drive value

2mA

4mA

8mA

16mA

I

II

 

Example :

drive => “8mA“

 

differential

type string (“true” or “false”)

default value Undefined (no default value)

This generic specifies if the IO uses a differential standard.

Example :

differential => ”true”

 

slewRate

type string (“Slow”, “Medium” or “Fast”)

default value Undefined (no default value)

This generic specifies slewrate of the output buffer.

Example :

slewRate => ”Fast”

 

termination

type string (value in ohms – range depends on variant and bank voltage)

default value ”” (no termination)

This generic specifies the value of the input impedance resistors. It’s specified in Ohms.

Example :

termination => ”50”

 

terminationReference

type string => “floating” or “VT”

default value Undefined (no default value)

This generic specifies if the input termination resistors are floating or connected to the VT voltage reference. Can be useful for some differential input cases.

Example :

termination => ”floating”

 

turbo

type string => “true” or “false”

default value “false”

This generic specifies if the input buffer is in turbo mode. Example :

turbo => ”true”

 

weakTermination

type string => “None”, “PullUp”, “PullDown” or “Keeper”

default value Undefined (no default value)

This generic specifies if the input pad is using weak termination impedance.

Example :

weakTermination => ”PullUp”

 

inputDelayOn

type string => “true” or “false”

default value Undefined (no default value)

This generic enables/disables delay when the pad is configured as an input.

Example :

inputDelayOn => ”true”

 

inputDelayLine

type string => “0” to “63” (“” – empty string to bypass the delay line)

default value Undefined (no default value)

This generic specifies the number of 160 ps delay taps used on the input path.

Example :

inputDelayLine => ”27”

 

outputDelayOn

type string => “true” or “false”

default value Undefined (no default value)

This generic enables/disables delay when the pad is configured as an output.

Example :

outputDelayOn => ”true”

 

outputDelayLine

type string => “0” to “63” (“” – empty string to bypass the delay line)

default value Undefined (no default value)

This generic specifies the number of 160 ps delay taps used on the output path.

Example :

outputDelayLine => ”35”

 

inputSignalSlope

type string => “decimal value in V/ns” (range 0.5 to 20)

default value Undefined (no default value)

This generic has no effect on the implementation process, but it’s used by the timing analyzer. The value must be specified in Volts/ns.

Example :

inputSignalSlope => ”8”

 

outputCapacity

type string “integer_value in pF” (range 0 to 40)

default value Undefined (no default value)

This generic has no effect on the implementation process, but it’s used by the timing analyzer. The value must be specified in ps.

Example :

outpuCapacity => ”15”

 

locked

type bit => ‘0’ or ‘1’

default value ‘0’

This generic specifies if the “location” on the instantiated NX_IOB is done in the instantiation (locked => ‘1’) or in the Nxpython script fine (locked => ‘0’).

Example :

location => ”IO_B2_D01_P_SWDO”,

locked => ‘1’

 

 

Ports

Ports

Direction

Type

Description

I

input

std_logic

From FPGA fabric

C

input

std_logic

Tristate control (‘0’ for High Z)

T

input

std_logic

Not used. . Must be left “open” or unconnected

IO

output

std_logic

External pad

 

 

Example

This documentation only provides the instantiation of the component.

 

IOB_0 : NX_IOB_O

 

generic map(

location => “IO_B12_D10_N”,

standard => “LVCMOS“,

drive => “4mA“,

slewRate => “Fast”,

outputDelayOn => ‘1’,

outputDelayLine => “17”,

outputCapacity => “15”,

locked => ‘1’

)

port map (

I => fromFPGA

, C => enable

, IO => open -- A signal name is not required on the external

-- signal

-- The pad will take the name of the instance

);

 

SERializers and DESerializers

Introduction

The NG-ULTRA complex I/O banks provide serializers and deserializer features.

Each serializer or deserializer can use a serialization factor of 2, 3, 4 or 5.

In addition in each I/O pair, the serializers/deserializers associated to the “_P” pad can be chained with its neighbor (associated to the “_N” pad) allowing thus serialization/deserialization factors of 6, 7, 8, 9 and 10.

The serializer/deserializer data path requires two clocks: bit clock (Fast clock – FCK) and word clock (Slow clock – SCK).

Serializers include optional output delay lines for both output and tri-state command. Although output delay lines can be dynamically controlled, serializer delays are usually configured in static mode – most often no delay.

Deserializers require a proper data/clock alignment mechanism for safe sampling, as well as word alignment to recover the original words. Data/clock alignment requires a dynamic control of the delay lines to adjust the phase relationship of the sampled data and the fast clock. This procedure is called Dynamic Phase Alignment (DPA). It requires a training sequence.

NG-ULTRA complex IO banks provide hardware support for DPA. The dynamic control of the delay lines requires an additional clock to read or write into the delay registers. This clock is called DCK. It can be synchronous or asynchronous with the data path clocks SCK and FCK.

 

All I/O related delay lines have 0 to 63 x 100 ps steps delays.

 

SERDES architecture overview

The serializers/deserializers architecture contains two main blocks :

  • Data path

  • Delay control path

 

Figure 25: SERDES data path simplified diagram

Figure 26: SERDES delay lines control block simplified diagram

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DPA : Dynamic Phase Adjustment

 

NG-ULTRA architecture provides hardware support for Dynamic Phase Adjustment on NX_DES. The following describes how to implement the adjustment procedure.

In the complex banks, all I/Os include three user’s selectable and adjustable delay lines that can be selected with “DS(1:0)” sub-address input. Those registers can be read and written with a simple microprocessor-like interface.

Each NX_DES or NX_SER include three delay lines, respectively for output (and tri-state control), input path and DPA path delays. The delay value on each one of those three paths (number of 100 ps delay taps) is defined by the value written into the corresponding delay register.

  • The output (and tri-state control) delay register controls the delay inserted on the output data path.

  • The input delay register controls the delay inserted between the input pad and the input register.

  • The DPA delay register controls the delay inserted between the input pad and the DPA input register.

The DPA logic allows to generate flags (FLD and FLG) to inform about the data input and fast clock relative phase :

  • FLD : this flag goes high when a transition on the data line at the output of the DPA delay line, occurs between the falling and the rising edge of the sampling clock (FCK, fast clock).

  • FLG : this flag goes high when a transition on the data line at the output of the DPA delay line, occurs between the rising and the falling edge of the sampling clock (FCK, fast clock).

  • FZ : Active low flags reset

  • By modifying the value of the DPA delay line, data/clock relationship can be analyzed by monitoring the FLD and FLG flags – and then deduce the optimal delay value to be written to the input delay register.

  • The following figures show the FLD and FLG flags behavior versus the transition detection on the DPA delay line output.

 

Figure 27: FLD activation

 

 

 

Figure 28: FLG activation

 

 

Write and read accesses to the delay registers can be easily managed with the following signals :

  • DCK : delay registers clock (can be asynchronous with SCK/FCK). Usually 2 to 20 MHz. Write operations occur on DCK rising edge.

  • DID(5:0) : address identifier of the considered I/O in the complex bank (0 to 33).

  • DRA(5:0) : address of the I/O in the considered complex bank (0 to 33). Note that when DRA = DID, the DRO outputs, as well as FLD and FLG flags outputs of the considered I/O go to low impedance (allowing thus to be read by the fabric).

  • DS(1:0) : allow to select the destination register into the DRA selected I/O. See next table for details.

DS value

Selected delay register

 

 

00

Output (and tri-state control) delay register

01

Input delay register

10

DPA delay register

11

Reserved

 

  • DRI(5:0) :value to be written into the selected register.

  • DRL : active high load (write enable)

 

Figure 29: Writing and reading delay registers

 

 

Note :

For deserialization, NanoXplore provides an IP Core that automatically adjusts the delay lines in order to properly align the sampled data with the fast clock. It also provides word alignment.

 

NanoXplore recommends to use NXcore – customizable IP Core generator - to use deserializers with automatic data/clock phase alignment and word alignment.

The IP Core uses an automatic procedure – launched by the user at any time – to proceed to the input delays calibration and word alignment on all DESerializers of the same group.

The IP Core also generates the required clocks (SCK, FCK and DCK) from a word clock input. It requires using the neighboring ClocK Generator block (CKG1 for I/O complex banks 11 & 12 for example).

Handshake signals with the transmitter and calibration status are provided to the user application. Among the available signals :

  • LAUNCH_CALIB (input) : launches the calibration process (on a rising edge)

  • TRAINING_REQ_OUT (output) : The IP Core requests the transmitter to send the serialized “TrainingValue” to the DESerializer(s).

  • TRAINING_ACK_IN (input) : The transmitter is ready and sends the serialized “TrainingValue”

  • TRAINING_REQ_IN (input) : if the IP Core is used as transmitter, the receiver might require a calibration sequence where the transmitter must send the serialized “TrainingValue”. TRAINING_REQ_IN is the request input of the transmitter.

  • TRAINING_ACK_OUT (output) : When the transmitter receives a request from the receiver, it sends the serialized “TrainingValue” and activates the TRAINING_ACK output to the receiver.

  • CALIB_DONE (output) : goes high to state that the calibration process is done.

  • CALIB_ERROR (output) : Active high status bit to state that the calibration was not successful.

Figure 30: SER_DES IP Core simplified diagram

 

NX_DES

Description

The NX_DES is a high performance DESerializer. The complex banks allows to configure the I/Os as DESerializers with deserialization factor from 2 to 5. Higher deserialization factors (6, 7, 8, 9 and 10) can be achieved by combining the two deserializers of a differential IO pair.

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 31 NX_DES primitive

 

Generics

data_size

type integer (range 2 to 10)

default value 5

This generic specifies the deserialization factor.

Example :

data_size => 8

 

location

type string

default value Undefined (no default value)

This generic specifies the position of the physical pad in the IO ring. Check the NanoXplore_NG-ULTRA-Datasheet_v1.0_first_draft.pdf document to get the full list of the pads that can be set for location.

Example :

location => “IO_B2_D01_P_SWDO“

 

standard

type string

default value Undefined (no default value)

This generic specifies the electrical standard of the IO, including its power supply and output current drive. The list of the possible values is:

 

Standard value

LVCMOS

SSTL

HSTL

POD

LVDS

 

Example :

standard => “LVCMOS“

 

drive

type string

default value Undefined (no default value)

This generic specifies the electrical standard of the IO, including its power supply and output current drive. The list of the possible values is:

 

drive value

2mA

4mA

8mA

16mA

I

II

 

Example :

drive => “8mA“

 

differential

type string (“true” or “false”)

default value Undefined (no default value)

This generic specifies if the IO uses a differential standard.

Example :

differential => ”true”

 

termination

type string (value in ohms – range depends on variant and bank voltage)

default value ”” (no termination)

This generic specifies the value of the input impedance resistors. It’s specified in Ohms.

Example :

termination => ”50”

 

terminationReference

type string => “floating” or “VT”

default value Undefined (no default value)

This generic specifies if the input termination resistors are floating or connected to the VT voltage reference. Can be useful for some differential input cases.

Example :

termination => ”floating”

 

turbo

type string => “true” or “false”

default value “false”

This generic specifies if the input buffer is in turbo mode. Example :

turbo => ”true”

 

weakTermination

type string => “None”, “PullUp”, “PullDown” or “Keeper”

default value Undefined (no default value)

This generic specifies if the input pad is using weak termination impedance.

Example :

weakTermination => ”PullUp”

 

inputDelayLine

type string => “0” to “63” (“” – empty string with no character or space for dynamic

delay)

default value “” (set to “” (empty string) by NXcore to allow dynamic delay for calibation

process)

This generic specifies the number of 100 ps delay taps used on the input path.

Example for dynamic delay (required for calibration process) :

inputDelayLine => “ “, -- Dynamic input delay (FLD and FLG are available)

 

Example for static delay (no calibration can be carried out) :

inputDelayLine => “27“, -- Static input delay (FLD and FLG are not available)

 

inputSignalSlope

type string => “decimal value in V/ns” (range 0.5 to 20)

default value Undefined (no default value)

This generic has no effect on the implementation process, but it’s used by the timing analyzer. The value must be specified in Volts/ns.

Example :

inputSignalSlope => ”8”

 

dpath_dynamic

type bit

default value ‘0’

This generic allows to select dynamic delay.

Example :

dpath_dynamic => ‘1’

 

 

Ports

 

Ports

Direction

Type

Description

FCK

In

Std_logic

Fast clock (bit clock)

SCK

In

Std_logic

Slow clock (word clock)

R

In

Std_logic

 

Active high Reset

IO

In

Std_logic

Input pad

O

Out

Std_logic_vector

(data_size-1 downto 0)

Sampled word to FPGA fabric

 

 

 

 

DCK

In

Std_logic

Delay lines management registers clock

DRL

In

Std_logic

Delay Registers Load

DIG

In

Std_logic

‘0’ for Multicast write (*)

‘1’ for normal operation

DS

In

Std_logic_vector

(1 downto 0)

Delay Select :

00 => out & tri-state regs

01 => input delay register

10 => DPA delay register

11 => RESERVED

 

DRA

In

Std_logic_vector

(5 downto 0)

Delay address (0 to 33)

DRI

In

Std_logic_vector

(5 downto 0)

Data input to delay registers

DRO

Out (with tri-state)

Std_logic_vector

(5 downto 0)

Delay value being read

Active when DRA = DID else high impedance

DID

Out

Std_logic_vector

(5 downto 0)

Pad address identification

FZ

In

Std_logic

Active low Flags Reset

FLD

Out (with tri-state)

Std_logic

Early capture flag Active when DRA = DID else high impedance

FLG

Out (with tri-state)

Std_logic

Late capture flag Active when DRA = DID else high impedance

(*) : When DIG is low, any write cycle will write the same value into all corresponding registers – selected by DS(1:0) - of the 34 I/Os in the current complex I/O bank.

DIG must be high for normal operation, particularly for delay calibration.

 

NX _SER

Description

The NX_SER is a high performance SERializer. The complex banks allows to configure the I/Os as SERializers with serialization factor from 2 to 5. Higher serialization factors (6, 7, 8, 9 and 10) can be achieved by combining the two serializers of a differential IO pair.

 

 

 

 

 

 

 

 

 

 

 

Figure 32: NX_SER primitive

 

Generics

 

data_size

type integer

default value Undefined (no default value)

This generic specifies the serialization factor.

Example :

data_size => 8

 

location

type string

default value Undefined (no default value)

This generic specifies the position of the physical pad in the IO ring. Check the NanoXplore_NG-ULTRA-Datasheet_v1.0_first_draft.pdf document to get the full list of the pads that can be set for location.

Example :

location => “IO_B2_D01_P_SWDO“

 

standard

type string

default value Undefined (no default value)

This generic specifies the electrical standard of the IO, including its power supply and output current drive. The list of the possible values is:

 

Standard value

LVCMOS

SSTL

HSTL

POD

LVDS

 

Example :

standard => “LVCMOS“

 

drive

type string

default value Undefined (no default value)

This generic specifies the electrical standard of the IO, including its power supply and output current drive. The list of the possible values is:

 

drive value

2mA

4mA

8mA

16mA

I

II

 

Example :

drive => “8mA“

 

differential

type string (“true” or “false”)

default value Undefined (no default value)

This generic specifies if the IO uses a differential standard.

Example :

differential => ”true”

 

termination

type string (value in ohms – range depends on variant and bank voltage)

default value ”” (no termination)

This generic specifies the value of the input impedance resistors. It’s specified in Ohms.

Example :

termination => ”50”

 

terminationReference

type string => “floating” or “VT”

default value Undefined (no default value)

This generic specifies if the input termination resistors are floating or connected to the VT voltage reference. Can be useful for some differential input cases.

Example :

termination => ”floating”

 

turbo

type string => “true” or “false”

default value “false”

This generic specifies if the input buffer is in turbo mode. Example :

turbo => ”true”

 

weakTermination

type string => “None”, “PullUp”, “PullDown” or “Keeper”

default value Undefined (no default value)

This generic specifies if the input pad is using weak termination impedance.

Example :

weakTermination => ”PullUp”

 

outputDelayLine

type string => “0” to “63” (“” – empty string to bypass the delay line)

default value “”

This generic specifies the number of 100 ps delay taps used on the output path. Example :

outputDelayLine => “35”

 

inputSignalSlope

type string => “decimal value in V/ns” (range 0.5 to 20)

default value Undefined (no default value)

This generic has no effect on the implementation process, but it’s used by the timing analyzer. The value must be specified in Volts/ns.

Example :

inputSignalSlope => ”8”

 

spath_dynamic

type bit

default value ‘0’

This generic allows to select dynamic delay.

Example :

dpath_dynamic => ‘1’

 

 

Ports

 

Ports

Direction

Type

Description

FCK

In

Std_logic

Fast clock (bit clock)

SCK

In

Std_logic

Slow clock (word clock)

R

In

Std_logic

 

Active high Reset

IO

Out

Std_logic

Input pad

I

In

Std_logic_vector

(data_size-1 downto 0)

Data to be serialized from fabric

 

 

 

 

DCK

In

Std_logic

Delay lines management registers clock

DRL

In

Std_logic

Delay Registers Load

DS

In

Std_logic_vector

(1 downto 0)

Delay Select :

00 => out & tri-state regs

01 => input delay register

10 => DPA delay register

11 => RESERVED

 

DRA

In

Std_logic_vector

(5 downto 0)

Delay address (0 to 33)

DRI

In

Std_logic_vector

(5 downto 0)

Data input to delay registers

DRO

Out (with tri-state)

Std_logic_vector

(5 downto 0)

Delay value being read

Active when DRA = DID, else high-impedance)

DID

Out

Std_logic_vector

(5 downto 0)

Pad address identifier (0 to 33)

 

 

NX _SERDES

Description

The NX_SERDES combines functionalities of NX_SER and NX_DES to perform a high performance SERializer/DESerializer component.

 

 

Generics

 

data_size

type integer (range 2 to 10)

default value 5

This generic specifies the serialization/deserialization factor.

Example :

data_size => 8

 

location

type string

default value Undefined (no default value)

This generic specifies the position of the physical pad in the IO ring. Check the NanoXplore_NG-ULTRA-Datasheet_v1.0_first_draft.pdf document to get the full list of the pads that can be set for location.

Example :

location => “IO_B2_D01_P_SWDO“

 

standard

type string

default value Undefined (no default value)

This generic specifies the electrical standard of the IO, including its power supply and output current drive. The list of the possible values is:

 

Standard value

LVCMOS

SSTL

HSTL

POD

LVDS

 

Example :

standard => “LVCMOS“

 

drive

type string

default value Undefined (no default value)

This generic specifies the electrical standard of the IO, including its power supply and output current drive. The list of the possible values is:

 

drive value

2mA

4mA

8mA

16mA

I

II

 

Example :

drive => “8mA“

 

differential

type string (“true” or “false”)

default value Undefined (no default value)

This generic specifies if the IO uses a differential standard.

Example :

differential => ”true”

 

slewRate

type string (“Slow”, “Medium” or “Fast”)

default value Undefined (no default value)

This generic specifies slewrate of the output buffer.

Example :

slewRate => ”Fast”

 

termination

type string (value in ohms – range depends on variant and bank voltage)

default value ”” (no termination)

This generic specifies the value of the input impedance resistors. It’s specified in Ohms.

Example :

termination => ”50”

 

terminationReference

type string => “floating” or “VT”

default value Undefined (no default value)

This generic specifies if the input termination resistors are floating or connected to the VT voltage reference. Can be useful for some differential input cases.

Example :

termination => ”floating”

 

turbo

type string => “true” or “false”

default value “false”

This generic specifies if the input buffer is in turbo mode. Example :

turbo => ”true”

 

weakTermination

type string => “None”, “PullUp”, “PullDown” or “Keeper”

default value Undefined (no default value)

This generic specifies if the input pad is using weak termination impedance.

Example :

weakTermination => ”PullUp”

 

inputDelayLine

type string => “0” to “63” (“” – empty string to bypass the delay line)

default value Undefined (no default value)

This generic specifies the number of 100 ps delay taps used on the input path.

Example :

inputDelayLine => ”27”

 

outputDelayLine

type string => “0” to “63” (“” – empty string to bypass the delay line)

default value Undefined (no default value)

This generic specifies the number of 100 ps delay taps used on the output path.

Example :

outputDelayLine => ”35”

 

inputSignalSlope

type string => “decimal value in V/ns” (range 0.5 to 20)

default value Undefined (no default value)

This generic has no effect on the implementation process, but it’s used by the timing analyzer. The value must be specified in Volts/ns.

Example :

inputSignalSlope => ”8”

 

outputCapacity

type string “integer_value in pF” (range 0 to 40)

default value Undefined (no default value)

This generic has no effect on the implementation process, but it’s used by the timing analyzer. The value must be specified in ps.

Example :

outpuCapacity => ”15”

 

cpath_registered

type bit

default value ‘0’

This generic allows to select delay register in enable path when set to ‘1’.

 

spath_dynamic

type bit

default value ‘0’

This generic allows to select dynamic delay control on serializer path.

Example :

spath_dynamic => ‘1’

 

dpath_dynamic

type bit

default value ‘0’

This generic allows to select dynamic delay control on deserializer path.

Example :

dpath_dynamic => ‘1’

 

 

Ports

 

Ports

Direction

Type

Description

FCK

In

Std_logic

Fast clock (bit clock)

SCK

In

Std_logic

Slow clock (word clock)

RTX

In

Std_logic

 

Active high Reset on TX path

RRX

In

Std_logic

 

Active high Reset on RX path

CI

In

Std_logic

Configure pad in input mode when set to 1 else pad in output mode

CCK

In

Std_logic

Control clock for the register on the enable path

CL

In

Std_logic

Control load to force use of register on enable path

CR

In

Std_logic

Control Reset used to reset the register on enable path

IO

inout

Std_logic

Inout data pad. Configured as input when CI=1 and output when CI=0

I

In

Std_logic_vector

(data_size-1 downto 0)

Data to be serialized from the fabric

O

Out

Std_logic_vector

(data_size-1 downto 0)

Data to be deserialized and sent to the fabric

DELAY CONTROL

DCK

In

Std_logic

Delay lines management registers clock

DRL

In

Std_logic

Delay Registers Load

DIG

In

Std_logic

‘0’ for Multicast write (*)

‘1’ for normal operation

DS

In

Std_logic_vector

(1 downto 0)

Delay Select :

00 => out & tri-state regs

01 => input delay register

10 => DPA delay register

11 => RESERVED

 

DRA

In

Std_logic_vector

(5 downto 0)

Delay Register address (0 to 33)

DRI

In

Std_logic_vector

(5 downto 0)

Data input to delay registers

FZ

In

Std_logic

Active low Flags Reset

DRO

Out (with tri-state)

Std_logic_vector

(5 downto 0)

Delay value being read

Active when DRA = DID, else high-impedance)

DID

Out

Std_logic_vector

(5 downto 0)

Pad address identification (0 to 33)

FLD

Out (with tri-state)

Std_logic

Early capture flag Active when DRA = DID else high impedance

FLG

Out (with tri-state)

Std_logic

Late capture flag Active when DRA = DID else high impedance

(*) : When DIG is low, any write cycle will write the same value into all corresponding registers – selected by DS(1:0) - of the 34 I/Os in the current complex I/O bank.

DIG must be high for normal operation, particularly for delay calibration.

NX_DFR

Description

The NX_DFR component describes a DFF located in the ring. The behaviour is the same as a core DFF except there is no context (no initialization).

Generics

 

dff_edge

type bit

default value ‘0’

This generic represents the front polarity of the clock of the associated DFF. ‘0’ is for rising edge and ‘1’ for falling edge.

 

dff_init

type bit

default value ‘0’

This generic represents whether the DFF considers the R (reset) input. ‘0’ is for ignore and ‘1’ for using connected net.

 

dff_load

type bit

default value ‘0’

This generic represents whether the DFF considers the L (load) input. ‘1’ is for ignore and ‘0’ for using connected net.

It is inverted compared with NX_DFF

 

dff_sync

type bit

default value ‘0’

This generic represents whether the DFF reset is synchronous or asynchronous. ‘0’ is for asynchronous and ‘1’ for synchronous.

 

dff_type

type bit

default value 0

This generic represents whether the reset must initialize the DFF to 0 or 1. dff_type is set to ‘0’ for reset initializing the DFF to 0, dff_type is set to ‘1’ for reset initializing the DFF to 1. dff_type can also be set to 2 to configure set/reset on signal.

 

Ports

Ports

Direction

Type

Description

I

input

std_logic

Input

CK

input

std_logic

Clock

L

input

std_logic

Load

R

input

std_logic

Reset, active high

O

output

std_logic

Output

 

Example

This documentation only provides the instantiation of the component.

 

 

NX_IDDFR

Description

The NX_IDDFR component describes an input double data rate resynchronizer as it is shown is the following diagram:

An example of double data rate resynchronization could be:

 

Generics

 

location

type string

default value ““

This generic specifies the position of the spot connected to the physical pad in the IO ring.

The format is IOBxx:IODyy.ID with xx the index of the bank in [2:5;8;13] and yy index of the pad in [1;34].

Example for physical pad location IOB02D01P:

location => “IOB2:IOD3.ID“

 

dff_load

type bit

default value ‘0’

This generic represents whether the DFF considers the L (load) input. ‘1’ is for ignore and ‘0’ for using connected net.

It is inverted compared with NX_DFF

 

dff_sync

type bit

default value ‘0’

This generic represents whether the DFF reset is synchronous or asynchronous. ‘0’ is for asynchronous and ‘1’ for synchronous.

 

dff_type

type bit

default value 0

This generic represents whether the reset must initialize the DFF to 0 or 1. dff_type is set to ‘0’ for reset initializing the DFF to 0, dff_type is set to ‘1’ for reset initializing the DFF to 1. dff_type can also be set to 2 to configure set/reset on signal.

 

Ports

Ports

Direction

Type

Description

I

input

std_logic

Input double data rate

CK

input

std_logic

Clock

L

input

std_logic

Load

R

input

std_logic

Reset, active high

O1

output

std_logic

Output single data rate caught on falling edge

O2

output

std_logic

Output single data rate caught on rising edge

 

Example

This documentation only provides the instantiation of the component.

  

 

NX_ODDFR

Description

The NX_ODDFR component describes an output double data rate resynchronizer as it is shown is the following diagram:

 

An example of double data rate resynchronization could be:

 

Generics

 

location

type string

default value ““

This generic specifies the position of the spot connected to the physical pad in the IO ring.

The format is IOBxx:IODyy.OD with xx the index of the bank in [2:5;8;13] and yy index of the pad in [1;34].

Example for physical pad location IOB02D01P:

location => “IOB2:IOD3.OD“

 

dff_load

type bit

default value ‘0’

This generic represents whether the DFF considers the L (load) input. ‘1’ is for ignore and ‘0’ for using connected net.

It is inverted compared with NX_DFF

 

dff_sync

type bit

default value ‘0’

This generic represents whether the DFF reset is synchronous or asynchronous. ‘0’ is for asynchronous and ‘1’ for synchronous.

 

dff_type

type bit

default value 0

This generic represents whether the reset must initialize the DFF to 0 or 1. dff_type is set to ‘0’ for reset initializing the DFF to 0, dff_type is set to ‘1’ for reset initializing the DFF to 1. dff_type can also be set to 2 to configure set/reset on signal.

 

Ports

Ports

Direction

Type

Description

I1

input

std_logic

Input double data rate caught on rising edge

I2

input

std_logic

Input double data rate caught on falling edge

CK

input

std_logic

Clock

L

input

std_logic

Load

R

input

std_logic

Reset, active high

O1

output

std_logic

Output double data rate

 

Example

This documentation only provides the instantiation of the component.

 

 

Reserved

There are some other components defined in NX library that are reserved for post synthesis and post place & route simulation. These components cannot be instantiated in pre synthesis VHDL.

 

The reserved components are:

  • NX_BUFFER

  • NX_CSC

  • NX_SCC

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