Application Note : NG-ULTRA Reset Management
- Kévin Chopier
- Fabrice NSONGO
- sylvain depierre
- 1 Introduction
- 2 Reset description
- 2.1 Overview
- 2.2 Soc Reset
- 2.2.1 Overview
- 2.2.2 Reset list
- 2.2.2.1 Power On Reset
- 2.2.2.2 System Reset
- 2.2.2.3 Post Mortem Reset
- 2.2.2.4 Warm Reset
- 2.2.2.5 Core Reset
- 2.2.2.6 DDR Controller Reset
- 2.2.2.7 Peripheral Reset
- 2.2.3 External pin
- 2.2.4 Internal Register
- 2.2.4.1 System Reset Mode Register (SRMR)
- 2.2.4.2 Core Reset Mode Register (CRMR)
- 2.2.4.3 Core Reset StatusRegister (CRSR)
- 2.2.5 SoC/Fabric interface
- 2.3 FPGA Reset
- 2.3.1 Reset list
- 2.3.1.1 Hard Reset
- 2.3.1.2 Soft Reset
- 2.3.2 Sequence
- 2.3.3 External pin
- 2.3.4 Internal Register
- 2.3.4.1 BSM RESETS
- 2.3.4.2 LOADERS STATUS
- 2.3.4.3 LOADERS FLAGS
- 2.3.5 SoC/Fabric interface
- 2.3.1 Reset list
- 3 Summary
Introduction
This document is aimed to help NG-ULTRA users to manage all resets in their designs.
Some of the reset are dedicated to the SoC part and others are dedicated to the FPGA part.
Reset description
Overview
Hereafter an overview of the whole reset system of NG-ULTRA:
Soc Reset
Overview
Hereafter the overview of all reset
Reset list
The Soc get multiple reset signals and modes affecting the cores, some interfaces or the whole Soc.
CLK pin must be still activated during any reset assertion
Power On Reset
It resets everything in the Soc including the clock manager
After releasing, the SoC restarts with the BL0 running.
The possible sources to generate this signal are:
Name | Type | Comment |
|---|---|---|
POWER_ON_RSTN | External pin |
|
POR | Internal register | SRMR² |
System Reset
It reset everything, as the Power On Reset except the clock manager.
As Power On Reset, the SoC restarts with the BL0 running once the reset is released.
Name | Type | Comment |
|---|---|---|
SYSTEM_RSTN | External pin | POST_MORTEM='0' |
SYSRST | Internal register | SRMR |
fabric_fpga_sysrstn | Internal signal | SoC/Fabric interface |
Post Mortem Reset
It gets the same impact than System Reset except the core restart mode can be modified.
CRMR and PMRSTHALT in SRMR are not reseted.
Name | Type | Comment |
|---|---|---|
SYSTEM_RSTN | External pin | POST_MORTEM='1' |
PMRST | Internal register | SRMR |
fabric_fpga_pmrstn | Internal signal | SoC/Fabric interface |
Warm Reset
Individual logic reset for each ARM Core.
Behavior after this reset is set by Core Reset Mode Register of each core.
In order to generate a Warm Reset request (Warmrstreq), RR bit in R52 HRMR control register of the associated core must be written.
Then, the following sequence must be done:
Assert warmrstreq and de-assert corepactive.
Wait for the assertion of Corepreqn and Corepstate.
When both Corepreqn and Corepstate are high, assert Corepaccept.
In order to abort the procedure, assert corepdeny instead of Corepaccept.
new warm reset procedure can be accepted by clock manager if previous warm reset has been released and both corepaccept and corepdeny are at low level.
Core Reset
Each R52 core is composed by the following resets:
nCORERESET[3:0]: individual core warm reset (except debug & trace logic)
nCPUPORESET[3:0]: individual core power-on reset (including core’s debug & trace logic)
nTOPRESET: cluster top-level logic reset (GIC, AXIS)
nPRESETDBG: APB and top level debug logic
In addition, CPUHALT[3:0] controls if the core waits out of reset before fetching instructions (1) or not (0).
DDR Controller Reset
DDR Controller reset
Peripheral Reset
There is one reset for all the following peripheral interface:
AXI Master 1 & 2
AXI Slave 1 & 2
LLPP 0 to 3
DDR
DMA Handshake
External pin
Hereafter the list of all resets coming from primary pin and connected to the SoC:
POWER_ON_RSTN: generates a Power On Reset
SYSTEM_RSTN: generates a System Reset or Post Mortem Reset depending on POST_MORTEM level
POST_MORTEM: Mode to indicate if SYSTEM_RSTN acts as a System Reset (0) or a Post-Mortem Reset (1)
Internal Register
System Reset Mode Register (SRMR)
SRMR register is a register in CLKRST_MNG range.
The address of SRMR register is 0x0D716040.
Only CORE 0 and external debugger can write into this register.
Bits | Bit Name | POR , SYSRST or PMRST Value | Description |
31:16 | Key | n.a. | Register write enable key: 0xCDEF. Read as 0 |
15:5 | Reserved | n.a. | Unused, Read as 0 |
4 | DDRCCRST | 1 | DDR Controller Core Reset:
1= DDRC Core reset 0= DDRC Core enabled |
3 | PMRSTHALT | 0 (not cleared by PMRST) | Select if all the cores are held in HALT after a PMRST 0 = each core behaves as dictated by its Core Reset Mode Register values 1 = all cores held in HALT after the next PMRST until cleared |
2 | PMRST | n.a. | Post Mortem Reset: writing 1 generates a SoC PMRST, 0 = no effect. Read as 0 |
1 | SYSRST | n.a. | System Reset: writing 1 generates a SoC SYSRST, 0 = no effect. Read as 0 |
0 | POR | n.a. | Power On Reset: writing 1 generates a SoC POR, 0 = no effect. Read as 0. |
Core Reset Mode Register (CRMR)
SRMR[3:0] registers are registers in CLKRST_MNG range.
The addresses of CRMR registers are:
Core | Address |
|---|---|
0 | 0x0D716044 |
1 | 0x0D716048 |
2 | 0x0D71604C |
3 | 0x0D716050 |
Bits | Bit Name | POR or SYSRST Value | Description |
31:5 | VECTABLE | 0 | Reset Vector base address |
4:2 | Reserved | n.a. | Unused. Read as 0. |
1 | TCMBOOT | 0 (core0) 1 (core1..3) | Enable TCMA at address 0 after reset 1 = enabled 0 = disabled |
0 | CPUHALT | 0 or 1 (core0) 1 (core1..3) | Core held in HALT after reset 1 = held in HALT 0 = free to run |
Core Reset StatusRegister (CRSR)
CRSR[3:0] registers are registers in CLKRST_MNG range.
It gives the ability to check the last reset source.
The addresses of CRSR registers are:
Core | Address |
|---|---|
0 | 0x0D716070 |
1 | 0x0D716074 |
2 | 0x0D716078 |
3 | 0x0D71607C |
Only CORE 0 and external debugger can write into these registers.
Bits | Bit Name | POR or SYSRST Value | Description |
31:5 | Reserved | n.a. | Unused. Read as 0. |
4:2 | LRSRC | X | Last Reset Source:
0 = Input Pin 1 = SRMR.POR 3 = SRMR.SYSRST 4 = SRMR.PMRST 5 = HRMR.RR 6 = FPGA |
1:0 | LRTYPE | X | Last Reset Type:
0 = POR 1 = SYSRST 2 = PMRST 3 = WARMRST |
SoC/Fabric interface
Hereafter the list of all resets coming from the SoC/Fabric interface with signals generated by the fabric:
fabric_fpga_sysrstn: generates a System Reset if SoC/Fabric interface is enabled (depends on enable_TMR)
fabric_fpga_pmrstn: generates a Post Mortem Reset if SoC/Fabric interface is enabled (depends on enable_TMR)
enable_TMR: enables the SoC/Fabric interfaces if equal to 0b111
fabric_fpga_nic_rstn_i[9:0]: Reset of AXI interfaces with the following mapping:
9: DDR 0
8: LLPP 3
7: LLPP 2
6: LLPP 1
5: LLPP 0
4: APB
3: AXI Slave 1
2: AXI Slave 0
1: AXI Master 1
0: AXI Master 1
fabric_fpga_dma_hs_rstn_i[5:0]: Reset of DMA handshake
These resets affect the Soc only if the SoC/Fabric interface is enabled (enable_TMR[2:0] set to 0b111 by the fabric.
FPGA Reset
Reset list
The FPGA get multiple reset signals affecting the FPGA manager or the Fabric.
CLK pin must be still activated during any reset assertion
Hard Reset
It resets the FPGA manager: the error registers and the configuration registers of each FPGA loader.
Hereafter the list of all error registers:
ERROR1 (0x0E)
ERROR1_MASK (0x0F)
TRIGGER1_MASK (0x24)
ERROR2 (0x10)
ERROR2_MASK (0x11)
TRIGGER2_MASK (0x25)
ERROR3 (0x22)
ERROR3_MASK (0x23)
TRIGGER3_MASK (0x26)
EVENT_CNT1 (0x12)
EVENT_CNT2 (0x13)
EVENT_CNT3 (0x34)
MAX_ERROR_CNT (0x14)
Hereafter the list of all configuration registers:
INIT (0x02)
JTAG_USERCODE (0x0C)
SPI_CTRL (0x0D)
DEVICE_ID (0x15)
CMIC_DELAY (0x17)
THSENS_CTRL (0x1A)
DUMP_CTRL (0x1C)
SPW_CTRL1 (0x1D)
SPW_CTRL2 (0x1E)
PARUSR_CTRL (0x28)
PAREXT_CTRL (0x29)
SPI_TIMING (0x2A)
SPI_ADDR (0x2B)
It resets the ERROR output pin.
It resets the configuration memory.
After releasing, the bitstream must be reloaded.
Soft Reset
It resets the FPGA manager: the configuration registers of each FPGA loader.
For the configuration registers, check Hard Reset description.
It resets the TRIGGER output pin.
Soft Reset does not reset error registers.
Sequence
The FPGA reset must comply with the following requirements:
Assert SOFT_RSTN
Wait for a minimum of 100 cycles of CLK
Assert HARD_RSTN
Wait for a minimum of 3 us
Deassert SOFT_RSTN and HARD_RSTN
Deassertion of SOFT_RSTN and HARD_RSTN can be done in any order.
CLK pin must be running during the whole sequence.
For instance, the sequence can be the following one:
External pin
Hereafter the list of all resets coming from primary pin and connected to the FPGA:
HARD_RSTN: It generates a Hard Reset.
SOFT_RSTN: It generates a Soft Reset.
Internal Register
BSM RESETS
SRMR register is a register in FPGA_LOADER range.
The address of BSM RESETS register is 0x000D701030.
Bits | Bit Name | Description |
31:16 | Hard Reset | Must be equal to 0xB007 to be enabled Any other value leads to disabling Generates a Hard Reset |
15:0 | Soft Reset | Must be equal to 0x50F7 to be enabled Any other value leads to disabling Generates a Soft reset Reset of AHB registers Reset of AHB/PAR16 interface |
LOADERS STATUS
LOADER STATUS register is a register in FPGA_LOADER range.
The address of LOADER STATUS register is0x000D701038.
This register is useful in order to get a global status of the FPGA.
Bits | Bit Name | Description |
31:3 | Reserved | Unused |
2 | Ready | OR-reduced of ready status of all loaders |
1 | Error | OR-reduced of error status of all loaders |
0 | Trigger | OR-reduced of trigger status of all loaders |
LOADERS FLAGS
LOADERS FLAGS register is a register in FPGA_LOADER range.
The address of LOADERS FLAGS register is 0x000D70103C.
This register is useful in order to get a global status of the FPGA.
Bits | Bit Name | Description |
31:4 | Reserved | Unused |
23:0 | Error Status | 1 error status bit per loader |
SoC/Fabric interface
fabric_rstn_fpga (fabric_lowskew_o[1]) is a logic reset for the fabric in order to indicate the SoC is enabled.
This reset is activated in case of any of the following reset is activated whatever the source (SoC/Fabric interface, external pin, internal register, …):
Power On Reset
System Reset
Post Mortem Reset
Summary
Hereafter the summary table:
Reset | Active level | Type | Functionnal/Debug | SoC/FPGA Reset | Configuration Memory Reset | Comment |
POWER_ON_RSTN | Low | External pin | Functionnal | Soc | No | Reset the SoC including the clock manager |
SYSTEM_RSTN | Low | External pin | Functionnal | Soc | No | Reset the SoC |
POST_MORTEM | High (Mode) | External pin | Debug | Soc | No | 0: Post-Mortem reset will be applied in case of SYSTEM_RSTN low level |
RST_HARD_N | Low | External pin | Functionnal | FPGA | Yes | Reset of error registers and the configuration memory |
RST_SOFT_N | Low | External pin | Functionnal | FPGA | No | Reset of configuration registers and trigger output |
POR | High | Internal register | Functionnal | Soc | No | Enabled when AHB Register address 0x0D716040 data bit 0 is 0b1 |
SYSRST | High | Internal register | Functionnal | Soc | No | Enabled when AHB Register address 0x0D716040 data bit 1 is 0b1 |
PMRST | High | Internal register | Debug | Soc | No | Enabled when AHB Register address 0x0D716040 data bit 2 is 0b1 |
PMRSTHALT | High | Internal register | Debug | Soc | No | Enabled when AHB Register address 0x0D716040 data bit 3 is 0b1 |
DDRCCRST | High | Internal register | Functionnal | Soc | No | Enabled when AHB Register address 0x0D716040 data bit 4 is 0b1 |
AHB Hard Reset | Low | Internal register | Functionnal | FPGA | No | Enabled when AHB Register address 0x000D701030 is data 0x50F7 |
AHB Soft Reset | Low | Internal register | Functionnal | FPGA | No | Enabled when AHB Register address 0x000D701030 is data 0xB007 |
Warmresetreq[3:0] | High | Internal register | Functionnal | Soc | No | Logic reset of Core processors |
fabric_fpga_sysrstn | Low | Internal signal | Functionnal | Soc | No | Impact only if NX_SOC_INTERFACE input enable_TMR[2:0]==0b111 |
fabric_fpga_pmrstn | Low | Internal signal | Debug | Soc | No | Impact only if NX_SOC_INTERFACE input enable_TMR[2:0]==0b111 |
fabric_fpga_nic_rstn_i[9:0] | Low | Internal signal | Functionnal | Soc | No | Reset of AXI interfaces |
fabric_fpga_dma_hs_rstn_i[5:0] | Low | Internal signal | Functionnal | Soc | No | Reset of DMA handshake |
fabric_rstn_fpga | Low | Internal signal | Functionnal | FPGA | No | Logic reset |
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