Important information

This document applies exclusively to the configuration of the NG-LARGE FPGA referenced NX1H140TSP.

For other NanoXplore chips, please refer to the associated documentation.

Introduction to NG-LARGE Configuration

NX1H140TSP is configured by loading the bitstream into internal configuration memory using one of these following modes:

• JTAG,

• Slave Parallel 8 bits,

• Slave Parallel 16 bits,

• Slave SpaceWire, compliant ECSS-E-ST-50-12C link,

• Master SPI, compliant with SPI JESD68.01

WARNING: changing MODE value while RST_HARD_N is unasserted is strictly forbidden.

Bitstream size

This NX1H140TSP bitstream size depends on the amount of logic resources used by the application, the number of initialized Flip-flops and the number of user Core RAM and Core Register Files to be initialized.

1. In a typical design the user can give – or not - an initial value to Flip-Flops at power-up. Reducing the number of initialized Flip-Flops contributes to reduce the bitstream size.

2. Core RAM and/or Core Register file can also be initialized – or not - at power-up. Reducing the number of initialized memories contributes to reduce the bitstream size.

Most applications do not require to initialize all memories.

These numbers are just estimations.

The actual size can be determined only by running the mapping software.

Configuration Memory Integrity Check (CMIC)

The CMIC is an embedded engine performing automatic verification and repair of the configuration memory.

A CMIC reference memory is initialized during the bitstream download process with reference data computed by the NanoXmap software.

Once the initialization is done, the CMIC engine can be periodically activated to perform the following sequence:

1. Read configuration data

2. Calculate signature

3. Compare the signature with CMIC reference

4. If a mismatch is detected:

a. Calculate faulty address (BAD @) and faulty bit location

b. Read DATA[BAD @]

c. Repair flipped bit

d. Write DATA[BAD @]

In case of error that cannot be corrected, for instance double error, the data is blacklisted in order to not generate definitive TRIGGER/ERROR high level.

For further information, please refer to the NX1H140TSP CMIC Application note.

Device configuration details

Purpose of NX1H140TSP configuration

NX1H140TSP chips are SRAM-based FPGAs. To achieve user-defined functionality their configuration bitstream must be downloaded first.

NX1H140TSP chips configuration modes summary

NX1H140TSP chips are always accessible through JTAG, and also support several configuration modes.

At power-up, MODE [2:0] pins state defines the configuration mode.

RST_HARD_N is a dedicated input pin that allows to reset the configuration engine, and launches the configuration process after RST_HARD_N is released. (It can’t be used to reset the FPGA user’s logic).

Multiple devices addressing

Thanks to Device ID feature in the Bitstream Manager, it is possible to connect multiple devices on the same bus and load a bitstream only to the desired device.

In broadcast mode (0xFF), all connected devices will load the bitstream in the configuration memory.

Open

Multiple Device ID

Bitstream Device ID is set during bitstream generation. It is 8 bits large.

Chip Device ID is set by external pins. It is only 4 bits large.

Configuration modes usage

JTAG configuration channel is always active regardless the selected configuration mode. JTAG accesses while the configuration interface is active are not recommended (risk of conflict with the bitstream manager operation and render ineffective the bitstream manager)

In slave modes (SpaceWire, Slave Parallel 8 or Slave Parallel 16), NX1H140TSP chip must be fed its bitstream through the selected interface.

In Master Serial SPI modes, NX1H140TSP chip automatically fetches its bitstream from the external memory (SPI or SPI with Vcc control) after RST_HARD_N is released.

Prog bank pins state during and after configuration

According the selected configuration mode, each of the prog is “multi-usage”. Some of the active pins must be required for correct configuration, and some other pins must be left unconnected. In addition, some prog bank pins can be configured as additional user’s I/O, providing that the supported I/O standard is:

• LVDS with external impedance adaptation for the dedicated SpaceWire pins.

• LVCMOS_3.3V for the other prog pins (with 60 mA output drive for the outputs, and 10K to 40K default Pull-Up)

The prog bank pins that are not used or activated by the selected configuration mode are configured as High-Z during the configuration. After the configuration they stay configured as High-Z if not used, or take the user’s defined functionality.

JTAG input pins (TRST, TMS, TDI) get internal default Pull-Up (10K to 40K).

User’s I/O pins state during and after configuration

Before reset, I/Os state are undetermined.

During the configuration process, all user’s I/Os are configured as High-Z with an internal 10K to 40K default Pull-Up.

After configuration the user I/O pins behaves as defined by the bitstream.

Internal default Pull-Up is set on single ended inputs.

NX1H140TSP chips prog interface pin list

The user must provide the 3-bit MODE value to select the configuration mode. In addition, the internal configuration engine requires an external reset signal (RST_HARD_N). RST_HARD_N must be asserted (low) during at least 3 microseconds. When RST_HARD_N is de-asserted, the configuration process starts after up to 3 us delay, according the MODE bits settings.

WARNING: changing MODE value while RST_HARD_N is unasserted is strictly forbidden (undefined behavior).

Depending on the selected configuration MODE, some prog bank pins are activated during the process. Some other remain as inputs with internal Pull-Up during the configuration process.

In addition, some prog bank pins can be used as auxiliary user defined I/Os after completing the configuration.

The next table summarizes the list of pins that can be affected during the configuration process.

Detailed configuration modes

SPI Modes

On board SPI flash memory programming:

For Master Serial modes, the on-board flash memory programming operation requires changing the MODE[2:0] into Slave mode to ensure the accessibility to the flash.

The NX1H140TSP chip may then be configured through JTAG with a dedicated design to program the memory with the user data, also transmitted by JTAG. NxBase2 provides such design and commands to program a given list of SPI flash memories. Please refer to NanoXplore_NxBase2_User_Manual.

Endianness

The bitstream must be sent by 32bits words with less significant byte first. Each byte must be sent with most significant bit first.

As an example, 0x12345678 is the first word of each bitstream. It must be sent as follows:

Open

Figure: Master Serial SPI endianness

Bistream manager clock

In Master SPI or in Master SPI + Vcc control, only an external clock can be used to connect to CLK IO.

Do not loop CLK_OSC to CLK in these modes.

Master Serial SPI configuration details:

The next figure shows a suggestion of schematic to implement the Master Serial SPI configuration, then the pin list table describes the behavior of the prog bank pins when this mode is selected.

Master Serial SPI Mode

Prog bank (INTERFACE) pins used and/or impacted by configuration

Master Serial SPI with Vcc control configuration details:

The next figure shows a suggestion of schematic to implement the Master Serial SPI with VCC control configuration, then the pin list table describes the behavior of the prog bank pins when this mode is selected.

This configuration mode is the same as Master Slave SPI, with the only difference that the SPI Flash memory is powered by using 3 pins of the NG-LARGE prog bank to supply the external SPI. This can contribute to reduce the risk of corruption of bitstream/data stored into the external SPI memory device.

Master Serial SPI Mode with VCC control

Prog bank (INTERFACE) pins used and/or impacted by configuration

Slave SpaceWire configuration details:

The next figure shows a suggestion of schematic to implement the Slave SpaceWire configuration, then the pin list table describes the behavior of the prog bank pins when this mode is selected.

Slave SpaceWire

Prog bank (INTERFACE) pins used and/or impacted by configuration

Strobe and Data input signals must comply with the following figure focusing on input capacitors and resistors:

Capacitors are needed in case of signals come from another board not connected to the same ground.

Resistors are needed to center the signal around VDDIO_SPW/2.

Spacewire configuration instructions

The supported SPW instructions by the NG-LARGE FPGA are as stated in the table below.

ADDR_DEBUG instruction

The ADDR_DEBUG instruction is used to set the address of the loader register which will be accessed in all subsequent instructions. Following figure illustrates the format of the packet. Note that if many reads and writes will be performed to the same register only one ADDR_DEBUG instruction is needed.

READ_DEBUG instruction

The READ_DEBUG instruction is used to read the loader register value from the address defined by the previous ADDR_DEBUG instruction. READ_DEBUG instruction is a 1-byte packet containing only the instruction code (0x02) as shown in 5 below. The FPGA responds with a 4-bytes packet containing the read value which is sent LSB first as shown in 6.

WRITE_DEBUG instruction

The WRITE_DEBUG instruction is used to write a value to the address of the loader register defined by the previous ADDR_DEBUG instruction. WRITE_DEBUG instruction contains the instructions code (0x04) followed by 4-bytes data to be written. Data is sent LSB first as shown in the following figure:

WRITE_CONF instruction

The WRITE_CONF instruction is used to program the NG-LARGE FPGA.

The SPW packet size depends on bitstream size and it has the following fields:

• Instruction code: 0x08 for WRITE_CONF

• FPGA bitstream: the bitstream to be programmed into the FPGA.

This field is obtained by converting each 32bits bitstream word to 4 bytes sent LSB first as illustrated in the figure below:

Slave parallel configuration details:

The next figure shows a suggestion of schematic to implement the Slave Parallel 8 configuration, then the pin list table describes the behavior of the prog bank pins when this mode is selected.

.

Slave Parallel 8 – Slave Parallel 16

Prog bank (INTERFACE) pins used and/or impacted by configuration

Slave Parallel interface usage

In Slave Parallel 8 and Slave Parallel 16 modes, the configuration clock must be provided to the FPGA on the dedicated CLK input pin. Its frequency can range in [0MHz;100MHz], in any case it must be strictly greater than twice the JTAG (TCK) frequency – if used.

In order to avoid setup/hold time problems, the master can use the falling CLK edge to generate CS, TYPE[1:0] and D(7:0) or D(15:0).

The master can start downloading the bitstream bytes after 50 configuration clock (CLK) cycles.

Each data access is done on the rising edge of CLK, while CS is activated (high level) and TYPE[1:0] informing type of access. Dummy cycles can be inserted – if required by the master by de-asserting CS during one or more cycles between two data. The next figure illustrates an example of timing diagram.

Data are 32 bits long and are sent in the following order:

• In Slave Parallel 16 mode, DATA[15:0] and then DATA[31:16].

• In Slave Parallel 8 mode, DATA[7:0], then DATA[16:8], then DATA[23:16] and then DATA[31:24].

Internal interface between fabric and BSM

I/O direction is given for fabric side.

Global signals

The following signals can be used by the fabric and consequently get an impact in the design if needed by users:

Slave Parallel 8 interface

There is an internal interface between the Bitstream Manager and the fabric. It operates as slave parallel 8 interface.

The difference is Bitstream Manager registers write/read accesses are made from the fabric and give the ability to use these control and status registers in the design.

Boundary scan

IEEE 1149 JTAG implementation

NX1H140TSP devices support IEEE Std 1149.1 JTAG boundary scan operation for board and device testing.

The EXTEST, INTEST, SAMPLE, BYPASS, IDCODE, USERCODE, and HIGHZ instructions are all included. The tap also supports internal user-defined registers (USER1, USER2) and instructions for device configuration and test.

JTAG interface pins include the standard TCK, TMS, TDI and TDO pads, as well as the optional TRST pad.

NX1H140TSP chips JTAG instructions

NX1H140TSP chips boundary scan instructions are the following:

NX1H140TSP devices provide a 1046-bit scan chain, described in each device BSDL file.

The WRITE_CONF instruction is used to program the NG-LARGE FPGA.

The ADDR_DEBUG instruction is used to set the address of the loader register which will be accessed in all subsequent instructions.

The READ_DEBUG instruction is used to read the loader register value from the address defined by the previous ADDR_DEBUG instruction.

The WRITE_DEBUG instruction is used to write a value to the address of the loader register defined by the previous ADDR_DEBUG instruction.

The IDCODE instruction returns the NG-LARGE Identification’s code: 0x675.

The USRCODE instruction returns the user-defined code (0xFFFFFFFF by default).

The USER1 instruction is used to access to the user1 registers from the FPGA fabric.

The USER2 instruction is used to access to the user2 registers from the FPGA fabric.

The HIGHZ instruction is used to deactivate the outputs of all pins.

The BYPASS instruction is used to bypass the device.

Endianness

The JTAG commands must be sent by 32bits words with less significant bit first.

Hereafter an example of bitstream loading using WR_CONF command. The first word 0x12345678 is sent with the following sequence “0001 1110 0110 … 0100 1000”

In order to write or read a Bitstream Manager register, it needs a ADDR_DEBUG command followed by respectively a WR_DEBUG or RD_DEBUG command. The address is 32 bits long and data are 96 bits long.

NX1H140TSP boundary scan usage

NX1H140TSP chips are fully programmable devices, so boundary scan instructions usage requires some minimal device configuration using a limited bitstream, especially for the EXTEST instruction:

- pads to be used as outputs need a minimum output drive configuration.

- pads to be used as inputs need a minimum input thresholds configuration.

NX1H140TSP boundary scan errata

NX1H140TSP chips boundary-scan architecture presents some implementation bugs, listed below:

Chip initialization with unused JTAG interface

Problem:

Workaround:

Dedicated clock inputs in boundary scan INTEST

Problem:

ANGIE JTAG adaptator

In order to debug a component, it can be very useful to use ANGIE adaptor and NxBase2 software.

An EEPROM is recommended in order to work in non-OEM mode. In this way, the board will be automatically recognized by the software.

Please refer to https://nanoxplore-wiki.atlassian.net/wiki/spaces/NAN/pages/53215245 documentation in ANGIE chapter.

NG_LARGE registers

To access a register, the user needs to use the ADDR_DEBUG instruction first, and then the WR_DEBUG or RD_DEBUG instructions.

NG-LARGE is divided in 9 rows with the following set of registers for each row. When addressing a register, address is 32 bits long with the following mapping:

When generating a bitstream, default values are sent for all registers but it is possible to change these values inside the bitstream. Refer to initRegister NXmap method.

Note all NG-MEDIUM registers are kept in NG-LARGE and get the same addresses.

STATUS

JTAG_IDCODE

JTAG_USERCODE

SPI_CTRL

ERROR1

ERROR1_MASK

ERROR2

ERROR2_MASK

EVENT_CNT1

EVENT_CNT2