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List of figures
Figure 2: Architecture of CortexR5
Figure 3: Architecture of ETMr5
Figure 4: Architecture of TPIU-Lite
Figure 5: Architecture of DAP-Lite
Figure 6: Cortex R5 AMBA Interface Clocking
Figure 7: AXI and APB interface clockingTable 1:
List of tables
Introduction
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The Figure 1 previous figure shows the ecosystem of the Cortex R5 implemented in NG-LARGE. It includes the Cortex R5 processor, the debug facility, the Bus Matrix and all users IPs. The bus matrix and users IPs (memory, IO controller, coprocessor, …) are implemented in the fabric (part “Fabric User” on the Figure 1).
The Trace Ram and JTAG/Serial Wire controllers are also implemented in the fabric (part “Fabric Debug” on the Figure 2following figure).
The architecture of the Cortex R5 is shown Figure 3 Architecture of ETMr5. The section 2.2 CortexR5 Configuration describes the Cortex R5 configuration.
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The architecture of the CoreSight TPIU Lite is displayed on the Figure 4 Architecture of TPIU-Lite. The APB Slave is connected with the APB Debug Bus and the Trace Interface is connected with the Fabric.
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The architecture of the CoreSight DAP-Lite is displayed on the Figure 5 Architecture of DAP-Lite. The APB System Slave is connected with the Fabric. The APB Debug Master is connected with the CoreSight TPIU and the CortexR5. The Serial Wire / JTAG (SWJ) interface is connected with the fabric. Both JTAG pins and serial interfaces are available via fabric for debugging purpose.
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For the debug sequence please refer to Cortex-R5_TechnicalReferenceManual - Chapter 12 (internal registers) and CoreSight TPIU-Lite Technical Reference ManuaManual.
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1 : 0x00003000 (TPIULite) (32b format)
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Feature | Options | Sub-Options |
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Number of CPUs | Single-CPU (No redundancy) | - |
Instruction cache | I-Cache included | 32KB (4x8KB ways) (64-bit ECC error checking) |
ATCM | One ATCM port | 64KB (32-bit ECC error checking) |
BTCM | No BTCM ports (No sufficient area) | - |
Instruction endianness | Pin-configured | Little-endian of Big-endian |
Floating point | FPU included | - |
MPU | MPU included | - |
TCM bus parity | No TCM address and control bus parity | - |
AXI bus ECC/parity on AXImaster, AXI-slave and ACP | No AXI bus ECC/parity | - |
Bus ECC/parity on AXI peripheral port and AHB peripheral port | No peripheral port bus ECC/parity | - |
Breakpoints | 2-8 breakpoint register pairs | 8 breakpoints |
Watchpoints | 1-8 watchpoint registers | 8 watchpoints |
ATCM as reset | Disabled | - |
BTCM as reset | Disabled | - |
Axi slave interface | Enabled | - |
TCM hard error cache | TCM hard error cache | - |
Non-Maskable FIQ Interrupt | Disabled | - |
Axi coherency port (ACP) | No ACP | - |
AHB peripheral port | AXI peripheral only | - |
Custom Power mode | none | - |
Table 1: General Configuration
Macrocell interface
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Each interface has a Clock Enable port. This input port must be asserted on every CLKIN rising edge for which there is a simultaneous rising edge on the FABIC clock. The Table 2 following table lists all clock enable port of each interface.
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Clock Enable Port | Interface | Connection |
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ACLKENMm | AXI Master Port | Core |
ACLKENSm | AXI Slave Port | Core |
ACLKENPm | AXI Peripheral Port | Core |
PCLKENDBG | APB Debug Port | Core, ETM, DAP, TPIU |
PCLKENSYS | APB System Port | DAP |
ATCLKEN | ATB Port | TPIU |
Table 2: Clock Enable Port
The Figure 6 following figure shows the AMBA interface clocking. All Cortex R5 clocks and clock enable are generated by the CLKGEN system and distributed through the FABRIC clock network.
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Figure 7 The following figure shows an example in which the processor is clocked at 200MHz (CLKIN) while the FABRIC system connected to the AXI master port, AXI Peripheral port and APB debug port are respectively clocked at 100MHz (AXI_MASTER_CLK), 100MHz (AXI_PERIHERAL_CLK) and 50MHz (APB_DEBUG_CLK). It should be noted that the AXI bus, implemented in FABRIC, cannot be faster than the processor clock.
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Resets
The Table 3 following table lists all reset port of the CortexR5.
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Reset Port | Descriptions |
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nRESETm | Main CPU reset Resets the non-debug CPU logic |
nSYSPORESET | Power On Reset Resets the entire processor group including debug CPU logic |
PRESETDBGm | CPU debug reset Resets the debug domain logic and the APB interface of the CPU |
Table 3: CortexR5 Reset Ports
DBGReset is implemented and connected to PRESETSYSn.
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