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NG-LARGE Cortex R5

NG-LARGE Cortex R5

List of figures

CortexR5 Overview

Architecture of CortexR5

Architecture of ETMr5

Architecture of TPIU-Lite

Architecture of DAP-Lite

Cortex R5 AMBA Interface Clocking

AXI and APB interface clocking

List of tables

General Configuration

Clock Enable Port

CortexR5 Reset Ports

Introduction

List of Acronyms ans Abreviations

ADD

Addition

ADD

Addition

FPGA

FPGA Field Programmable Gate Array

LUT

Look-Up Table

LVDS

Low Voltage Differential Signal

PLL

Phase Lock Loop

RAM

Random Access Memory

TBD

To Be Define

Macrocell Description

The macro cell nx_cortex_r5 contains:

• Cortex R5 CPU (r1p3-00rel0)

• CoreSight ETM R5

• CoreSight TPIU-Lite

• CoreSight DAP-Lite

Macrocell interface is the interface with the FPGA fabric.

 

Block Diagram

CortexR5 Overview

The previous figure shows the ecosystem of the Cortex R5 implemented in NG-LARGE. It includes the Cortex R5 processor, the debug facility, the Bus Matrix and all users IPs. The bus matrix and users IPs (memory, IO controller, coprocessor, …) are implemented in the fabric (part “Fabric User” on the Figure 1).

The Trace Ram and JTAG/Serial Wire controllers are also implemented in the fabric (part “Fabric Debug” on the following figure).

The architecture of the Cortex R5 is shown Figure Architecture of ETMr5. The section CortexR5 Configuration describes the Cortex R5 configuration.

This implementation of the Cortex R5 does not include the ACP (uSCU), B0TCM, B1TCM, PAHB interface.

The ATB interface is connected with the CoreSight TPIU Lite module and the APB Slave is connected with the APB Debug Bus.

The architecture of the CoreSight TPIU Lite is displayed on the Figure Architecture of TPIU-Lite. The APB Slave is connected with the APB Debug Bus and the Trace Interface is connected with the Fabric.

The Trace memory is implemented using a DPRAM included on the Fabric CGB.

The architecture of the CoreSight DAP-Lite is displayed on the Figure Architecture of DAP-Lite. The APB System Slave is connected with the Fabric. The APB Debug Master is connected with the CoreSight TPIU and the CortexR5. The Serial Wire / JTAG (SWJ) interface is connected with the fabric. Both JTAG pins and serial interfaces are available via fabric for debugging purpose.

After a reset, the SWJ is configured in JTAG Mode. A 16-bit sequence on SWIOTMS switch the Mode (Serial Wire or JTAG).

For the debug sequence please refer to Cortex-R5_TechnicalReferenceManual - Chapter 12 (internal registers) and CoreSight TPIU-Lite Technical Reference Manual.

Architecture of CortexR5

Architecture of ETMr5

Architecture of TPIU-Lite

 

Architecture of DAP-Lite*

*: Content of DAP rom:

0 : 0x00080000 (CORTEXR5ROM) (32b format)

1 : 0x00003000 (TPIULite) (32b format)

CortexR5 Configuration

Feature

Options

Sub-Options

Feature

Options

Sub-Options

Number of CPUs

Single-CPU (No redundancy)

-

Instruction cache

I-Cache included

32KB (4x8KB ways) (64-bit ECC error checking)

ATCM

One ATCM port

64KB (32-bit ECC error checking)

BTCM

No BTCM ports (No sufficient area)

-

Instruction endianness

Pin-configured

Little-endian of Big-endian

Floating point

FPU included

-

MPU

MPU included

-

TCM bus parity

No TCM address and control bus parity

-

AXI bus ECC/parity on AXImaster, AXI-slave and ACP

No AXI bus ECC/parity

-

Bus ECC/parity on AXI peripheral port and AHB peripheral port

No peripheral port bus ECC/parity

-

Breakpoints

2-8 breakpoint register pairs

8 breakpoints

Watchpoints

1-8 watchpoint registers

8 watchpoints

ATCM as reset

Disabled

-

BTCM as reset

Disabled

-

Axi slave interface

Enabled

-

TCM hard error cache

TCM hard error cache

-

Non-Maskable FIQ Interrupt

Disabled

-

Axi coherency port (ACP)

No ACP

-

AHB peripheral port

AXI peripheral only

-

Custom Power mode

none

-

General Configuration

Macrocell interface

Name

Direction

Width (bits)

Name

Direction

Width (bits)

Global

CLKIN

input

1

nRESET0

input

1

nSYSPORESET

input

1

nCPUHALT0

input

1

DBGNOCLKSTOP

input

1

nCLKSTOPPED0

output

1

nWFEPIPESTOPPED0

output

1

nWFIPIPESTOPPED0

output

1

EVENTI0

input

1

EVENTO0

output

1

Configuration

VINITHI0

input

1

CFGEE

input

1

CFGIE

input

1

INITRAMA0

input

1

LOCZRAMA0

input

1

TEINIT

input

1

CFGNMFI0

input

1

PARECCENRAM0 1

input

1

PARITYLEVEL 1

input

1

ERRENRAM0 1

input

1

GROUPID 4

input

4

INITPPX0 1

input

1

PPXBASE0 20

input

20

PPXSIZE0 5

input

5

PPVBASE0 20

input

20

PPVSIZE0 5

input

5

Interrupt

nFIQ0

input

1

nIRQ0

input

1

nPMUIRQ0

output

1

IRQACK0

output

1

IRQADDR0

input

30

IRQADDRV0

input

1

IRQADDRVSYNCEN

input

1

AXI3 Master

ACLKENM0

input

1

AWADDRM0

output

32

AWBURSTM0

output

2

AWCACHEM0

output

4

AWIDM0

output

4

AWLENM0

output

4

AWLOCKM0

output

2

AWPROTM0

output

3

AWREADYM0

input

1

AWSIZEM0

output

3

AWINNERM0

output

4

AWSHAREM0

output

1

AWVALIDM0

output

1

WDATAM0

output

64

WIDM0

output

4

WLASTM0

output

1

WREADYM0

input

1

WSTRBM0

output

8

WVALIDM0

output

1

BIDM0

input

4

BREADYM0

output

1

BRESPM0

input

2

BVALIDM0

input

1

ARADDRM0

output

32

ARBURSTM0

output

2

ARCACHEM0

output

4

ARIDM0

output

4

ARLENM0

output

4

ARLOCKM0

output

2

ARPROTM0

output

3

ARREADYM0

input

1

ARSIZEM0

output

3

ARINNERM0

output

4

ARSHAREM0

output

1

ARVALIDM0

output

1

RDATAM0

input

64

RIDM0

input

4

RLASTM0

input

1

RREADYM0

output

1

RRESPM0

input

2

RVALIDM0

input

1

AXI3 Slave

ACLKENS0

input

1

AWADDRS0

input

32

AWBURSTS0

input

2

AWCACHES0

input

4

AWIDS0

input

8

AWLENS0

input

4

AWLOCKS0

input

2

AWPROTS0

input

3

AWREADYS0

output

1

AWSIZES0

input

3

AWVALIDS0

input

1

WDATAS0

input

64

WIDS0

input

8

WLASTS0

input

1

WREADYS0

output

1

WSTRBS0

input

8

WVALIDS0

input

1

BIDS0

output

8

BREADYS0

input

1

BRESPS0

output

2

BVALIDS0

output

1

ARADDRS0

input

32

ARBURSTS0

input

2

ARCACHES0

input

4

ARIDS0

input

8

ARLENS0

input

4

ARLOCKS0

input

2

ARPROTS0

input

3

ARREADYS0

output

1

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