Figure 1: CortexR5 Overview

Figure 2: Architecture of CortexR5

Figure 3: Architecture of ETMr5

Figure 4: Architecture of TPIU-Lite

Figure 5: Architecture of DAP-Lite

Figure 6: Cortex R5 AMBA Interface Clocking

Figure 7: AXI and APB interface clocking

Table 1: General Configuration

Table 2: Clock Enable Port

Table 3: CortexR5 Reset Ports

Introduction

List of Acronyms ans Abreviations

Macrocell Description

The macro cell nx_cortex_r5 contains:

• Cortex R5 CPU (r1p3-00rel0)

• CoreSight ETM R5

• CoreSight TPIU-Lite

• CoreSight DAP-Lite

Macrocell interface is the interface with the FPGA fabric.

Block Diagram

The Figure 1 shows the ecosystem of the Cortex R5 implemented in NG-LARGE. It includes the Cortex R5 processor, the debug facility, the Bus Matrix and all users IPs. The bus matrix and users IPs (memory, IO controller, coprocessor, …) are implemented in the fabric (part “Fabric User” on the Figure 1).

The Trace Ram and JTAG/Serial Wire controllers are also implemented in the fabric (part “Fabric Debug” on the Figure 2).

The architecture of the Cortex R5 is shown Figure 3. The section 2.2 describes the Cortex R5 configuration.

This implementation of the Cortex R5 does not include the ACP (uSCU), B0TCM, B1TCM, PAHB interface.

The ATB interface is connected with the CoreSight TPIU Lite module and the APB Slave is connected with the APB Debug Bus.

The architecture of the CoreSight TPIU Lite is displayed on the Figure 4. The APB Slave is connected with the APB Debug Bus and the Trace Interface is connected with the Fabric.

The Trace memory is implemented using a DPRAM included on the Fabric CGB.

The architecture of the CoreSight DAP-Lite is displayed on the Figure 5. The APB System Slave is connected with the Fabric. The APB Debug Master is connected with the CoreSight TPIU and the CortexR5. The Serial Wire / JTAG (SWJ) interface is connected with the fabric. Both JTAG pins and serial interfaces are available via fabric for debugging purpose.

After a reset, the SWJ is configured in JTAG Mode. A 16-bit sequence on SWIOTMS switch the Mode (Serial Wire or JTAG).

For the debug sequence please refer to Cortex-R5_TechnicalReferenceManual - Chapter 12 (internal registers) and CoreSight TPIU-Lite Technical Reference Manua

*: Content of DAP rom:

0 : 0x00080000 (CORTEXR5ROM) (32b format)

1 : 0x00003000 (TPIULite) (32b format)

CortexR5 Configuration

Table 1: General Configuration

Macrocell interface

All signals above are connected to the FPGA. They are not controlled by the configuration module.

If the AXI peripheral port is activated, the base address PPXBASE0 needs to be set at 0xAE000 and the size PPXSIZE0 needs to be set at 0x07 (64Kb)

Macrocell usage

Clocking interface

All interfaces are synchronous to the processor clock, CLKIN. In many cases the FABRIC clock is at a lower frequency. This means that every rising edge on the FABRIC clock must be synchronous to a rising edge on CLKIN.

Each interface has a Clock Enable port. This input port must be asserted on every CLKIN rising edge for which there is a simultaneous rising edge on the FABIC clock. The Table 2 lists all clock enable port of each interface.

Table 2: Clock Enable Port

The Figure 6 shows the AMBA interface clocking. All Cortex R5 clocks and clock enable are generated by the CLKGEN system and distributed through the FABRIC clock network.

Figure 7 shows an example in which the processor is clocked at 200MHz (CLKIN) while the FABRIC system connected to the AXI master port, AXI Peripheral port and APB debug port are respectively clocked at 100MHz (AXI_MASTER_CLK), 100MHz (AXI_PERIHERAL_CLK) and 50MHz (APB_DEBUG_CLK). It should be noted that the AXI bus, implemented in FABRIC, cannot be faster than the processor clock.

Resets

The Table 3 lists all reset port of the CortexR5.

Table 3: CortexR5 Reset Ports

DBGReset is implemented and connected to PRESETSYSn.

Boot

Boot code outside of the TCM

The Boot code is included in ROM connected at the Bus Matrix or a Memory (SRAM, Flash, …) connected at the FPGA. The ROM or memory controller must be mapped in the reset memory space (start with the address 0). The TCM must be disabled or not mapped in the reset memory space.

• INITRAMAm must be tied LOW. ATCM is disabled at reset; or

• LOCZRAMAm must be tied LOW. ATCM initial address is 20’h40000.

In the boot code, the user can copy the program code in the TCM and jump a the TCM base address.

Boot example

Those command will allow you to compile the assembly code:

arm-none-eabi-as -march=armv7-r -mfpu=vfpv3-d16 gboot.s -o gboot.bin
arm-none-eabi-objdump -D gboot.bin|tee gboot.txt

Boot code example:

.global _prestart
.global _boot
.global __stack
.global __irq_stack
.global __supervisor_stack
.global __abort_stack
.global __fiq_stack
.global __undef_stack
.global _vector_table
/* this initializes the various processor modes */
_prestart:
_boot:
OKToRun:
/* Initialize processor registers to 0 */
 mov r0,#0
 mov r1,#0
 mov r2,#0
 mov r3,#0
 mov r4,#0
 mov r5,#0
 mov r6,#0
 mov r7,#0
 mov r8,#0
 mov r9,#0
 mov r10,#0
 mov r11,#0
 mov r12,#0
 mrs r0, cpsr /* get the current PSR */
 mvn r1, #0x1f /* set up the system stack pointer */
 and r2, r1, r0
 orr r2, r2, #0x1F /* SYS mode */
 msr cpsr, r2
 ldr r13,=#0x00000200 /* SYS stack pointer */
//
//* Disable MPU and caches */
 //mrc p15, 0, r0, c1, c0, 0 /* Read CP15 Control Register*/
 //bic r0, r0, #0x05 /* Disable MPU (M bit) and data
cache (C bit) */
 //bic r0, r0, #0x1000 /* Disable instruction cache (I
bit) */
 //dsb /* Ensure all previous loads/sto
res have completed */
 //mcr p15, 0, r0, c1, c0, 0 /* Write CP15 Control Register *
/
//isb /* Ensure subsequent insts execu
te wrt new MPU settings */
 /* Invalidate caches */
 //mov r0,#0 /* r0 = 0 */
 //dsb
 //mcr p15, 0, r0, c7, c5, 0 /* invalidate icache */
 //mcr p15, 0, r0, c15, c5, 0 /* Invalidate entire data cache*/
 //isb
 //mrc p15, 0, r1, c1, c0, 1 /* Read ACTLR */
 //str r1, [sp, #-8]
 //ldr r0, =0x30000 /* [17] = 1 = Return stack disabled. [16:15]
= 10 Branch always not taken and history table updates disabled. */
 //orr r1,r1,r0
 //dsb
 //mcr p15, 0, r1, c1, c0, 1
 //isb
 //str r1, [sp, #-8]
 b main /* jump to C startup code */
 
main:
 @ args = 0, pretend = 0, frame = 8
 @ frame_needed = 1, uses_anonymous_args = 0
 @ link register save eliminated.
 str fp, [sp, #-4]!
 add fp, sp, #0
 sub sp, sp, #12
 mov r3, #1056
 str r3, [fp, #-12]
 mov r3, #0
 str r3, [fp, #-8]
.L2:
 ldr r3, [fp, #-8]
 lsl r3, r3, #2
 ldr r2, [fp, #-12]
 add r3, r2, r3
 ldr r2, [fp, #-8]
 str r2, [r3]
 ldr r3, [fp, #-8]
 add r3, r3, #1
 add fp, fp, #16
 str r3, [fp, #-8]
b .L2
 .size main, .-main
 .ident "GCC: (15:6.3.1+svn253039-1build1) 6.3.1 20170620"

Boot code inside the TCM

The CPU can boot with the Preloaded TCM. The TCM must be enabled and mapped in the reset memory space.

• INITRAMAm must be tied HIGH. ATCM is enable at reset; and

• LOCZRAMAm must be tied HIGH. ATCM initial address is 0. The user can write the TCM directly with the Debug Access Port (DAP) or with the AXI slave interface.

During the TCM initialization, the CPU don’t fetch any instructions. The input port nCPUHALTm must be asserted.