1 List of figures
2 List of tables
3 Introduction
- 3.1 List of Acronyms ans Abreviations
4 Macrocell Description
- 4.1 Block Diagram
- 4.2 CortexR5 Configuration
- 4.3 Macrocell interface
5 Macrocell usage
- 5.1 Clocking interface
- 5.2 Resets
- 5.3 Boot
  - 5.3.1 Boot code outside of the TCM
  - 5.3.2 Boot example
  - 5.3.3 Boot code inside the TCM

List of figures

CortexR5 Overview

Architecture of CortexR5

Architecture of ETMr5

Architecture of TPIU-Lite

Architecture of DAP-Lite

Cortex R5 AMBA Interface Clocking

AXI and APB interface clocking

List of tables

General Configuration

Clock Enable Port

CortexR5 Reset Ports

Introduction

List of Acronyms ans Abreviations

ADD	Addition

ADD	Addition
FPGA	FPGA Field Programmable Gate Array
LUT	Look-Up Table
LVDS	Low Voltage Differential Signal
PLL	Phase Lock Loop
RAM	Random Access Memory
TBD	To Be Define

Macrocell Description

The macro cell nx_cortex_r5 contains:

• Cortex R5 CPU (r1p3-00rel0)

• CoreSight ETM R5

• CoreSight TPIU-Lite

• CoreSight DAP-Lite

Macrocell interface is the interface with the FPGA fabric.

Block Diagram

CortexR5 Overview

The previous figure shows the ecosystem of the Cortex R5 implemented in NG-LARGE. It includes the Cortex R5 processor, the debug facility, the Bus Matrix and all users IPs. The bus matrix and users IPs (memory, IO controller, coprocessor, …) are implemented in the fabric (part “Fabric User” on the Figure 1).

The Trace Ram and JTAG/Serial Wire controllers are also implemented in the fabric (part “Fabric Debug” on the following figure).

The architecture of the Cortex R5 is shown Figure Architecture of ETMr5. The section CortexR5 Configuration describes the Cortex R5 configuration.

This implementation of the Cortex R5 does not include the ACP (uSCU), B0TCM, B1TCM, PAHB interface.

The ATB interface is connected with the CoreSight TPIU Lite module and the APB Slave is connected with the APB Debug Bus.

The architecture of the CoreSight TPIU Lite is displayed on the Figure Architecture of TPIU-Lite. The APB Slave is connected with the APB Debug Bus and the Trace Interface is connected with the Fabric.

The Trace memory is implemented using a DPRAM included on the Fabric CGB.

The architecture of the CoreSight DAP-Lite is displayed on the Figure Architecture of DAP-Lite. The APB System Slave is connected with the Fabric. The APB Debug Master is connected with the CoreSight TPIU and the CortexR5. The Serial Wire / JTAG (SWJ) interface is connected with the fabric. Both JTAG pins and serial interfaces are available via fabric for debugging purpose.

After a reset, the SWJ is configured in JTAG Mode. A 16-bit sequence on SWIOTMS switch the Mode (Serial Wire or JTAG).

For the debug sequence please refer to Cortex-R5_TechnicalReferenceManual - Chapter 12 (internal registers) and CoreSight TPIU-Lite Technical Reference Manual.

Architecture of CortexR5

Architecture of ETMr5

Architecture of TPIU-Lite

Architecture of DAP-Lite*

*: Content of DAP rom:

0 : 0x00080000 (CORTEXR5ROM) (32b format)

1 : 0x00003000 (TPIULite) (32b format)

CortexR5 Configuration

Feature	Options	Sub-Options

Feature	Options	Sub-Options
Number of CPUs	Single-CPU (No redundancy)	-
Instruction cache	I-Cache included	32KB (4x8KB ways) (64-bit ECC error checking)
ATCM	One ATCM port	64KB (32-bit ECC error checking)
BTCM	No BTCM ports (No sufficient area)	-
Instruction endianness	Pin-configured	Little-endian of Big-endian
Floating point	FPU included	-
MPU	MPU included	-
TCM bus parity	No TCM address and control bus parity	-
AXI bus ECC/parity on AXImaster, AXI-slave and ACP	No AXI bus ECC/parity	-
Bus ECC/parity on AXI peripheral port and AHB peripheral port	No peripheral port bus ECC/parity	-
Breakpoints	2-8 breakpoint register pairs	8 breakpoints
Watchpoints	1-8 watchpoint registers	8 watchpoints
ATCM as reset	Disabled	-
BTCM as reset	Disabled	-
Axi slave interface	Enabled	-
TCM hard error cache	TCM hard error cache	-
Non-Maskable FIQ Interrupt	Disabled	-
Axi coherency port (ACP)	No ACP	-
AHB peripheral port	AXI peripheral only	-
Custom Power mode	none	-

General Configuration

Macrocell interface

Name	Direction	Width (bits)

Name	Direction	Width (bits)
Global
CLKIN	input	1
nRESET0	input	1
nSYSPORESET	input	1
nCPUHALT0	input	1
DBGNOCLKSTOP	input	1
nCLKSTOPPED0	output	1
nWFEPIPESTOPPED0	output	1
nWFIPIPESTOPPED0	output	1
EVENTI0	input	1
EVENTO0	output	1
Configuration
VINITHI0	input	1
CFGEE	input	1
CFGIE	input	1
INITRAMA0	input	1
LOCZRAMA0	input	1
TEINIT	input	1
CFGNMFI0	input	1
PARECCENRAM0 1	input	1
PARITYLEVEL 1	input	1
ERRENRAM0 1	input	1
GROUPID 4	input	4
INITPPX0 1	input	1
PPXBASE0 20	input	20
PPXSIZE0 5	input	5
PPVBASE0 20	input	20
PPVSIZE0 5	input	5
Interrupt
nFIQ0	input	1
nIRQ0	input	1
nPMUIRQ0	output	1
IRQACK0	output	1
IRQADDR0	input	30
IRQADDRV0	input	1
IRQADDRVSYNCEN	input	1
AXI3 Master
ACLKENM0	input	1
AWADDRM0	output	32
AWBURSTM0	output	2
AWCACHEM0	output	4
AWIDM0	output	4
AWLENM0	output	4
AWLOCKM0	output	2
AWPROTM0	output	3
AWREADYM0	input	1
AWSIZEM0	output	3
AWINNERM0	output	4
AWSHAREM0	output	1
AWVALIDM0	output	1
WDATAM0	output	64
WIDM0	output	4
WLASTM0	output	1
WREADYM0	input	1
WSTRBM0	output	8
WVALIDM0	output	1
BIDM0	input	4
BREADYM0	output	1
BRESPM0	input	2
BVALIDM0	input	1
ARADDRM0	output	32
ARBURSTM0	output	2
ARCACHEM0	output	4
ARIDM0	output	4
ARLENM0	output	4
ARLOCKM0	output	2
ARPROTM0	output	3
ARREADYM0	input	1
ARSIZEM0	output	3
ARINNERM0	output	4
ARSHAREM0	output	1
ARVALIDM0	output	1
RDATAM0	input	64
RIDM0	input	4
RLASTM0	input	1
RREADYM0	output	1
RRESPM0	input	2
RVALIDM0	input	1
AXI3 Slave
ACLKENS0	input	1
AWADDRS0	input	32
AWBURSTS0	input	2
AWCACHES0	input	4
AWIDS0	input	8
AWLENS0	input	4
AWLOCKS0	input	2
AWPROTS0	input	3
AWREADYS0	output	1
AWSIZES0	input	3
AWVALIDS0	input	1
WDATAS0	input	64
WIDS0	input	8
WLASTS0	input	1
WREADYS0	output	1
WSTRBS0	input	8
WVALIDS0	input	1
BIDS0	output	8
BREADYS0	input	1
BRESPS0	output	2
BVALIDS0	output	1
ARADDRS0	input	32
ARBURSTS0	input	2
ARCACHES0	input	4
ARIDS0	input	8
ARLENS0	input	4
ARLOCKS0	input	2
ARPROTS0	input	3
ARREADYS0	output	1
ARSIZES0	input	3
ARVALIDS0	input	1
RDATAS0	output	64
RIDS0	output	8
RLASTS0	output	1
RREADYS0	input	1
RRESPS0	output	2
RVALIDS0	output	1
AXI3 Peripheral
ACLKENP0	input	1
AWIDP0	output	4
AWADDRP0	output	32
AWLENP0	output	4
AWSIZEP0	output	3
AWBURSTP0	output	2
AWLOCKP0	output	2
AWCACHEP0	output	4
AWPROTP0	output	3
AWVALIDP0	output	1
AWREADYP0	input	1
WIDP0	output	4
WDATAP0	output	32
WSTRBP0	output	4
WLASTP0	output	1
WVALIDP0	output	1
WREADYP0	input	1
BIDP0	input	4
BRESPP0	input	2
BVALIDP0	input	1
BREADYP0	output	1
ARIDP0	output	4
ARADDRP0	output	32
ARLENP0	output	4
ARSIZEP0	output	3
ARBURSTP0	output	2
ARLOCKP0	output	2
ARCACHEP0	output	4
ARPROTP0	output	3
ARVALIDP0	output	1
ARREADYP0	input	1
RIDP0	input	4
RDATAP0	input	32
RRESPP0	input	2
RLASTP0	input	1
RVALIDP0	input	1
RREADYP0	output	1
Debug
DBGEN0	input	1
NIDEN0	input	1
EDBGRQ0	input	1
DBGACK0	output	1
DBGRSTREQ0	output	1
COMMRX0	output	1
COMMTX0	output	1
DBGNOPWRDWN	output	1
DBGROMADDR	input	20
DBGROMADDRV	input	1
DBGSELFADDR0	input	20
DBGSELFADDRV0	input	1
Validation
nVALIRQ0	output	1
nVALFIQ0	output	1
nVALRESET0	output	1
FPU
FPIXC0	output	1
FPOFC0	output	1
FPUFC0	output	1
FPIOC0	output	1
FPDZC0	output	1
FPIDC0	output	1
Power Modes
RAMCONTROL0	input	8
ATB
ATCLK	input	1
ATCLKEN	input	1
ATRESETn	input	1
Trace
TRACECLK	output	1
TRACEDATA	output	32
TRACECTL	TRACECTLx	1
APB System
PCLKSYS	input	1
PCLKENSYS	input	1
PRESETSYSn	input	1
PADDRSYS	input	29
PENABLESYS	input	1
PRDATASYS	output	32
PREADYSYS	output	1
PSELSYS	input	1
PSLVERRSYS	output	1
PWDATASYS	input	32
PWRITESYS	input	1
DAP
CDBGRSTACK	input	1
DEVICEEN	input	1
Serial Wire/JTAG
JTAGNSW	output	1
nPOTRST	input	1
nTDOEN	output	1
nTRST	input	1
SWCLKTCK	input	1
SWDITMS	input	1
SWDO	output	1
SWDOEN	output	1
TDI	input	1
TDO	output	1

All signals above are connected to the FPGA. They are not controlled by the configuration module.

If the AXI peripheral port is activated, the base address PPXBASE0 needs to be set at 0xAE000 and the size PPXSIZE0 needs to be set at 0x07 (64Kb)

Macrocell usage

Clocking interface

All interfaces are synchronous to the processor clock, CLKIN. In many cases the FABRIC clock is at a lower frequency. This means that every rising edge on the FABRIC clock must be synchronous to a rising edge on CLKIN.

Each interface has a Clock Enable port. This input port must be asserted on every CLKIN rising edge for which there is a simultaneous rising edge on the FABIC clock. The following table lists all clock enable port of each interface.

Clock Enable Port	Interface	Connection

Clock Enable Port	Interface	Connection
ACLKENMm	AXI Master Port	Core
ACLKENSm	AXI Slave Port	Core
ACLKENPm	AXI Peripheral Port	Core
PCLKENDBG	APB Debug Port	Core, ETM, DAP, TPIU
PCLKENSYS	APB System Port	DAP
ATCLKEN	ATB Port	TPIU

Clock Enable Port

The following figure shows the AMBA interface clocking. All Cortex R5 clocks and clock enable are generated by the CLKGEN system and distributed through the FABRIC clock network.

Cortex R5 AMBA Interface Clocking

The following figure shows an example in which the processor is clocked at 200MHz (CLKIN) while the FABRIC system connected to the AXI master port, AXI Peripheral port and APB debug port are respectively clocked at 100MHz (AXI_MASTER_CLK), 100MHz (AXI_PERIHERAL_CLK) and 50MHz (APB_DEBUG_CLK). It should be noted that the AXI bus, implemented in FABRIC, cannot be faster than the processor clock.

AXI and APB interface clocking

Resets

The following table lists all reset port of the CortexR5.

Reset Port	Descriptions

Reset Port

Descriptions

nRESETm

Main CPU reset

Resets the non-debug CPU logic

nSYSPORESET

Power On Reset

Resets the entire processor group including debug CPU logic

PRESETDBGm

CPU debug reset

Resets the debug domain logic and the APB interface of the CPU

CortexR5 Reset Ports

DBGReset is implemented and connected to PRESETSYSn.

Boot

Boot code outside of the TCM

The Boot code is included in ROM connected at the Bus Matrix or a Memory (SRAM, Flash, …) connected at the FPGA. The ROM or memory controller must be mapped in the reset memory space (start with the address 0). The TCM must be disabled or not mapped in the reset memory space.

• INITRAMAm must be tied LOW. ATCM is disabled at reset; or

• LOCZRAMAm must be tied LOW. ATCM initial address is 20’h40000.

In the boot code, the user can copy the program code in the TCM and jump a the TCM base address.

Boot example

Those command will allow you to compile the assembly code:

arm-none-eabi-as -march=armv7-r -mfpu=vfpv3-d16 gboot.s -o gboot.bin
arm-none-eabi-objdump -D gboot.bin|tee gboot.txt

Boot code example:

.global _prestart
.global _boot
.global __stack
.global __irq_stack
.global __supervisor_stack
.global __abort_stack
.global __fiq_stack
.global __undef_stack
.global _vector_table
/* this initializes the various processor modes */
_prestart:
_boot:
OKToRun:
/* Initialize processor registers to 0 */
 mov r0,#0
 mov r1,#0
 mov r2,#0
 mov r3,#0
 mov r4,#0
 mov r5,#0
 mov r6,#0
 mov r7,#0
 mov r8,#0
 mov r9,#0
 mov r10,#0
 mov r11,#0
 mov r12,#0
 mrs r0, cpsr /* get the current PSR */
 mvn r1, #0x1f /* set up the system stack pointer */
 and r2, r1, r0
 orr r2, r2, #0x1F /* SYS mode */
 msr cpsr, r2
 ldr r13,=#0x00000200 /* SYS stack pointer */
//
//* Disable MPU and caches */
 //mrc p15, 0, r0, c1, c0, 0 /* Read CP15 Control Register*/
 //bic r0, r0, #0x05 /* Disable MPU (M bit) and data
cache (C bit) */
 //bic r0, r0, #0x1000 /* Disable instruction cache (I
bit) */
 //dsb /* Ensure all previous loads/sto
res have completed */
 //mcr p15, 0, r0, c1, c0, 0 /* Write CP15 Control Register *
/
//isb /* Ensure subsequent insts execu
te wrt new MPU settings */
 /* Invalidate caches */
 //mov r0,#0 /* r0 = 0 */
 //dsb
 //mcr p15, 0, r0, c7, c5, 0 /* invalidate icache */
 //mcr p15, 0, r0, c15, c5, 0 /* Invalidate entire data cache*/
 //isb
 //mrc p15, 0, r1, c1, c0, 1 /* Read ACTLR */
 //str r1, [sp, #-8]
 //ldr r0, =0x30000 /* [17] = 1 = Return stack disabled. [16:15]
= 10 Branch always not taken and history table updates disabled. */
 //orr r1,r1,r0
 //dsb
 //mcr p15, 0, r1, c1, c0, 1
 //isb
 //str r1, [sp, #-8]
 b main /* jump to C startup code */
 
main:
 @ args = 0, pretend = 0, frame = 8
 @ frame_needed = 1, uses_anonymous_args = 0
 @ link register save eliminated.
 str fp, [sp, #-4]!
 add fp, sp, #0
 sub sp, sp, #12
 mov r3, #1056
 str r3, [fp, #-12]
 mov r3, #0
 str r3, [fp, #-8]
.L2:
 ldr r3, [fp, #-8]
 lsl r3, r3, #2
 ldr r2, [fp, #-12]
 add r3, r2, r3
 ldr r2, [fp, #-8]
 str r2, [r3]
 ldr r3, [fp, #-8]
 add r3, r3, #1
 add fp, fp, #16
 str r3, [fp, #-8]
b .L2
 .size main, .-main
 .ident "GCC: (15:6.3.1+svn253039-1build1) 6.3.1 20170620"

Boot code inside the TCM

The CPU can boot with the Preloaded TCM. The TCM must be enabled and mapped in the reset memory space.

• INITRAMAm must be tied HIGH. ATCM is enable at reset; and

• LOCZRAMAm must be tied HIGH. ATCM initial address is 0. The user can write the TCM directly with the Debug Access Port (DAP) or with the AXI slave interface.

During the TCM initialization, the CPU don’t fetch any instructions. The input port nCPUHALTm must be asserted.

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NG-LARGE Cortex R5