Important information

This document applies exclusively to the configuration of the NG-LARGE FPGA referenced NX1H140TSP.

For other NanoXplore chips, please refer to the associated documentation.

Introduction to NG-LARGE Configuration

NX1H140TSP is configured by loading the bitstream into internal configuration memory using one of these following modes:

JTAG,
Slave Parallel 8 bits,
Slave Parallel 16 bits,
Slave SpaceWire, compliant ECSS-E-ST-50-12C link,
Master SPI, compliant with SPI JESD68.01

WARNING: changing MODE value while RST_HARD_N is unasserted is strictly forbidden.

Bitstream size

This NX1H140TSP bitstream size depends on the amount of logic resources used by the application, the number of initialized Flip-flops and the number of user Core RAM and Core Register Files to be initialized.

Maximum user logic configuration (100%)	24.43Mb
Medium configuration (70%)	17.10Mb
Small configuration (50%)	12.22Mb
D-Flip-Flop initialization⁽¹⁾ (129024)	1b/D-Flip-Flop
Core RAM initialization⁽²⁾ (192 instances)	96.06Kb/RAM block
Core Register File initialization⁽²⁾ (672 instances)	3.03Kb/Register File
CMIC	64.15Kb
Total	44.53Mb

In a typical design the user can give – or not - an initial value to Flip-Flops at power-up. Reducing the number of initialized Flip-Flops contributes to reduce the bitstream size.
Core RAM and/or Core Register file can also be initialized – or not - at power-up. Reducing the number of initialized memories contributes to reduce the bitstream size.

Most applications do not require to initialize all memories.

These numbers are just estimations.

The actual size can be determined only by running the mapping software.

Configuration Memory Integrity Check (CMIC)

The CMIC is an embedded engine performing automatic verification and repair of the configuration memory.

A CMIC reference memory is initialized during the bitstream download process with reference data computed by the NanoXmap software.

Once the initialization is done, the CMIC engine can be periodically activated to perform the following sequence:

1. Read configuration data

2. Calculate signature

3. Compare the signature with CMIC reference

4. If a mismatch is detected:

a. Calculate faulty address (BAD @) and faulty bit location

b. Read DATA[BAD @]

c. Repair flipped bit

d. Write DATA[BAD @]

In case of error that cannot be corrected, for instance double error, the data is blacklisted in order to not generate definitive TRIGGER/ERROR high level.

For further information, please refer to the NX1H140TSP CMIC Application note.

Device configuration details

Purpose of NX1H140TSP configuration

NX1H140TSP chips are SRAM-based FPGAs. To achieve user-defined functionality their configuration bitstream must be downloaded first.

NX1H140TSP chips configuration modes summary

NX1H140TSP chips are always accessible through JTAG, and also support several configuration modes.

At power-up, MODE [2:0] pins state defines the configuration mode.

RST_HARD_N is a dedicated input pin that allows to reset the configuration engine, and launches the configuration process after RST_HARD_N is released. (It can’t be used to reset the FPGA user’s logic).

MODE [2:0]	Configuration mode

MODE [2:0]	Configuration mode
000 0x0	Master Serial SPI
001 0x1	Master Serial SPI with VCC control
010 0x2	Slave Spacewire
011 0x3	JTAG (reserved)
100 0x4	Slave Parallel 8-bit
101 0x5	Slave Parallel 16-bit
110 0x6	Reserved
111 0x7	Test mode

Table: NG-LARGE NX1H140TSP configuration modes

Multiple devices addressing

Thanks to Device ID feature in the Bitstream Manager, it is possible to connect multiple devices on the same bus and load a bitstream only to the desired device.

In broadcast mode (0xFF), all connected devices will load the bitstream in the configuration memory.

Multiple Device ID

Bitstream Device ID is set during bitstream generation. It is 8 bits large.

Chip Device ID is set by external pins. It is only 4 bits large.

Configuration modes usage

JTAG configuration channel is always active regardless the selected configuration mode. JTAG accesses while the configuration interface is active are not recommended (risk of conflict with the bitstream manager operation and render ineffective the bitstream manager)

In slave modes (SpaceWire, Slave Parallel 8 or Slave Parallel 16), NX1H140TSP chip must be fed its bitstream through the selected interface.

In Master Serial SPI modes, NX1H140TSP chip automatically fetches its bitstream from the external memory (SPI or SPI with Vcc control) after RST_HARD_N is released.

Prog bank pins state during and after configuration

According the selected configuration mode, each of the prog is “multi-usage”. Some of the active pins must be required for correct configuration, and some other pins must be left unconnected. In addition, some prog bank pins can be configured as additional user’s I/O, providing that the supported I/O standard is:

LVDS with external impedance adaptation for the dedicated SpaceWire pins.
LVCMOS_3.3V for the other prog pins (with 60 mA output drive for the outputs, and 10K to 40K default Pull-Up)

The prog bank pins that are not used or activated by the selected configuration mode are configured as High-Z during the configuration. After the configuration they stay configured as High-Z if not used, or take the user’s defined functionality.

JTAG input pins (TRST, TMS, TDI) get internal default Pull-Up (10K to 40K).

User’s I/O pins state during and after configuration

Before reset, I/Os state are undetermined.

During the configuration process, all user’s I/Os are configured as High-Z with an internal 10K to 40K default Pull-Up.

After configuration the user I/O pins behaves as defined by the bitstream.

Internal default Pull-Up is set on single ended inputs.

NX1H140TSP chips prog interface pin list

The user must provide the 3-bit MODE value to select the configuration mode. In addition, the internal configuration engine requires an external reset signal (RST_HARD_N). RST_HARD_N must be asserted (low) during at least 3 microseconds. When RST_HARD_N is de-asserted, the configuration process starts after up to 3 us delay, according the MODE bits settings.

WARNING: changing MODE value while RST_HARD_N is unasserted is strictly forbidden (undefined behavior).

Depending on the selected configuration MODE, some prog bank pins are activated during the process. Some other remain as inputs with internal Pull-Up during the configuration process.

In addition, some prog bank pins can be used as auxiliary user defined I/Os after completing the configuration.

The next table summarizes the list of pins that can be affected during the configuration process.

Grp	Name	I/O	Description

Grp	Name	I/O	Description

GLOBAL	MODE(2:0)	I	They define the configuration mode to be used for NG-LARGE configuration. MODE(2:0) cannot be changed when RST_HARD_N = ‘1’
	ID(3:0)	I	Device Identification. It must comply with the bitstream device id to allow access bitstream loading.
	FABRIC_USER(3:0)	I	Additional IO for user. FABRIC_USER[0] can be connected to low-skew network.
	CLK	I	Always required. Can be routed externally to CLK_OSC 100MHz internal oscillator (except in Master SPI modes) or to an external clock in the range [0MHz;100MHz].
	RST_HARD_N	I	Mandatory input. When low, it resets the internal configuration engine. RST_HARD_N must be low at least during 3 microseconds to ensure a proper configuration engine reset. When RST_HARD_N goes high, the configuration starts after up to 3 additional microseconds.
	RST_SOFT_N	I	It only resets internal configuration registers but does not apply a reset on the configuration memory.
	READY	O	Goes high when the configuration is complete (the FPGA enters in user’s mode)
	TRIGGER	O	Generates a high-level pulse (~20 ns or one CLK cycle) each time an error is encountered during the configuration and during design processing. Error is taken into account only if it is not masked by the associated TRIGGER_MASK.
	ERROR	O	Generates a high-level pulse (~20 ns or one CLK cycle) each time an error is encountered during the configuration and during design processing. Error is taken into account only if it is not masked by the associated ERROR_MASK.
	POK	O	Goes high when VDD1V2 Core and VDD2V5A Analog Supply are on.

Slave Parallel 16/8	CS	I	Active high Chip Select input. Used in Slave Parallel 16/8 mode. The master can write or read to/from the configuration engine when CS is high during a CLK rising edge.
	TYPE[1:0]	I	2-bits control input. Used in Slave Parallel 16/8 mode. It indicates the type of access: 0b00: ADDR_DEBUG 0b01: READ_DEBUG 0b10: WRITE_DEBUG 0b11: WRITE_CONF
	DATA_OE	O	Active high output. Used in Slave Parallel 16/8 mode. It is a data valid signal for reading operations.
	D(15 :0)	I/O	16-bit data bus used in Slave Parallel 16/8 mode to write the bitstream and/or read internal NG-LARGE internal state values. In case of Slave Parallel 8, only the first 8 LSB are used.

Master Serial SPI	D(8)	O	Used in Master Serial SPI and Master Serial SPI with Vcc control, as CS output to the external SPI Flash memory.
	D(9)	O	Used in Master Serial SPI and Master Serial SPI with Vcc control, as clock output to the external SPI Flash memory.
	D(10)	I	Used in Master Serial SPI and Master Serial SPI with Vcc control, as data input (MISO) from the external SPI Flash memory.
	D(11)	O	Used in Master Serial SPI and Master Serial SPI with Vcc control, as data output (MOSI) to the external SPI Flash memory (while writing a new bitstream into the SPI Flash.
	D(12)	I	Configured as input (with internal Pull-Up) during the configuration. Can be configured as, user’s I/O available after completing the configuration.
	D(13)	I/O	Configured as input (with internal PullPup) during the configuration in Master Serial SPI Configured as high level output during the configuration in Master Serial SPI with Vcc control. Can be configured as user I/O available after completing the configuration.
	D(14)	I/O
	D(15)	I/O

SpaceWire	DIN_P	I	SpaceWire interface is available after completing the configuration in Master Serial SPI, Master Serial SPI with Vcc control or Slave Parallel 8 o 16-bit modes. If SpaceWire is used for the configuration, it can’t be used for other purpose than the configuration.
	DIN_N	I
	SIN_P	I
	SIN_N	I
	DOUT_P	O
	DOUT_N	O
	SOUT_P	O
	SOUT_N	O

JTAG	TCK	I	JTAG CLK
	TMS	I	JTAG TMS
	TDI	I	JTAG TDI
	TRST_HARD_N	I	JTAG TRST_HARD_N
	TDO	O	JTAG TDO

Table: Configuration related pins

Detailed configuration modes

SPI Modes

On board SPI flash memory programming:

For Master Serial modes, the on-board flash memory programming operation requires changing the MODE[2:0] into Slave mode to ensure the accessibility to the flash.

The NX1H140TSP chip may then be configured through JTAG with a dedicated design to program the memory with the user data, also transmitted by JTAG. NxBase2 provides such design and commands to program a given list of SPI flash memories. Please refer to NanoXplore_NxBase2_User_Manual.

Endianness

The bitstream must be sent by 32bits words with less significant byte first. Each byte must be sent with most significant bit first.

As an example, 0x12345678 is the first word of each bitstream. It must be sent as follows:

Figure: Master Serial SPI endianness

Bistream manager clock

In Master SPI or in Master SPI + Vcc control, only an external clock can be used to connect to CLK IO.

Do not loop CLK_OSC to CLK in these modes.

Master Serial SPI configuration details:

The next figure shows a suggestion of schematic to implement the Master Serial SPI configuration, then the pin list table describes the behavior of the prog bank pins when this mode is selected.

Figure: Master Serial SPI configuration diagram example

Master Serial SPI Mode

Prog bank (INTERFACE) pins used and/or impacted by configuration

Group	Pin name	I, O or I/O	User I/O	During configuration
Group	Pin name	I, O or I/O	User I/O	Required	Impacted	Pin behavior

GLOBAL	MODE(2:0)	I	No	Yes	000	Input pins sampled at power-up. MODE(2:0). They define the configuration mode to be used for NG-LARGE configuration. MODE(2:0) cannot be changed when RST_HARD_N = ‘1’
	ID(3:0)	I	No	Yes	-	Device Identification. It must comply with the bitstream device id to allow access bitstream loading or the bitstream device id e equal to 0xF (broadcast mode).
	FABRIC_USER(3:0)	I	Yes	No	-	Additional IO for user. FABRIC_USER[0] can be connected to low-skew network.
	CLK	I	No	Yes	-	Always required. Must be routed to an external clock in the range [0MHz;100MHz].
	RST_HARD_N	I	No	Yes	-	Mandatory input. When low, it resets the internal configuration engine. RST_HARD_N must be low at least during 3 microseconds to ensure a proper configuration engine reset. When RST_HARD_N goes high, the configuration starts after up to 3 additional microseconds.
	RST_SOFT_N	I	No	No	-	It only resets internal configuration registers but does not apply a reset on the configuration memory.
	READY	O	No	No	Yes	Goes high when the configuration is complete (the FPGA enters in user’s mode)
	TRIGGER	O	No	No	Yes	Generates a high-level pulse (~20 ns or one CLK cycle) each time an error is encountered during the configuration and during design processing. Error is taken into account only if it is not masked by the associated TRIGGER_MASK.
	ERROR	O	No	No	Yes	Generates a high-level pulse (~20 ns or one CLK cycle) each time an error is encountered during the configuration and during design processing. Error is taken into account only if it is not masked by the associated ERROR_MASK.
	POK	O	No	No	No	Goes high when VDD1V2 Core and VDD2V5A Analog Supply are on.

Slave Parallel 8	CS	I	No	No	Yes	Unused but unavailable. Must be left unconnected
	TYPE[1:0]	I	No	No	Yes	Unused but unavailable. Must be left unconnected
	DATA_OE	O	No	No	Yes	Unused but unavailable. Must be left unconnected
	D(7:0)	I	No	No	Yes	Unused but unavailable. Must be left unconnected

Slave par ext	D(8)	O	No	Yes	-	External memory Chip Select (active Low) When the bitstream download is completed this pin is driven to ‘1’
	D(9)	O	No	Yes	-	External bitstream memory Clock When the bitstream download is completed this pin is driven to ‘0’
	D(10)	I	No	Yes	-	MISO (data in from external memory)
	D(11)	O	No	Yes	-	MOSI (data out to external memory) When the bitstream download is completed this pin is driven to ‘0’
	D(12)	I	Yes	No	No	Available as User’s I/O
	D(13)	I/O	Yes	No	No	Available as User’s I/O
	D(14)	I/O	Yes	No	No	Available as User’s I/O
	D(15)	I/O	Yes	No	No	Available as User’s I/O

SPACEWIRE	DIN_P	I	Yes(*)	No	No	When Master Serial SPI is selected the SpaceWire internal IP can be used after completing the configuration (*) The SpaceWire internal IP is available for the user’s application.
	DIN_N	I	Yes(*)	No	No
	SIN_P	I	Yes(*)	No	No

Configuration Guide NG-LARGE