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Introduction

The purpose of this document is to guide users of NanoXplore Impulse software through the steps involved in the design flow and to describe the options available in the NanoXplore Design Suite:

• Impulse
  A graphical user interface providing all the options necessary to complete your entire design flow and floorplanning exploration

• nxpython
  A wrapper around a Python executable that enables you to control Impulse software as a wrapper

  • nxpython fully supports Python syntax, structures and external modules

  • All commands for nxpython described in this document can be applied to the VHDL examples provided in the example folder

You can create new projects using either Impulse or nxpython

 

Requirements

Impulse is intended to operate on a 64 bits Linux workstation running one of the following distributions:

• CentOS 7

• CentOS 8

• RedHat Enterprise Linux 7

• RedHat Enterprise Linux 8

Impulse has also been tested on the following distributions:

• UBUNTU 18

• UBUNTU 20

• DEBIAN 11

Impulse requires Python however, to prevent conflicts, we do not provide a preinstalled version of Python with Impulse. Python must therefore be installed on the user's workstation. Impulse is compatible with Python versions 3.6 and above.

 

For any other distribution or platform issues, please contact the NanoXplore support team: support@nanoxplore.com.

When a command argument appears with parentheses around the brackets, e.g. “([argument])”, this means the argument is optional

System Requirements

Package Description

The Impulse archive provided contains the following directories.

Installation

To install Impulse:

1. Unpack the compressed nxdesignsuite-VERSION.tar.gz file to the installation directory of your choice
   (e.g. /opt/NanoXplore) using the following command:

   $> tar xzf nxdesignsuite-VERSION.tar.gz -C /opt/NanoXplore

2. Set the licence by exporting the following shell variable*:

   $> export LM_licence_FILE=27000@servername

*Where servername is the hostname of the server running the licence daemon and 27000 is the port the daemon listens to.

Run Impulse

To run Impulse, use the following command:

Run nxpython

To run nxpython, use the following command:

To access Python functionalities in Impulse, call the following command in nxpython:

Design Flow Overview

The entire Design Flow is performed in NanoXplore NX tools:

• Impulse (the dedicated NX graphical user interface), or

• nxpython (the NX Python command-line tool)

 Impulse supports VHDL and Verilog

• Impulse is a graphical interface to guide you through Project creation, as well as debug and inspect the design at various stages. For more information on Impulse, please see Impulse (Graphical User Interface)

• nxpython is a Python wrapper to control Impulse. It fully supports Python syntax, structures and external modules. You can use nxpython for the entire design flow or any specific step in the flow

• Both Impulse and nxpython are fully compatible so that any file generated by one can be used by the other at any stage in the design flow

NanoXplore design environment does not include any simulation tools, however, you can use third-party tools to simulate or verify the design by using HDL files generated by NanoXplore Design Flow

Project Creation

Creating a new project starts “from scratch”, which involves defining a project directory, adding sources and configuring settings which can be compulsory or optional.

See the following sections for instructions on how to create projects in Impulse or nxpython:

•  See Impulse (Graphical User Interface) to create a project with the impulse user interface

•  See the Nxpython specification to create a project with the nxpython command-line interface

Synthesis

Synthesis translates the design hardware description into a gate-level netlist using FPGA resources.

You can run the Synthesise step of the design flow in both Impulse and the nxpython environments (please refer to sections Synthesise and synthesise().

Place and Route

The Place and Route steps are performed on the synthesised design generated in the previous step.

In these steps, solutions for implementation are found to fit the user's design to the FPGA physical architecture:

• The placement task computes the positions of the basic instance elements based on design and user-defined constraints

• The routing process then assigns signals of the design to routing resources to successfully route all nets while achieving a given overall performance

 

 The Place and Route steps of design flow can be executed in both the Impulse and nxpython environments:

•  See Place & Route for further information on how to launch corresponding states through Impulse

• See place() and route() to learn how to launch the corresponding steps through command lines in the nxpython interface

Bitstream Generation

Bitstream data format is used to programme the FPGA.

Note: This step can only be launched after a Routing step has been successfully completed

• See Export Bitstream and generateBitstream(file) for more details

Design Netlist Generation and Simulation

In nxpython, you can generate Post-Synthesis, Post-Place and Post-Route design netlists (Verilog or VHDL) which can be useful for simulation purposes (see section save(file)).

In Impulse, intermediate netlists are generated automatically

Third-party simulation tools can be used for design verification on Post-Synthesis, Place and Route files. Generated design netlists are provided along with the FPGA elements library.

This library is provided to the user in VHDL-protected format.

• The library file can be found at the following directory path:

  $> /opt/NanoXplore/impulse/VERSION/share/modelsim/nxLibrary.vhdp

Static Timing Analysis

Static Timing Analysis (STA) can be performed by using its Timing analyser tool to analyse, debug, and validate the timing performance of the design.

This feature produces a detailed report on the timing characteristics of the design, i.e. timing domains in the design, longest/shortest paths in the domain, path delay, data arrival time, clock skew, etc.

Static Timing Analysis can be performed by Impulse (see section Static Timing Analysis) and nxpython (see section Static Timing Analysis related methods).

Welcome Screen

When you launch Impulse, a welcome screen opens offering quick access to startup tools.

The page is divided into the following areas:

• Menu bar
  The main toolbar at top of the page displays the menus with a selection of available tools and options

• Start
  The Start area at left gives you quick access to create or open projects:

  • Create New Project
    Opens the Project Creation Wizard which guides you through the steps to create a new project

  • Open Project
    Opens the File Manager to import your desired project into Impulse

  • Open Example Project
    Opens an example project with prefilled sample data and information to help become familiar with the tools and features in Impulse such as the Project Creation Wizard and Design Flow functionalities

Note: You can use your Example Project to run any step of the Design Flow

Tip: Click on the Run button in any step in the Design Flow to automatically run all previous steps

• Recent
  The area at right of the page displays the last opened projects (use your mouse-wheel to scroll down the list of recent projects)

• Learn
  Opens the Help and Documentation window with access to NX FPGA range datasheets, Impulse User Guide and beginner-level troubleshooting articles and FAQ’s

• Python Console
  The console enables you to execute python commands in the GUI or view any python command that was previously executed in the interface

Click the maximise icon at right to expand or contract the window

Create New Project (Wizard)

To create your project and configure the environment of your choice:

• Click Create New Project in the Start Panel at left, or

• In the Menu bar at top, click File > New > Project

The resulting window is a Project Creation Wizard which guides you through the steps to create your project:

Step 1: Set Project Information

Define a project name and project location where files, logs, reports and data during the flow execution will be written:

1. Type your desired name in the Project name field

2. Type the path of your choice in the Project location field or click the Browse button at right to define a location for your project
   Tick the Use as Default Project Location checkbox to set it as default for all New Projects

3. You can add an optional description

4. Click the Next button at bottom-right to move on to step 2
   
   

Step 2: Add Sources

Specify the Sources for your project (RTL files, netlist, Block Design, IP files, library, script):

1. Click on the Add Files button under the Name and Location area, or
   Click on the Add Directories button to add directories containing your sources
   Note: You may need to use the scrollbar at right to navigate down to the buttons

2. Tick the Copy Source Files to Project checkbox to create a duplicate copy of the selected sources in the project directory
   Note: Only the following file extensions are supported: sv, .vhdl, .vhd, .v, .vh, .svh and .py
   Note: The Name is the directory name of the folder where scripts, files and reports will be written

3. Click Next at bottom-right to move to step 3 or, if you wish, you can also set Top Cell information at this point (see Optional sub-steps below)

(Optional) Set Top Cell Information

To enter the Top Cell Name or Library:

1. Type the Top Cell Name and/or Top Cell Library directly in the corresponding fields at right, or
   Navigate to the file where the Top Cell Name is defined

2. Right-click on the file and

3. Click on the Select as Top Cell

4. Click Next at bottom-right to move on to step 3 or, if you wish to do so, you can set optional Top Cell Parameters (see the section below)

Note: The Top Cell Name must be the name of the top cell declared in the top-level project HDL file

Note: The Top Cell Library is used to specify the library in which the top cell is defined (work library is defined by default)

Note: Both parameters can be modified in Project Settings after the project creation

(Optional) Set Parameters of the Top Design Entity

You can also declare generic HDL parameters for selected top-level project design sources at this step:

1. Click on the "+" button

2. Fill in the Name field for the parameter and

3. Enter a value in the Value field

4. Click Next to proceed to step 3

Note: Only parameters with a valid Name and Value can be applied

You can add as many parameters as you require

top level

You can also use nxpython to assign generic parameters to the top level of the user design via the execution of python scripts. For further information on the assignment of parameters via nxpython, see the addParameter(name, value) or addParameters(parameters) commands

Step 3: Add Constraintsdrop-down

You can specify physical or timing constraints associated with the project if you have an existing constraints file in .sdc, .xdc or .py format.

Follow these steps:

1. Click on the Add Files button (or Add Directory to add a folder)
   Note: You may need to use the scrollbar at right to navigate down to the buttons

2. Browse and select your desired File/Directory and click Add

3. Tick the Copy Constraints File to the Project checkbox to create a duplicate copy in the project directory

Step 4: Select Devices

To select a device and associated package:

1. Click on the down arrow at right of the Device or Package field to open the drop-down menu

2. Click on the desired device and package

   • Repeat steps (1) and (2) for both the Device and the Package fields

3. Click on the Next button at bottom to move on to step 5

Step 5: Project Summary

Check all the information is as you wish for your new project in the Project Summary screen.

• If any of the settings need modification, click the Back button to return to the appropriate step and follow the instructions described in the previous sections

• If all is as desired, click the Finish button to confirm the creation of your project and close the Project Creation Wizard

Open Project

You can load projects at any step or sub-step phase of the design flow, as long as the project has been saved in .NYM format during execution of the corresponding step.

Impulse supports databases and projects to .NYM format only

To open an existing project:

1. Click on Open Project in the welcome screen, or

   • Scroll through the Recent history at right and click to open your desired project, or

   • Click File > Open > Project

2. Navigate to the .nym file of your choice

3. Double-click the file or click to select your project and click the Open button

Open an Example Project (Wizard)

Impulse also enables you to create new projects based on existing test cases which are bundled with the tool.

To do so do one of the following:

• In the welcome screen, click Open an Example Project in the Start section at centre-left, or

• In the main toolbar at top, click File > New > Project Example

Step 1: Select a Project Template

1. Use your mouse wheel or cursor to select a Template from the available list and

2. Click the Next button at bottom-right to move to Step 2
   
   

   Open

   

   Select a Project Template

Step 2: Select a Device

1. Use the drop-down menus to select your device and associated package then

2. Click the Next button at bottom-right to move to step 3
   
   

   Open

   

   Select a Device

Step 3: Set Project Information

1. Type your desired name in the Project name field

2. Type the path of your choice in the Project location field or click the Browse button at right to define the location for your project
   Tick the Use as Default Project Location checkbox to set your choice as default for all New Projects

3. Click the Next button at bottom-right to move to step 4

   Open

   

   Set Project Information

Step 4: Project Summary

1. Check the details in the Project Summary screen and and

2. Click the Finish button at bottom to confirm creation of your Example Project, or

3. Click the Back button to go back to any previous step and modify the details as desired

   Open

   

   Project Summary

Help Menu

The Help menu at far right of the main menu toolbar at top contains the following options:

• Open Help and Documentation
  The Help and Documentation screen provides access to NX FPGA range datasheets, Impulse User Guide and beginner-level troubleshooting articles and FAQ’s

• Find Technical Support
  Access to our Support Team for any questions about our products or licences

• Report Issue
  Opens the NanoXplore Support Portal with access to Ticket Creation, Knowledge Base Articles, Release Notes, etc.)

• Licence Manager
  Displays list of all features enabled by the NanoXplore licence file management tool

• About Impulse
  Displays the current software version with the associated distribution information

Help and Documentation Screen

The Help and Documentation screen provides access to helpful resources laid out in 3 main areas:

• DataSheet (top-left):

  • Datasheets for NanoXplore’s range of FPGA devices

    • Documents providing technical descriptions of the electronic components and features are included as well as instructions to use or configure them

• Impulse User Guide (top-right)

• Help & Troubleshooting

  • Simple troubleshooting, knowledge articles and FAQ’s for beginner-level users

Help & Troubleshooting

When you click on the Help > Open Help and Documentation option, the Help & Troubleshooting section at bottom of the page provides basic help and troubleshooting tips for beginners.

How To

 

The How To guides providestep-by-stepp instructions to perform basic operations such as project creation, I/O pad configuration or bitstream generation.

Design Flow Overviews

These short guides are general functional descriptions of the Impulse Design Flow features, including conceptual presentations of the Synthesis, Place and Route processes.

Known Issues

These describe common issues and their workarounds, such as oversize, overflow behaviour or blending tile errors you may encounter during execution of the placing and routing phases.

Licence Manager

The Licence Manager lists all features enabled under the current licence file, such as the various FPGA models or specific options and attributes available.

About Impulse

Click on Help > About Impulse to view Licence information and Distribution details.

Note: This information is required when you contact NanoXplore Support with queries or issues

Edit Project

When you create or load a project or database, the main workspace opens with all available project management tools to edit, run, rerun any step of the NanoXplore Impulse design flow.

The Impulse interface is laid out as follows:

• Main Menu Bar at top

• Editor bar at left with the main editing and configuration tools:

  • Project Settings

  • STA Manager

  • IP Catalogue

  • I/O Attribute Editor

  • Floorplan

• Project Sources Editor at centre-top of the screen

• Design Flow Navigator at centre-bottom of the screen

• The main area at top-right to configure the Editors

  • Click on a tool in the Editor bar to access the configuration settings in this area

• The Python Console at bottom-right

Main Menu Bar

You can access all project management tools and editors through the horizontal menu at top:

• File
  The File Menu contains the following options:

  • New
    Enables you to create new:

    • Projects/Example Projects

    • Constraint files, or

    • Design Source files

  • Open
    Enables you to open an existing project

  • Save Project/Save Project As
    Save your project in NYM format or in various other archive formats such as SDF, VHD or V

  • Generate SDF or Generate Netlist files at the corresponding design flow steps

  • Exit
    To close the application

• Edit
  Enables you to set User Preferences (click Apply to validate your changes then OK to close the preferences screen):

  • Environment Settings

    • Interface (Themes and Font size

    • Dialogue (enable/disable dialogue boxes)

    • Enable/diable Welcome Screen

    • Window Layout preferences

  • Shortcuts

    • Personalise your shortcut settings

  • Build Settings

    • Define various options for Build edition to select which default name for .nym file generation

  • Text Editor preferences

    • Select preferred editor along with associated font properties

  • Console Configuration

  • View

    • Edit navigation options related to the graphical interface

• Project

  • Provides access to the Project Settings Menu (also avaiable via the corresponding Project Editor icon)

  • Enfables you to run Source Analysis in order to check design libraries dependencies and packages found in HDL sources of the current project and

  • Offers menu shortcuts to execute each of the design flow steps available to run Synthesis, Place and Route and to generate Bitstream

• Tools

  • Lists all the provided tools within Impulse for the following:

    • Static Timing Analysis Manager

    • Constraints Editor

    • IP Catalogue NxCore Generator

    • IO Editor and

    • Floorplan View

• Reports

  • Prints various reports concerning the project in a dedicated Impulse panel.
    Note: it is mandatory to execute NanoXplore flow steps through Impulse graphical interface to be able to print corresponding reports

• Window

  • Enables you to select whether to view or hide panels of the Impulse interface like the Python console, the Flow navigator, Reports, Log, Messages, Editor, Sources template and Project sources

• Help

  • Edit Impulse default settings and check release and licence features information

 

Editing Tools

The main Editors in the bar at left enable you to configure your project and device. Click on an editor to invoke the tool’s setting panel in the area at top-right.

Project Settings

The Project Settings editor enables you to configure project settings and edit parameters related to each step of the NanoXplore Design Flow:

Project Settings also enable you to change the default settings for the Synthesis, Place, Route and Bitstream steps:

Constraints Editor

The Constraints Editor identifies existing timing constraints that have been previously declared via python script or graphical execution through python console and saved in the database.

The Constraints Editor includes the followin categories for timing constraints classifications:

• Clock-related constraints such as:

  • CreateClock(), CreateGeneratedClock() and SetClockGroup()

• Inputs

  • Lists SetInputDelay() constraints

• Outputs

  • Lists SetOutputDelay() constraints

• Exceptions

  • Regroups SetMulticyclePath(), SetFalsePath(), SetMaxDelay(), SetMinDelay() and SetCaseAnalysis() constraints

The Constraint Editor respects the following syntax for declaration:

• Mandatory arguments, which are marked with a red asterisk (“*”), and

• Optional arguments, which are available for certain constraints by clicking on Add Parameters:

STA Manager

The STA Manager enables you to schedule or to directly launch a Static Timing Analysis after the Synthesis, Place or Route steps, depending on parameters such as;

• Requested condition case scenario

• Maximum number of violating paths or

• Maximum slack upon analysis

IP Editor

The IP Editor provides graphical access to the IP Catalogue NxCore Generator provided with Impulse for IP configuration and generation concerning the provided list:

I/O Attribute Editor

The I/O Editor opens enables manual attribution or modification of placement of Inputs and Outputs in the selected device up to launch of the first step of Place. Once Place step 1/5 is launched, the location of Inputs and Outputs are defined either by user-defined constraints or automatically by the software.

I/O Config

The I/O Config tab shows how the input and output ports of the current design are mapped on specific pads with the following associated Pad Features:

See the addPad(name, parameters) command section for further details on Pad features.

Banks CKG Config

The Banks CKG Config tab shows:

• Which banks with associated voltage are configured for the inputs/outputs of the Top Entity Design, and

• Which CKG are used to control clock distribution into the design, including the location of the WFG which Impulse will use.

Data available in the I/O Attribute Editor can be copied, exported to files or imported from files using the following icons:

Export I/O Data

You can export your I/O Config and Banks CKG Config data to an external file in python script (PY) format in comma-separated values (CSV) format.

1. Click on the Export Data icon at left

   Open

   

2. Navigate to the location of your choice in the File Manager

3. Enter your desired file name in the Name field

4. Click on the down arrow at bottom-right

   Open

   

5. Select your your choice of file format in the drop-down menu

   Open

   

6. Click the Save button

Import I/O Data

You can import an external set of pad assignments to configure rings either in via a dedicated python script or a CSV file.

Importing an external set of pad assignments can only be performed between execution of the Synthesis step and execution of first step of Place. Otherwise, the tool will provide automatic pad configuration to execute the Place & Route flow steps.

Floorplan Editor

Click Floorplan to open the graphical Floorplan design view at loaded .nym database status :

Project Management

Once the multiple settings for the creation of the current project have been completed, user enters project management to launch design flow steps through Impulse panel.

The design flow steps are available for launching through either the dedicated Flow Navigator panel or the previously described scrolling Tools menu:

Each flow step in the Flow Navigator allows for editing associated flow options to the selected step before launching it, run either the whole Synthesis, Place & Route flow or a selected sub-step for each flow part, the possibility to generate netlist files, possibly SDF files after Route or to run a Static Timing analysis available for each flow step:

Once one or several flow steps have been successfully executed and completed, you can check the Messages panel to look at reported Infos, Warnings & Errors, verify the step flow execution in the associated Log window.

Users also have direct graphical access to reports generated at each flow step - labelled in green - in the Reports panel along the Flow navigator.

Logging

All messages generated by the application such as generic information, warning and error messages or reports are stored into several log and report files, using either nxpython or Impulse.

When using nxpython the “logsPython” subdirectory is created into the working directory and log files are created inside it during flow execution. nxpython provides several commands to print error, warning or texting user defined messages (see section Export bitstream).

When using the GUI,the “logs” subdirectory is created into the working directory and log files and reports are saved inside.

Several log files are created:

 

Report generation

Several reports are generated during the design processing to give information about resource utilization such as instances, ports, regions or timing.

Hdlfiles report

nxpython lists in hdlfiles.rpt report all HDL source files provided to Verific tool and also reports in which source file the Top Cell is declared.

Hdlanalysis report

nxpython lists in hdlanalysis.rpt report the messages issued by the Verific tool during the analysis of HDL source files. This files provides the name of all modules which have been compiled.

Fsmachines report

nxpython lists in fsmachines.rpt detailed information about finite state machines (FSM) identified in the design. If no FSM has been found, the file will be empty.

Hierarchy report

nxpython reports in hierarchy.rpt all instances for each module specifically kept by user with the command addModule(). By default, the file reports only the top level module, written ‘~’, if no module has been declared by user. See section addModule(model, instance, format) for description of this nxpython command and check carefully section Creating and handling regions for a complete and detailed example on the best way to keep modules.

Instances report

User has the possibility to generate instances report utilization of the design mapped on the current variant. For more information about generating instances report with nxpython, please refer to section reportInstances().