This NX1H35AS bitstream size depends on the amount of logic resources used by the application, the number of initialized Flip-flops and the number of user Core RAM and Core Register Files to be initialized.

Maximum user logic configuration (100%)	6.77Mb
Medium configuration⁽¹⁾ (70%)	4.74Mb
Small configuration⁽¹⁾ (50%)	3.38Mb
Maximum Core RAM initialization⁽²⁾	5.50Mb
Maximum Core Register File initialization⁽²⁾	258.04Kb
CMIC	22.44Kb
Maximum bitstream size	12.55Mb

In a typical design the user can give – or not - an initial value to Flip-Flops at power- up. Reducing the number of initialized Flip-Flops contributes to reduce the bitstream size.
Core RAM and/or Core Register_file can also be initialized – or not - at power-up. Reducing the number of initialized memories contributes to reduce the bitstream size.

Most applications do not require to initialize all memories. A typical bitstream is less than 8Mb.

These numbers are just estimations. The actual size can be determined only by running the mapping software.

Configuration Memory Integrity Check (CMIC)

The CMIC is an embedded engine performing automatic verification and repair of the configuration memory.

A CMIC reference memory is initialized during the bitstream download process with reference data computed by the NanoXmap software.

Once the initialization is done, the CMIC engine can be periodically activated to perform the following sequence:

Read configuration data
Calculate signature
Compare the signature with CMIC reference
If a mismatch is detected:
1. Calculate faulty address (BAD @) and faulty bit location
2. Read DATA[BAD @]
3. Repair flipped bit
4. Write DATA[BAD @]

For further information, please refer to the NX1H35AS CMIC Application note.

Device configuration details

Purpose of NX1H35AS configuration

NX1H35AS chips are SRAM-based FPGAs. To achieve user-defined functionality their configuration bitstream must be downloaded first.

NX1H35AS chips configuration modes summary

NX1H35AS chips are always accessible through JTAG, and also support several configuration modes. At power-up, MODE[3:0] pins state define the configuration mode. RST_N is a dedicated input pin that allows to reset the configuration engine, and launches the configuration process after RST_N is released. (It can’t be used to reset the FPGA user’s logic).

When MODE[3]='0', internal 50 MHz is used as Bitstream manager clock. Otherwise, user must provide an external clock.

MODE[3:0]	MODE[3:0]	Configuration mode

MODE[3:0]	MODE[3:0]	Configuration mode
0b0000	0x0	Master Serial
0b0001	0x1	Jtag Only
0b0010	0x2	Master Serial SPI
0b0011	0x3	Master Serial SPI with Vcc control
0b0100	0x4	Slave SpaceWire
0b0101	0x5	RESERVED
0b0110	0x6	Slave Parallel 8
0b0111	0x7	Slave Parallel 16
0b1000	0x8	Master Serial
0b1001	0x9	RESERVED
0b1010	0xA	Master Serial SPI
0b1011	0xB	Master Serial SPI with Vcc control
0b1100	0xC	Slave SpaceWire
0b1101	0xD	RESERVED
0b1110	0xE	Slave Parallel 8
0b1111	0xF	Test Mode

NG-MEDIUM NX1H35AS configuration modes

Multiple devices addressing

Thanks to Device ID feature in the Bitstream Manager, it is possible to connect multiple devices on the same bus and load a bitstream only to the desired device.

In broadcast mode (0xFF), all connected devices will load the bitstream in the configuration memory.

Multiple Device ID

Bitstream Device ID is set during bitstream generation. It is 8 bits large.

Chip Device ID is set by Bitstream Manager register. It is only 4 bits large.

Configuration modes usage

JTAG configuration channel is always active regardless the selected configuration mode. JTAG accesses while the configuration interface is active are not recommended (risk of conflict with the bitstream manager operation)

In slave modes (SpaceWire, Slave Parallel 8 or Slave Parallel 16), NX1H35AS chip must be fed its bitstream through the selected interface.

In Master Serial SPI modes, NX1H35AS chip automatically fetches its bitstream from the external memory (SPI or SPI with Vcc control) after RST_N is released.

MODE pins must be static and not change while RST_N is not activated.

Prog bank pins state during and after configuration

According the selected configuration mode, each of the prog is “multi-usage”. Some of the active pins must be required for correct configuration, and some other pins must be left unconnected. In addition, some prog bank pins can be configured as additional user’s I/O, providing that the supported I/O standard is:

LVDS with internal impedance adaptation for the dedicated Spacewire pins.
LVCMOS_3.3V for the other prog pins (with 60 mA output drive for the outputs, and 10K to 40K default PullUp)

The prog bank pins that are not used or activated by the selected configuration mode are configured as inputs with internal default PullUp (10K to 40K) during the configuration. After the configuration they stay configured as inputs with internal default PullUp if not used, or take the user’s defined functionality.

User’s I/O pins state during and after configuration

Before reset, I/Os state are undetermined.

During the configuration process, all user’s I/Os are configured in High-Z with an internal 10K to 40K default Pullup.

After configuration the user I/O pins behaves as defined by the bitstream. Internal default PullUp is set on single ended inputs. Internal PullDown is not available. For external PullDown resistors, NanoXplore recommends 1K to 2.2K values.

Bitstream loading

It is recommended to do a reset power cycle with RST_N pin before loading a bitstream.

In case a bitstream is already loaded and CMIC is enabled, it is mandatory

NX1H35AS chips prog interface pin list

The NX1H35AS presents 40 signal pins.

The user must provide the 4-bit MODE value to select the configuration mode. In addition, the internal configuration engine requires an external reset signal (RST_N). RST_N must be asserted (low) during at least 3 microseconds. When RST_N is de-asserted, the configuration process starts after up to 3 us delay, according the MODE bits settings.

Depending on the selected configuration MODE, some prog bank pins are activated during the process. Some other remain as inputs with internal PullUp during the configuration process.

In addition, some prog bank pins can be used as auxiliary user’s defined I/Os after completing the configuration.

The next table summarizes the list of pins that can be affected during the configuration process.

Group	Name	I/O	Description

Group	Name	I/O	Description
GLOBAL	MODE(3 :0)	I	They define the configuration mode to be used for NG-MEDIUM configuration. MODE(3:0) cannot be changed when RST_N = ‘1’
	CLK	I	Required only for slave parallel 8/16 configuration (20 or 50 MHz). For other configuration modes, must be tied to 3.3V via 10KOhms pullup resistor
	RST_N	I	Mandatory input. When low, it resets the internal configuration engine. RST_N must be low at least during 3 microseconds to ensure a proper configuration engine reset. When RST_N goes high, the configuration starts after up to 3 additional microseconds.
	READY	O	Goes high when the configuration is complete (the FPGA enters in user’s mode)
	ERROR	O	Generates a high level pulse (~20 ns or one CLK cycle) each time an error is encountered during the configuration.
Slave Parallel 8	CS_N	I	Active low Chip_Select input. Used in Slave Parallel 8 mode. The master can write or read to/from the configuration engine when CS_N is low during a CLK rising edge.
	WE_N	I	Active low Write_Enable input. Used in Slave Parallel 8 mode. The master can write to the configuration engine when both CS_N and WE_N are low during a CLK rising edge.
	DATA_OE	O	This pin is reserved. Must be left unconnected
	D(7 :0)	I/O	8-bit data bus used in Slave Parallel 8 mode to write the bitstream and/or read internal NG-MEDIUM internal state values

Slave Parallel 16	CS_N	I	Active low Chip_Select input. Used in Slave Parallel 16 mode. The master can write or read to/from the configuration engine when CS_N is low during a CLK rising edge.
	WE_N	I	Active low Write_Enable input. Used in Slave Parallel 16 mode. The master can write to the configuration engine when both CS_N and WE_N are low during a CLK rising edge.
	DATA_OE	O	This pin is reserved. Must be left unconnected
	D(15 :0)	I/O	16-bit data bus used in Slave Parallel 16 mode to write the bitstream and/or read internal NG-MEDIUM internal state values
Master Serial SPI	D(8)	O	Used in Master Serial SPI and Master Serial SPI with Vcc control, as CS_N output to the external SPI Flash memory.
	D(9)	O	Used in Master Serial SPI and Master Serial SPI with Vcc control, as clock output to the external SPI Flash memory.
	D(10)	I	Used in Master Serial SPI and Master Serial SPI with Vcc control, as data input (MISO) from the external SPI Flash memory.
	D(11)	O	Used in Master Serial SPI and Master Serial SPI with Vcc control, as data output (MOSI) to the external SPI Flash memory (while writing a new bitstream into the SPI Flash.
	D(12)	I	Configured as input (with internal PullUp) during the configuration. Can be configured as,user’s I/O available after completing the configuration.
	D(13)	I/O	Configured as input (with internal PullPup) during the configuration in Master Serial SPI Configured as high level output during the configuration in Master Serial SPI with Vcc control. Can be configured as,user’s I/O available after completing the configuration.
	D(14)	I/O
	D(15)	I/O
SpaceWire	DIN_P	I	SpaceWire interface is available after completing the configuration in Master Serial SPI, Master Serial SPI with Vcc control or Slave Parallel 8 o 16-bit rmodes. If SpaceWire is used for the configuration, it can’t be used for other purpose than the configuration.
	DIN_N	I
	SIN_P	I
	SIN_N	I
	DOUT_P	O
	DOUT_N	O
	SOUT_P	O
	SOUT_N	O
JTAG	TCK	I	JTAG clock
	TMS	I	JTAG TMS
	TDI	I	JTAG TDI
	TRST_N	I	JTAG TRST_N
	TDO	O	JTAG TDO

Configuration related pins

Detailed configuration modes

SPI Modes

On board SPI flash memory programming:

For Master Serial modes, the on-board flash memory programming operation requires changing the MODE[3:0] into Slave mode to ensure the accessibility to the flash. The NX1H35AS chip may then be configured through JTAG with a dedicated design, to program the memory with the user data, also transmitted by JTAG.

Temporary change of the configuration mode, might be:

Master Serial SPI mode 0010 moved to 0001
Master Serial SPI-Vcc mode 0011 moved to 0001

(“0110” Slave Parallel 8 and “0100” Slave SpaceWire are also valid for “on board SPI Flash programming”).

Please refer to the NXbase2 User Manual – Board related commands for detailed information.

Master Serial SPI configuration details:

The next figure shows a suggestion of schematic to implement the Master Serial SPI configuration, then the pin list table describes the behavior of the prog bank pins when this mode is selected.

Endianness

The bitstream must be sent by 32bits words with less significant byte first. Each byte must be sent with most significant bit first.

As an example, 0x12345678 is the first word of each bitstream. It must be sent as follows:

Master Serial SPI endianess

Master Serial SPI Mode

Master Serial SPI configuration diagram example

Master Serial SPI Mode

Prog bank (INTERFACE) pins used and/or impacted by configuration

Group	Pin name	I, O or I/O	User I/O	During configuration
Group	Pin name	I, O or I/O	User I/O	Required	Impacted	Pin behavior
GLOBAL	Mode(3 :0)	I	No	0010	-	Configuration Mode
	RST_N	I	No	Yes	-	Active Low Reset of the internal configuration engine. Mandatory input. When low, it resets the internal configuration engine. RST_N must be low at least during 3 us to ensure a proper configuration engine reset. When RST_N goes high, the configuration starts after up to 3 us RST_N is released.
	READY	O	No	No	Yes	Goes High when the configuration is complete
	ERROR	O	No	No	Yes	Generates a High level pulse if an error has been detected during the configuration (~20 ns pulse)
	CLK	I	No	No	-	Not required (tie to 3.3V via pull-up resistor)
Slave	CS_N	I	No	No	Yes	Unused but unavailable. Must be left unconnected
	WE_N	I	No	No	Yes	Unused but unavailable. Must be left unconnected
	DATA_OE	O	No	No	Yes	Unused but unavailable. Must be left unconnected
	D(7:0)	I	No	No	Yes	Unused but unavailable. Must be left unconnected
Slave par ext	D(8)	O	No	Yes	-	External memory Chip Select (active Low) When the bitstream download is completed this pin is drived to ‘1’
	D(9)	O	No	Yes	-	External bitstream memory Clock When the bitstream download is completed this pin is drived to ‘0’
	D(10)	I	No	Yes	-	MISO (data in from external memory)
	D(11)	O	No	Yes	-	MOSI (data out to external memory) When the bitstream download is completed this pin is drived to ‘0’
	D(12)	I	Yes	No	No	Available as User’s I/O
	D(13)	I/O	Yes	No	No	Available as User’s I/O
	D(14)	I/O	Yes	No	No	Available as User’s I/O
	D(15)	I/O	Yes	No	No	Available as User’s I/O
SPACEWIRE	DIN_P	I	Yes(*)	No	No	When Master Serial SPI is selected the SpaceWire internal IP can be used after completing the configuration (*) The SpaceWire internal IP is available for the user’s application.
	DIN_N	I	Yes(*)	No	No
	SIN_P	I	Yes(*)	No	No
	SIN_N	I	Yes(*)	No	No
	DOUT_P	O	Yes(*)	No	No
	DOUT_N	O	Yes(*)	No	No
	SOUT_P	O	Yes(*)	No	No
	SOUT_N	O	Yes(*)	No	No
JTAG	TCK	I	No	No	No	JTAG is available in all modes. Don’t use it while configuration is in progress.
	TMS	I	No	No	No
	TDI	I	No	No	No
	TRST_N	I	No	No	No
	TDO	O	No	No	No

Master Serial SPI configuration pin description

Master Serial SPI with Vcc control configuration details:

The next figure shows a suggestion of schematic to implement the Master Serial SPI with VCC control configuration, then the pin list table describes the behavior of the prog bank pins when this mode is selected.

This configuration mode is the same as Master Slave SPI, with the only difference that the SPI Flash memory is powered by using 3 pins of the NG-MEDIUM prog bank to supply the external SPI. This can contribute to reduce the risk of corruption of bitstream/data stored into the external SPI memory device.

Master Serial SPI Mode with VCC control

Master Serial SPI with Vcc configuration diagram example

Master Serial SPI Mode with VCC control

Prog bank (INTERFACE) pins used and/or impacted by configuration

Group	Pin name	I, O or I/O	User I/O	During configuration
Group	Pin name	I, O or I/O	User I/O	Required	Impacted	Pin behavior
GLOBAL	Mode(3 :0)	I	No	0011	-	Configuration Mode
	RST_N	I	No	Yes	-	Active Low Reset of the internal configuration engine. Mandatory input. When low, it resets the internal configuration engine. RST_N must be low at least during 3 us to ensure a proper configuration engine reset. When RST_N goes high, the configuration starts up to 3 us after RST_N is released.
	READY	O	No	No	Yes	Goes High when the configuration is complete
	ERROR	O	No	No	Yes	Generates a High level pulse if an error has been detected during the configuration (~20 ns pulse)
	CLK	I	No	No	-	Not required (tie to 3.3V via pull-up resistor)
Slave	CS_N	I	No	No	Yes	Unused but unavailable. Must be left unconnected
	WE_N	I	No	No	Yes	Unused but unavailable. Must be left unconnected
	DATA_OE	O	No	No	Yes	Unused but unavailable. Must be left unconnected
	D(7:0)	I	No	No	Yes	Unused but unavailable. Must be left unconnected
Slave Par ext	D(8)	O	No	Yes	-	External memory Chip Select (active Low) Requires a diode + PullUp (see diagram) When the bitstream download is completed this pin is drived to ‘1’
	D(9)	O	No	Yes	-	External bitstream memory Clock When the bitstream download is completed this pin is drived to ‘0’
	D(10)	I	No	Yes	-	MISO (data in from external memory)
	D(11)	O	No	Yes	--	MOSI (data out to external memory) When the bitstream download is completed this pin is drived to ‘0’
	D(12)	I	Yes	No	No	Available as User’s I/O
	D(13)	I/O	Yes	Yes	-	To Vcc SPI Flash memory When the bitstream download is completed this pin is drived to ‘0’
	D(14)	I/O	Yes	Yes	-	To Vcc SPI Flash memory When the bitstream download is completed this pin is drived to ‘0’
	D(15)	I/O	Yes	Yes	-	To Vcc SPI Flash memory When the bitstream download is completed this pin is drived to ‘0’
SPACEWIRE	DIN_P	I	Yes(*)	No	No	When Master Serial SPI with Vcc Control is selected the SpaceWire internal IP can be used after completing the configuration (*) The SpaceWire internal IP is available for the user’s application.
	DIN_N	I	Yes(*)	No	No
	SIN_P	I	Yes(*)	No	No
	SIN_N	I	Yes(*)	No	No
	DOUT_P	O	Yes(*)	No	No
	DOUT_N	O	Yes(*)	No	No
	SOUT_P	O	Yes(*)	No	No
	SOUT_N	O	Yes(*)	No	No
JTAG	TCK	I	No	No	No	JTAG is available in all modes. Don’t use it while configuration is in progress.
	TMS	I	No	No	No
	TDI	I	No	No	No
	TRST_N	I	No	No	No
	TDO	O	No	No	No

Master Serial SPI configuration pin description

Frequency clock configuration for Master Serial SPI Mode / Master Serial SPI Mode with VCC control

The frequency of SPI clock is defined by the field spi_clk_ratio, inside the SPI_CTRL register, handled by the Bitstream Manager. spi_clk_ratio defines the divider applied to the SPI clock, the default value is 17 which implies the following default SPI frequency : spi_clk/spi_clk_ratio = 50MHz / 17 = 3MHz.

The default SPI clock value in the generated bitstream aimed to be programmed in the Flash SPI memory can be modified using the NXmap3 method initRegister(command, value).

As an example, the user would like to modify the default 3MHz frequency of SPI clock to increase it to 13MHz. To do so, the default value 0x01f4003f of SPI_CTRL register must be overridden with the corresponding change for spi_clk_ratio field : spi_clk_ratio = 2 implies 50MHz / (2+2) = 13MHz (see details in the spi_clk_ratio values of SPI_CTRL). The SPI_CTRL register value obtained is 0x01f40032. In order to program this value into the bitstream, the user must declare the following command during flow execution in NXmap3:

project.initRegister('SPI_CTRL', '0x01f40032')

project.generateBitstream('bitstream.nxb')

Then the SPI Flash memory is programmed with the bitstream. After this, the FPGA configured in master SPI mode will load the bitstream from the memory and the SPI clock frequency will change from 3MHz to 13MHz once the corresponding instruction in the bitstream will be read.

Slave SpaceWire configuration details:

The next figure shows a suggestion of schematic to implement the Slave SpaceWire configuration, then the pin list table describes the behavior of the prog bank pins when this mode is selected.

Slave SpaceWire

Slave Spacewire configuration diagram example

Slave SpaceWire

Prog bank (INTERFACE) pins used and/or impacted by configuration

Group	Pin name	I, O or I/O	User I/O	During configuration
Group	Pin name	I, O or I/O	User I/O	Required	Impacted	Pin behavior
GLOBAL	Mode(3:0)	I	No	1100	-	Configuration Mode
	RST_N	I	No	Yes	-	Active Low Reset of the internal configuration engine. Mandatory input. When low, it resets the internal configuration engine. RST_N must be low at least during 3 us to ensure a proper configuration engine reset. When RST_N goes high, the configuration starts up to 3 us after RST_N is released.
	READY	O	No	No	Yes	Goes High when the configuration is complete
	ERROR	O	No	No	Yes	Generates a High level pulse if an error has been detected during the configuration (~20 ns pulse)
	CLK	I	No	No	-	Not required (tie to 3.3V via pull-up resistor)
Slave Parallel	CS_N	I	No	No	Yes	Unused but unavailable. Must be left unconnected
	WE_N	I	No	No	Yes	Unused but unavailable. Must be left unconnected
	DATA_OE	O	No	No	Yes	Unused but unavailable. Must be left unconnected
	D(7:0)	I	No	No	Yes	Unused but unavailable. Must be left unconnected
Slave Par ext	D(8)	O	No	No	-	Available as User’s I/O
	D(9)	O	No	No	-	Available as User’s I/O
	D(10)	I	No	No	-	Available as User’s I/O
	D(11)	O	No	No	-	Available as User’s I/O
	D(12)	I	Yes	No	No	Available as User’s I/O
	D(13)	I/O	Yes	No	-	Available as User’s I/O
	D(14)	I/O	Yes	No	-	Available as User’s I/O
	D(15)	I/O	Yes	No	-	Available as User’s I/O
SPACEWIRE	DIN_P	I	No	Yes	-	When Slave SpaceWire configuration mode is selected, the SpaceWire IP remains dedicated to configuration monitoring functions.
	DIN_N	I	No	Yes	-
	SIN_P	I	No	Yes	-
	SIN_N	I	No	Yes	-
	DOUT_P	O	No	Yes	-
	DOUT_N	O	No	Yes	-
	SOUT_P	O	No	Yes	-
	SOUT_N	O	No	Yes	-
JTAG	TCK	I	No	No	No	JTAG is available in all modes. Don’t use it while configuration is in progress.
	TMS	I	No	No	No
	TDI	I	No	No	No
	TRST_N	I	No	No	No
	TDO	O	No	No	No

Slave Spacewire configuration pin description

Spacewire configuration instructions

The supported SPW instructions by the NG-Medium FPGA are as stated in table below.

Command Code	Command

Command Code	Command
0x01	ADDR_DEBUG
0x02	READ_DEBUG
0x04	WRITE_DEBUG
0x08	WRITE_CONF

NG-Medium SPW instructions

ADDR_DEBUG instruction

The ADDR_DEBUG instruction is used to set the address of the loader register which will be accessed in all subsequent instructions. Following figure illustrates the format of the packet. Note that if many reads and writes will be performed to the same register only one ADDR_DEBUG instruction is needed.

ADDR_DEBUG instruction

READ_DEBUG instruction

READ_DEBUG instruction

The READ_DEBUG instruction is used to read the loader register value from the address defined by the previous ADDR_DEBUG instruction. READ_DEBUG instruction is a 1-byte packet containing only the instruction code (0x02) as shown in 5 below. The FPGA responds with a 4-bytes packet containing the read value which is sent LSB first as shown in 6.

Figure 6: READ_DEBUG reply

WRITE_DEBUG instruction

The WRITE_DEBUG instruction is used to write a value to the address of the loader register defined by the previous ADDR_DEBUG instruction. WRITE_DEBUG instruction contains the instructions code (0x04) followed by 4-bytes data to be written. Data is sent LSB first as shown in the following figure.

WRITE_DEBUG instruction

WRITE_CONF instruction

The WRITE_CONF instruction is used to program the NG-MEDIUM FPGA. The SPW packet size depends on bitstream size and it has the following fields:

Instruction code: 0x08 for WRITE_CONF
FPGA bitstream: the bitstream to be programmed into the FPGA.

WRITE_CONF instruction

This field is obtained by converting each 32bits bitstream word to 4 bytes sent LSB first as illustrated in the following figure.

Bitstream packing into SPW packet

Slave parallel 8 configuration details:

The next figure shows a suggestion of schematic to implement the Slave Parallel 8 configuration, then the pin list table describes the behavior of the prog bank pins when this mode is selected.

Slave Parallel 8

Slave Parallel 8 configuration diagram example

Slave Parallel 16

Slave Parallel 16 configuration diagram example

Slave Parallel 8 – Slave Parallel 16

Prog bank (INTERFACE) pins used and/or impacted by configuration

Group	Pin name	I, O or I/O	User I/O	During configuration
Group	Pin name	I, O or I/O	User I/O	Required	Impacted	Pin behavior
GLOBAL	Mode(3:0)	I	No	1110	-	Configuration Mode
	RST_N	I	No	Yes	-	Active Low Reset of the internal configuration engine. Mandatory input. When low, it resets the internal configuration engine. RST_N must be low at least during 50 CLK cycles to ensure a proper configuration engine reset. When RST_N goes high, the configuration starts after up to 50 CLK cycles.
	READY	O	No	No	Yes	Goes High when the configuration is complete
	ERROR	O	No	No	Yes	Generates a High level pulse if an error has been detected during the configuration (pulse width = one CLK cycle)
	CLK	I	No	Yes	-	20 to 50 MHz input clock for the configuration engine (must be strictly greater than twice the frequency of TCK is JTAG is used)
Slave Parallel	CS_N	I	No	Yes	-	Active low Chip Select input
	WE_N	I	No	Yes	-	Active low Write Enable input
	DATA_OE	O	No	Yes	-	This pin is reserved. Must be left unconnected
	D(7 :0)	I/O	No	Yes	-	8-bit data bus (input during the configuration)
Slave Par ext	D(8)	I/O	Yes	No	No	Slave Parallel 8 : Available as User’s I/O Slave Parallel 16 :
	D(9)	I/O	Yes	No	No
	D(10)	I/O	Yes	No	No
	D(11)	I/O	Yes	No	No
	D(12)	I/O	Yes	No	No
	D(13)	I/O	Yes	No	No
	D(14)	I/O	Yes	No	No
	D(15)	I/O	Yes	No	No
SPACEWIRE	DIN_P	I	Yes(*)	No	No	When Slave Parallel 8 is selected the SpaceWire internal IP can be used after completing the configuration (*) The SpaceWire internal IP is available for the user’s application.
	DIN_N	I	Yes(*)	No	No
	SIN_P	I	Yes(*)	No	No
	SIN_N	I	Yes(*)	No	No
	DOUT_P	O	Yes(*)	No	No
	DOUT_N	O	Yes(*)	No	No
	SOUT_P	O	Yes(*)	No	No
	SOUT_N	O	Yes(*)	No	No
JTAG	TCK	I	No	No	No	JTAG is available in all modes. Don’t use it during configuration
	TMS	I	No	No	No
	TDI	I	No	No	No
	TRST_N	I	No	No	No
	TDO	O	No	No	No

Slave Parallel 8 – Slave Parallel 16 configuration pins description

Slave Parallel interface usage

In Slave Parallel 8 and Slave Parallel 16 modes, the configuration clock must be provided to the FPGA on the dedicated CLK input pin. Its frequency can range from 20 MHz to 50 MHz, in any case it must be strictly greater than twice the JTAG (TCK) frequency – if used.

In order to avoid setup/hold time problems, the master can use the falling CLK edge to generate CS_N, WE_N and D(7:0) or D(15:0).

The master can start downloading the bitstream bytes after 50 configuration clock (CLK) cycles.

Each byte (or word) is written on the rising edge of CLK, while CS_N and WE_N are activated (low level) simultaneously. Dummy cycles can be inserted – if required by the master by de-asserting both CS_N and WE_N during one or more cycles between any two consecutive bytes. The next figure illustrates an example of timing diagram.

Timing diagram example

Hereafter the setup and hold times for Slave parallel NG-MEDIUM configuration interface:

PAD	setup time (ps)	hold time (ps)
RST_N	1354	106
CS_N	1879	19
WE_N	785	247
D0	-454	481
D1	-146	445
D2	-222	395
D3	-19	421
D4	836	181
D5	16	451
D6	-17	435
D6	-96	495
D8	244	471
D9	268	353
D10	1188	212
D11	739	341
D12	1327	361
D13	2138	247
D14	819	331
D15	935	341

PAD	CKtoQ_min	CKtoQ_max
READY	3125	7156
ERROR	2926	6219
DATA_OE	3526	8993

Internal interface between fabric and BSM

The following signals can be used by the fabric and consequently get an impact in the design if needed by users:

Grp	Name	I/O	Description

BSM	COLD_START	I	Goes high if the FPGA is ready and not reboot because of error occurred.
	CMIC_CORR[10:0]	I	Sum of all CMIC corrected errors counters (8 bits counter by row for 5 rows).
THS	OVF	I	Overflow of allowed range.
	DRDY	I	Data is ready.
	DATA[6:0]	I	Data in the range [0;127].

Boundary scan

IEEE 1149 JTAG implementation

NX1H35AS devices support IEEE Std 1149.1 JTAG boundary scan operation for board and device testing.

The EXTEST, INTEST, SAMPLE, BYPASS, IDCODE, USERCODE, and HIGHZ instructions are all included. The tap also supports internal user-defined registers (USER1, USER2) and instructions for device configuration and test.

JTAG interface pins include the standard TCK, TMS, TDI and TDO pads, as well as the optional TRST pad.

NX1H35AS chips JTAG instructions

NX1H35AS chips boundary scan instructions are the following:

Hex	Instruction	Function

Hex	Instruction	Function
0x0	EXTEST	Boundary scan external test
0x1	SAMPLE	Boundary scan sample
0x1	PRELOAD	Boundary scan preload
0x2	WR_CONF	Nanoxplore bitstream download
0x3	WR_DEBUG	Write debug instruction
0x4	RD_DEBUG	Read debug instruction
0x5	ADDR_DEBUG	Address debug instruction
0x6	INTEST	Boundary scan in internal test
0x7	IDCODE	Boundary scan design identification
0x8	USRCODE	User design identification register
0x9	USER1	User registers access
0xA	USER2	User registers access
0xC	HIGHZ	Tri-state all device I/Os
0xF	BYPASS	Single-clock bypass TDI to TDO

Boundary scan instructions

NX1H35AS devices provide a 1046-bit scan chain, described in each device BSDL file.

The WRITE_CONF instruction is used to program the NG-MEDIUM FPGA.

The ADDR_DEBUG instruction is used to set the address of the loader register which will be accessed in all subsequent instructions.

The READ_DEBUG instruction is used to read the loader register value from the address defined by the previous ADDR_DEBUG instruction.

The WRITE_DEBUG instruction is used to write a value to the address of the loader register defined by the previous ADDR_DEBUG instruction.

The IDCODE instruction returns the NG-MEDIUM Identification’s code: 0x675.

The USRCODE instruction returns the user-defined code (0xFFFFFFFF by default). The USER1 instruction is used to access to the user1 registers from the FPGA fabric. The USER2 instruction is used to access to the user2 registers from the FPGA fabric. The HIGHZ instruction is used to deactivate the outputs of all pins.

The BYPASS instruction is used to bypass the device.

NX1H35AS boundary scan usage

NX1H35AS chips are fully programmable devices, so boundary scan instructions usage requires some minimal device configuration using a limited bitstream, especially for the EXTEST instruction:

pads to be used as outputs need a minimum output drive configuration.
pads to be used as inputs need a minimum input thresholds configuration.

NX1H35AS boundary scan errata

NX1H35AS chips boundary-scan architecture presents some implementation bugs, listed below:

Chip initialization with unused JTAG interface

Problem:

When JTAG interface is not used, the NX1H35AS chip initialization may fail on a boundary scan initialization error. The interface initialization requires at least one rising edge on the TCK JTAG clock.

Workaround:

unused JTAG input pads TCK, TMS and TDI should be provided a 10-100KΩ pull- up resistor to VDDIO_SERVICE.
unused TRST input should be provided a 1KΩ pull-down resistor
TCK should be driven by a diode (anode) connected to RST_N (cathod) prog interface reset pin, so that the end-of-reset rising edge provides the required TCK.

Dedicated clock inputs in boundary scan INTEST

Problem:

In boundary scan INTEST instruction execution, the dedicated clock inputs on the SIMPLE banks (0, 1, 6 and 8) are seen by the internal design as simple inputs but not as clock inputs.

Dedicated clock inputs on the COMPLEX banks (2, 5, 9 and 12) are fully functional in boundary scan INTEST.

ANGIE JTAG adaptator

In order to debug a component, it can be very useful to use ANGIE adaptor and NxBase2 software.

An EEPROM is recommended in order to work in non-OEM mode. In this way, the board will be automatically recognized by the software.

Please refer to NxBase2 User Manual documentation in ANGIE chapter.

NG_MEDIUM register

To access a register, the user needs to use the ADDR_DEBUG instruction first, and then the WR_DEBUG or RD_DEBUG instructions.

NG-MEDIUM is divided in 5 rows with the following set of registers for each row. When addressing a register, address is 32 bits long with the following mapping:

Address	Mapping

Address	Mapping
[31:16]	Address of the row. 0xff indicates a broadcast mode addressing all rows in the same time.
[15:0]	Address of register for the corresponding row.

When generating a bitstream, default values are sent for all registers but it is possible to change these values inside the bitstream. Refer to initRegister NXmap method.

Address	Register Name	R/W	Description

Address	Register Name	R/W	Description
0x00	STATUS	R	Status register
0x0b	JTAG_IDCODE	R	JTAG identification code
0x0c	JTAG_USERCODE	RW	JTAG user code
0x0d	SPI_CTRL	RW	SPI configuration
0x0e	ERROR1	R	Error Flags
0x0f	ERROR1_MASK	RW	Error Mask
0x10	ERROR2	R	Error Flags
0x11	ERROR2_MASK	RW	Error Mask
0x12	EVENT_CNT1	R	Event Counter 1
0x13	EVENT_CNT2	R	Event Counter 2
0x14	MAX_ERROR_CNT	RW	Error counter
0x15	DEVICE_ID	RW	FPGA Device ID
0x1a	THSENS_CTRL	RW	Thermal Sensor Configuration
0x1b	THSENS_DATA	R	Thermal Sensor Data
0x1c	DUMP_CTRL	RW	DUMP configuration
0x1d	SPW_CTRL1	RW	SPACEWIRE configuration
0x1e	SPW_CTRL2	RW	SPACEWIRE configuration
0x1f	LOADER_CTRL	RW	Loader Controller

STATUS

Name	Address	Access	Reset Value	Description

Name	Address	Access	Reset Value	Description
STATUS	0x00	Read-only	0x0000	Status register

Bits	Field name	rst	Description

Bits	Field name	rst	Description
[15]	had_error_unmasked	0x0	1 when ERRORx contents flags errors (without application of mask vector)
[14]	had_error	0x0	1 when ERRORx contents flags errors (with application of mask vector)
[13]	status_cmic_run	0x0	1 when CMIC is running
[5]	status_max_error	0x0	1 when the Max Error is reach
[4]	status_error	0x0	1 when the Error Flag is rise
[3]	status_download	0x0	1 when the loader download a bitstream
[2]	status_prog	0x0	1 when the Programmation Flag is rise
[1]	status_cold_start	0x0	1 when the Ready Flag is first run
[0]	status_ready	0x0	1 when the Ready Flag is rise

JTAG_IDCODE

Name	Address	Access	Reset Value	Description

Name	Address	Access	Reset Value	Description
JTAG_IDCODE	0x0b	Read-only	0x00000675	JTAG identification code

Bits	Field name	rst	Description

Bits	Field name	rst	Description
[31:28]	jtag_idcode_version	0x0	Version number
[27:12]	jtag_idcode_part	0x0	Part number
[11:1]	jtag_idcode_manufacturer	0x33a	Manufacturer ID: 11:8 (4bits) bank, 7:1 (7bits) manufacturer id
[0]	jtag_idcode_one	0x1	Constant Always 1

JTAG_USERCODE

Name	Address	Access	Reset Value	Description

Name	Address	Access	Reset Value	Description
JTAG_USERCODE	0x0c	Read-write	0xffffffff	JTAG user code

Bits	Field name	Reset Value	Description

Bits	Field name	Reset Value	Description
[31:0]	jtag_usercode	0xffffffff	JTAG user code

SPI_CTRL

Name	Address	Access	Reset Value	Description

Name	Address	Access	Reset Value	Description
SPI_CTRL	0x0d	Read- write	0x1f4003f	SPI configuration

Bits	Field name	rst	Description

Bits	Field name	rst	Description
[30:15]	spi_powerup_cycle	0x3e8	PowerUp duration (need 300us). Number of clock cycles needed for 300us
[14:12]	spi_dummy_cycle	0x0	Number of Dummy cycle
[11:4]	spi_read_code	0x3	SPI Read Code
[3:0]	spi_clk_ratio	0xf	SPI Clock frequency is divided by spi_clk_ratio+2

ERROR1

Name	Address	Access	Reset Value	Description

Name	Address	Access	Reset Value	Description
ERROR1	0x0e	Read-only	0x00000000	Error Flags

Bits	Field name	Description

Bits	Field name	Description
[31]	flag_error_spi_sel	SPI selection error flag
[30]	flag_error_parallel_read_access_ovf	Parallel read access overflow
[29]	flag_error_parallel_write_access_conflict	Parallel write access conflict
[28]	flag_error_fifo_serializer_full	FIFO of serializer full
[27]	flag_error_reg_read_unaccepted	Register read access is rejected
[26]	flag_error_reg_write_unaccepted	Register write access is rejected
[25]	flag_error_bl_read_unaccepted	Bootloader read is rejected
[24]	flag_error_cfgctx_read_unaccepted	CFGCTX read is rejected
[23]	flag_error_cfgctx_write_unaccepted	CFGCTX write is rejected

Bits	Field name	Description

Bits	Field name	Description
[22]	flag_error_clear_unaccepted	Clear command rejected
[21]	flag_error_bltest_unaccepted	Bootloader test command is rejected
[20]	flag_error_reg_read_busy	Register read busy error
[19]	flag_error_reg_write_busy	Register write busy error
[18]	flag_error_bl_read_busy	Bootloader read busy error
[17]	flag_error_cfgctx_read_busy	CFGCTX read busy error
[16]	flag_error_cfgctx_write_busy	CFGCTX write busy error
[15]	flag_error_clear_busy	Clear busy error
[14]	flag_error_bltest_busy	Bootloader test busy error
[13]	flag_error_invalid_address	Address is invalid
[12]	flag_error_direct_engine_rsp_busy	Direct engine response is busy
[11]	flag_error_direct_engine_rsp_conflict	Direct engine response in conflict
[10]	flag_error_direct_engine_req_invalid_loader	Direct engine request signals invalid loader
[9]	flag_error_access_write_conflict	Write access conflict detected
[8]	flag_error_frame_engine_edac_uncorrected	Uncorrected error on frame engine's EDAC
[7]	flag_error_frame_engine_crc_frame	CRC error detected on frame
[6]	flag_error_frame_engine_crc_bitstream	CRC error detected on bitstream
[5]	flag_error_frame_engine_watchdog_timeout	Watchdog's timeout is reached
[4]	flag_error_frame_engine_unexpected_frame	Frame received but not expected
[3]	flag_error_frame_engine_req_invalid_loader	Invalid loader error detected on frame request
[2]	flag_error_frame_access_conflict	Access conflict detected on frame
[1]	flag_error_direct_access_rsp_conflict	Direct access response conflict detected
[0]	flag_error_direct_access_req_conflict	Direct access request conflict detected

ERROR1_MASK

Name	Address	Access	Reset Value	Description

Name	Address	Access	Reset Value	Description
ERROR1_MASK	0x0f	Read-write	0x00000000	Error Mask

Bits	Field name	rst	Description

Bits	Field name	rst	Description
[31:0]	flag_error1_mask	0x0	Mask register for ERROR1

ERROR2

Name	Address	Access	Reset Value	Description

Name	Address	Access	Reset Value	Description
ERROR2	0x10	Read-only	0x00	Error Flags

Bits	Field name	Description

Bits	Field name	Description
[9]	flag_error_spw_link_broken	SPW link disconnection error detected
[8]	flag_error_spw_err_int	SPW internal error detected
[7]	flag_error_spw_nom_int	SPW NOM error
[6]	flag_error_cmic_max_run	CMIC max run error
[5]	flag_error_cmic_check_uncorrected	CMIC error is uncorrected
[4]	flag_error_cmic_ref_edac_uncorrected	CMIC reference for EDAC is uncorrected
[3]	flag_error_cmic_ref_addr_ovf	CMIC reference address overflow detected
[2]	flag_error_cmic_access_conflict	Conflict detected on CMIC access
[1]	flag_error_spw_unexpected_packet	Unexpected SPW packet detected
[0]	flag_error_spw_eep	SPW EEP marker detected

ERROR2_MASK

Name	Address	Access	Reset Value	Description

Name	Address	Access	Reset Value	Description
ERROR2_MASK	0x11	Read-write	0x000	Error Mask

Bits	Field name	rst	Description

Bits	Field name	rst	Description
[9:0]	flag_error2_mask	0x000	Mask register for ERROR2

EVENT_CNT1

Name	Address	Access	Reset Value	Description

Name	Address	Access	Reset Value	Description
EVENT_CNT1	0x12	Read	0x0000	Event counter 1

Bits	Field name	rst	Description

Bits	Field name	rst	Description
[15:0]	ERROR_CNT	0x00	Number of errors since last hardware reset

EVENT_CNT2

Name	Address	Access	Reset Value	Description

Name	Address	Access	Reset Value	Description
EVENT_CNT2	0x13	Read	0x00000000	Event counter 2

Bits	Field name	rst	Description

Bits	Field name	rst	Description
[31:24]	CMIC_CHECK_SIGNATURE_CNT	0x00	CMIC signature error counter
[23:16]	CMIC_CHECK_CORRECTED_CNT	0x00	CMIC corrected error counter
[15:8]	CMIC_REF_EDAC_CORRECT_CNT	0x00	Reference EDAC corrected error counter
[7:0]	FRAME_ENGINE_EDAC_CORRECT_CNT	0x00	Frame engine EDAC corrected error counter

MAX_ERROR_CNT

Name	Address	Access	Reset Value	Description

Name	Address	Access	Reset Value	Description
MAX_ERROR_CNT	0x14	Read-write	0x0000000f	Error counter

Bits	Field name	rst	Description

Bits	Field name	rst	Description
[3:0]	MAX_ERROR_CNT	0xf	Maximum error count permitted before lighting error led

DEVICE_ID

Name	Address	Access	Reset Value	Description

Name	Address	Access	Reset Value	Description
DEVICE_ID	0x15	Read-write	0x0	FPGA Device ID

Bits	Field name	rst	Description

Bits	Field name	rst	Description
[3:0]	device_id	0x0	FPGA device id

THSENS_CTRL

Name	Address	Access	Reset Value	Description

Name	Address	Access	Reset Value	Description
THSENS_CTRL	0x1a	Read-write	0x0000	JTAG identification code

Bits	Field name	rst	Description

Bits

Field name

rst

Description

[15:6]

thsens_clk_ratio

0x0

Clock ratio between bitstream manager and thermal sensor

Clock frequency is divided by thsens_clk_ratio+2

[5:1]

thsens_dcorrect

0x0

Digital code to correct

[0]

thsens_power_up

0x0

Thermal Sensor is powered

THSENS_DATA

Name	Address	Access	Reset Value	Description

Name	Address	Access	Reset Value	Description
THSENS_DATA	0x1b	Read-only	0x00	Thermal Sensor Data

Bits	Field name	rst	Description

Bits	Field name	rst	Description
[8:2]	thsens_data	0x0	Thermal Sensor Ouput
[1]	thsens_overflow	0x0	Overflow of digital
[0]	thsens_enable	0x0	Thermal Sensor is online

DUMP_CTRL

Name	Address	Access	Reset Value	Description

Name	Address	Access	Reset Value	Description
DUMP_CTRL	0x1c	Read-write	0xf	DUMP configuration

Bits	Field name	rst	Description

Bits	Field name	rst	Description
[3:0]	dump_clk_ratio	0xf	DUMP Clock frequency is divided by dump_clk_ratio+2

SPW_CTRL1

Name	Address	Access	Reset Value	Description

Name	Address	Access	Reset Value	Description
SPW_CTRL1	0x1d	Read-write	0x0000	SPACEWIRE configuration

Bits	Field name	rst	Description

Bits

Field name

rst

Description

[15:8]

spw_freq_run

0x0

frequency used in run state

Clock frequency divided by (spw_freq_run+1)

[7:0]

spw_freq_init

0x0

frequency used in init state

Clock frequency divided by (spw_freq_init+1)

SPW_CTRL2

Name	Address	Access	Reset Value	Description

Name	Address	Access	Reset Value	Description
SPW_CTRL2	0x1e	Read-write	0x1402b	SPACEWIRE configuration

Bits	Field name	rst	Description

Bits

Field name

rst

Description

[17:8]

spw_delay_prg

0x140

delay of 6.4 us

Number of clock cycles needed for 6.4 us

[7:0]

spw_DisCntLim

0x2b

Disconnect time limit (850ns)

Number of clock cycles needed for 850ns

LOADER_CTRL

Name	Address	Access	Reset Value	Description

Name	Address	Access	Reset Value	Description
LOADER_CTRL	0x01	Read-write	0xf	Loader Controller

Bits	Field name	rst	Description

Bits	Field name	rst	Description
[3]	config_force	0x1	Force configuration (force bitstream load)
[2]	ready_force	0x1	Force ready flag
[1]	ready	0x1	Set ready flag when postamble frame occurs
[0]	cmic_enable	0x1	CMIC Feature Enable

Configuration Guide NG-MEDIUM

Table of figures

Table of tables

Important information

Introduction to NG-MEDIUM Configuration

Bitstream size

Configuration Memory Integrity Check (CMIC)

Device configuration details

Purpose of NX1H35AS configuration

NX1H35AS chips configuration modes summary

Multiple devices addressing

Configuration modes usage

Prog bank pins state during and after configuration

User’s I/O pins state during and after configuration

Bitstream loading

NX1H35AS chips prog interface pin list

Detailed configuration modes

SPI Modes

Slave SpaceWire configuration details:

Internal interface between fabric and BSM

Boundary scan

IEEE 1149 JTAG implementation

NX1H35AS chips JTAG instructions

NX1H35AS boundary scan usage

NX1H35AS boundary scan errata

Chip initialization with unused JTAG interface

Dedicated clock inputs in boundary scan INTEST

ANGIE JTAG adaptator

NG_MEDIUM register

STATUS

JTAG_IDCODE

JTAG_USERCODE

SPI_CTRL

ERROR1

ERROR1_MASK

ERROR2

ERROR2_MASK

EVENT_CNT1

EVENT_CNT2

MAX_ERROR_CNT

DEVICE_ID

THSENS_CTRL

THSENS_DATA

DUMP_CTRL

SPW_CTRL1

SPW_CTRL2

LOADER_CTRL