Table of Figures

Hierarchy report providing user modules detection

Unused pattern reported due to incorrect addModule arguments

Output tables from reportInstances() method

Report region

Data and clock delay between a source and destination register

Examples of timing domains D1, D2, D3 in a simple design

Hold/Setup time relationship for active high launch and active high latch clocks

Hold/Setup time relationship for acitve high launch and active low latch clocks

Hold/Setup time relationship for active low launch and active high latch clocks

Hold/Setup time relationship for active low launch and active low latch clocks

Summary.timing example

Example 1 of critical paths table

Example 2 of critical paths table

Example of path detail table

Copyright Notice

All the contents of this document are protected by the copyright law. They may not be disclosed to third parties or copied or duplicated in any form without the written consent of NanoXplore.

Introduction

This document is intended to guide users of NanoXplore Impulse software through all the steps involved in the design flow and the options available in NanoXplore design suite:

• impulse is a graphical interface that allows user to view and compile an existing project.

• nxpython is a wrapper around Python executable that allows user to control impulse software as a wrapper. It fully supports Python syntax, structures and external modules.

• The creation of a new project can be performed with both impulse and nxpython tools.

All commands described in this document for NXpython can be applied to the provided VHDL examples in example folder.

Package Description

The provided impulse archive contains the following directories:

• bin       folder contains binary files for each supported Linux distribution

• doc      folder contains documentation files in pdf format

• example folder contains several examples of different projects with design sources in VHDL

• lib64 folder contains dynamic libraries and Python modules for each supported Linux distribution and associated Python version

• share folder contains additional files (vhdl libraries, simulation libraries, etc...)

Installation

To install impulse, the user needs to unpack nxdesignsuite-VERSION.tar.gz file into the installation directory (e.g. /opt/NanoXplore) using the following command:

To set the license, it is required to export the following shell variable:

Where servername is the hostname of the server running the license daemon and 27000 is the port the daemon listens to.

Run NXPython

To run nxpython, use the following command:

To use the nanoxmap module in python, user must first call the following command in nxpython:

NXPython Specification

Command List and Context

The table below list all available nxpython commands and the context they affect:

General commands

This chapter presents the general purpose commands. These commands do not need any object to be called as they are directly defined in the impulse module.

createProject([workingDirectory])

This method is used to create an empty project object. The project can then be loaded or built.

 Arguments:

When no argument is supplied, the working directory will be the one nxpython is launched from.

 Example:

getErrorCount()

This function returns the number of errors issued during Synthesize, Place and Route flow steps.

This function takes no argument.

Example:

Output:

getRemarkCount()

This function returns the number of remarks issued during Synthesize, Place and Route flow steps.

This function takes no argument.

Example:

Output:

getWarningCount()

This function returns the number of warnings issued during Synthesize, Place and Route flow steps.

This function takes no argument.

Example:

Output:

listOptions()

This method lists all available options for current project.

 This method takes no argument.

Example:

Output:

printError(message)

This function is used to print an error message in the impulse output. This includes terminal output and log file if set. An error message is prefixed by ERROR string so it can be easily found.

When using this method, the global number of errors is incremented by 1.

Arguments:

Example:

Output:

printRemark(message)

This function is used to print a remark message in the impulse output. This includes terminal output and log file if set. An error message is prefixed by REMARK string so it can be easily found.

When using this method, the global number of remarks is incremented by 1.

Arguments:

Example:

Output:

printText([message])

This function is used to print a message in the impulse output. This includes terminal output and log file if set. When no message is given, method prints a new line in the impulse output.

Arguments:

Example:

Output:

printWarning(message)

This function is used to print a warning message in the impulse output. This includes terminal output and log file if set. A warning message is prefixed by WARNING string so it can be easily found.

When using this method, the global number of warnings is incremented by 1.

Arguments:

Example:

Output:

setCoreCount(core_count)

This function sets the number of core to use in multi-thread algorithm.

Minimum value is 1. The tool uses the number of logic cores of the computer as a maximum.

Arguments:

Example:

Output:

setDirAutoChange(change_project_dir)

This function allows to create a user-defined directory to stock the reports created during the execution of the flow.

Arguments:

Example:

setLogDirectory(log_directory)

This function allows to create a user-defined directory to stock the reports created during the execution of the flow.

Arguments:

Example:

Output:

usage()

This method displays application usage.

This method takes no argument.

Example:

Output:

version()

This method displays application version.

This method takes no argument.

Example:

Output:

Expected expressions for NXpython methods

NxPython methods get a standardized format for arguments expecting a path.

This section describes the expression format specific to NX.

Impacted methods:

The following methods allow regular expressions / wildcard formats in order to match with multiple instances:

·       addDSPLocation

·       addModule

·       addRAMLocation

·       constrainPath

·       getInstances

·       getModels

·       getRegisters

·       setSite

·       …

Maintainability:

It is no longer necessary to escape (with the ‘\’ character) special characters for these methods.

Affected special characters are:

·       ‘[‘

·       ‘]’

·       ‘(‘

·       ‘)’

·       ‘|’

For instance, the constraint:

addModule('timing_pipe\(X2A98C8C6\)', 'GEN_HIER0.GEN_COL[0].COL_PIPE', 'GEN_HIER0_COL-%')

can be replaced by:

addModule('timing_pipe(X2A98C8C6)', 'GEN_HIER0.GEN_COL[0].COL_PIPE', 'GEN_HIER0_COL-%')

However, the old format is still compliant and still operates.

User use:

In a usual way, a copy/paste of a path from a log file works for the constraint.

In addition, it is comfortable to use ‘*’ and ‘+’ characters to match several paths.

‘*’ matches with any character: can be very useful to match with all paths beginning with a specified path.

‘+’ matches with any character but ‘|’: can be very useful to match with all paths beginning with a specified path without matching with lower hierarchy levels.

Hereafter an example with existing paths and constraints:

Note:

If the user needs to use regular expressions ignoring auto-escaping of special characters, it is possible to set the constraint using back quotes as follow:

addMappingDirective(getModels(“add_`[1-2][0-9]`u_*”), …)

Project related methods

This section presents the methods related to the project object.

addBank(name, dict)

The method addBank allows user to configure a specific bank of the FPGA. The pads inside the defined bank will be used first to configure inputs/outputs of the HDL module. For the given bank, the configuration has two basic arguments name and dict.

Arguments:

dict is a dictionary which can take the following keys:

The voltage must be one of the following values:

• 1.5

• 1.8

• 2.5

• 3.3

Example:

addBanks(dict)

The method addBanks allows user to configure several banks of the FPGA to be used for configuration of inputs/outputs of the HDL module. addBanks use a dictionary as an argument.

Arguments:

Example:

addBlackBox(name, type, mapping, interface)

The method addBlackBox allows users to define customized mapping of certain HDL modules on the specific FPGA blocks and to dispose the interface of the blocks.

Arguments:

The type argument can only be overridden for specific object types. The available types are:

For each type, there are some specific instances in the FPGA onto which it can be mapped. This can be specified using mapping argument. The following table presents all the available mapping targets for each type:

The argument interface argument specifies the interface mapping between the HDL module and nxpython.

When setting ROM value for type argument, the nxpython interface is:

When setting RAM value for type argument, the nxpython interface depends on the mode RAM is being used in:

• RAM mode: Simple port

• RAM mode: Split read/write port (1 port for read and 1 port for write)

• RAM mode: True dual port (2 ports for read/write)

First port:

Second port:

Example:

If the HDL design contains a micro code ROM define in VHDL as:

User can add a black box to force nxpython to recognize this module as a ROM.

addBlackBox() : for Preplaced IP

The idea is to offer the possibility to the user to reuse the result of an impulse flow as an IP in a top design.

For instance, the user will work on a design named IP with the desired performance.

Open

Preplaced IP for addBlackBox()

The user can then reuse the result of this first flow in another design. named top, which instanciates the IP entity several times.

Impulse will use the result of synthesis and place from the first flow and replicate then in the top flow

Open

Replication of synthesized IP

To specify that an entity of the design top must be taken into account as a preplaced IP, the user has to add the following constraint before the synthesis

• The first argument is the name of the VHDL entity

• The second argument must be ‘IP’

• The third argument is the .nym Preplace results of the IP

• The fourth argument is a string character which lists for each instanciation of the entity, the name of the instance followed by : and the region of the IP in fortmat (col x row). Instanciations are separated by the character ;

Limitations :

This functionality has some important limitations :

Variant

The variant on which the IP design is prepared must be strictly identical to the variant used for the design. For example, NG-MEDIUM in both cases.

Aperture

It is necessary that the IP design is placed/routed using minimal aperture.

addBlackBox

The method addBlackBox should be called only once by an entity in the top design.
For instance, it is not allowed to use the following lines :

Fabric instances

Among the instances of the ring, some are not supported yet :
CDC, CKS, FIFO, XFIFO

Ring instances

Among the instances of the ring, some are not supported yet :
PLL, WFG, CR5, SOC_IF, HSSL

addDSPLocation(pattern, place)

This method is used to select the spot in which a DSP should be placed before launching Place step execution.

Arguments:

DSP must be placed into CGB elements. As each CGB contains two DSP macros, user has to specify for place argument either to use the left DSP (L) or the right DSP (R) into the CGB. 

Wildcard symbol is accepted for pattern argument.

Example:

addFalsePath(from_list, to_list)

This method is used to specify the false path for the timing paths. This constraint is used by timing driver algorithms and static timing analysis.

Arguments:

Example:

addFile([library], file)

This method is used to add a HDL source file to the project. The file can be added to a specific library by passing its name as the first optional library argument. The default library is work.

Arguments:

Example:

addFiles([library], fileList)

This method is used to add several HDL source files to the project. The files can be added to a specific library by passing its name as the first optional library argument. The default library is work.

Arguments:

Example:

addHSSLLocation(pattern,location)

This method is used to set the spot in which a HSSL should be set.

Placement of HSSL elements can also be done during instantiation (with location generic in source code).add

Arguments:

Example:

addMappingDirective(name, type, mapping)

This method is used to add a mapping directive for Synthesis flow step which overrides the default nxpython mapping behavior for a specific HDL module or instance.

Arguments:

The name argument can be a regular expression matching a HDL module or instance name. In order to specify whether to search for module or instance, the user has to use the getModels(...) or getInstances(...) keyword.

The type argument can only be overridden for specific object types. For each type, there are some specific instances in the FPGA onto which it can be mapped. This can be specified using mapping argument. The following table presents all the available mapping targets for each type:

Example:

If the HDL design named myTest contains a small 3 write ports and 3 read ports FIFO named myFifo, nxpython cannot automatically map it into RF or RAM, but user can add a mapping directive to map it into DFF:

addMaxDelayPath(from_list, to_list, delay)

This method is used to specify the maximum delay path for the timing paths. It is used by timing driver algorithms and static timing analysis.

Arguments:

Example:

addMemoryInitialization(name, type, file)

This method is used to specify a file that will be used to initialize a specific memory instance.
Arguments:

The name argument can be a regular expression matching a HDL module or instance name. In order to specify whether to search for module or instance, the user has to use the getModels(...) or getInstances(...) keyword.

The available file formats are:

The NX File format is a simple format in which initialization bits are written in ASCII. Each line of the file represents one vector in the memory. NULL MSBs and empty (only 0's) lines at the end of the file are NOT mandatory.

Example:

To initialize a memory called IMG_1' in a design called 'test_init' using data from a file called "initdata.nx", call:

If you declare a memory array 'array(0 to 5) of std_logic_vector(0 to 3)' and want to load an identity matrix, the file should contain:

Since it is not mandatory to initialize:

• the end of the array if it contains only zeros

MSBs if they are null

The previous example can be written this way:

addMinDelayPath(from_list, to_list, delay)

This method is used to specify the minimum delay path for the timing paths. It is used by timing driver algorithms and static timing analysis.

Arguments:

Example:

addModule(model, instance, format)

This method is used to add a HDL module definition to the current project that contains all HDL logic elements including within the model given in argument.

Arguments:

Example:

Open

Hierarchy report providing user modules detection

nxpython reports user modules detection in the hierarchy.rpt (previous figure) file with detailed information including resources used for each module and detailed hierarchy of all modules defined in the current project.

hierarchy.rpt also allows to check if pattern expression provided for model and instance arguments have been fully accepted by nxpython tool. User can use the wildcard operator '*'. See full details with an example.

Example:

addMulticyclePath(from_list, to_list, cycle_count)

This method is used to specify the multicycle path for the timing paths. It is used by timing driver algorithms and static timing analysis.

Arguments:

Example:

addPad(name, parameters)

This method allows user to configure an input/output of the HDL module into specific pad of the FPGA. For the given pad, the configuration has two basic argument (name and parameters).

Arguments:

The parameters argument is a dictionary which can take the following keys:

The standard key must respect the following values:

• LVCMOS (Default)

• LVDS

• LVDS_STR

• SSTL

• HSTL

LVDS is the nominal LVDS standard. LVDS_STR is a strong LVDS with higher voltage (ex : 550mVpp LVDS vs 900mVpp LVDS_STR for NG-LARGE variant).

The I/O differential (Default False) activation is conditioned depending on standard:

In case of differential mode, the user must only declare the “_P” pad. The associated differential “_N” pad will be automatically set by the software with the same parameters.

The drive key must respect the following values:

• 2mA (only allowed for LVCMOS standard - Default for LVCMOS standard)

• 4mA (only allowed for LVCMOS standard)

• 8mA (only allowed for LVCMOS standard)

• 12mA (only allowed for LVCMOS standard)

• 16mA (only allowed for LVCMOS standard)

• I (only allowed for SSTL and HSTL standard - Default for SSTL and HSTL standard)

• II (only allowed for SSTL and HSTL standard)

• Undefined (only allowed for LVDS standard - Default for LVDS standard)

As an example for NG-Large variant, the following array gives a trade-off between the maximum frequency reachable and noise limitation plus power consumption:

The weakTermination key must respect the following values:

• None

• PullDown

• PullUp (Default)

• Keeper

The slewRate key must respect the following values:

• Slow

• Medium (Default)

• Fast

The termination key specifies the output impedance of the pad in Ohms. In differential mode, the impedance is two times the value. It’s specified in Ohms, (Default is set to minimum value).

Min and max values depend on the variant and the bank voltage.

The inputDelayLine and outputDelayLine keys should be between 0 (Default) and 63. This number correspond to a number of step. Values are applied only if inputDelayOn and outputDelayOn are set to True.

The terminationReference key is used only if termination is set (Default '-'). It must respect the following criteria to be set to ‘Floating’ value otherwise it should always be defined as ‘VT’.

Unit of inputSignalSlope key is V/ns in the range [0.5;20] (Default 0).

Unit of ouputCapacity key is pF in the range [0;40] (Default 0).

When set to ‘True”, the turbo key (Default False) specifies that the input buffer of the pad is in turbo mode. As an example for NG-Large variant, the following array gives a trade-off between the maximum frequency reachable and power consumption:

The registered key (Default '') allows user to merge registers into Input/Output pads. This key can take the following values:

When a key is not in the dictionary, its value is set to default, i.e. 0 for inputDelayLine/outputDelayLine/signalSlope/outputCapacity and False for all the boolean arguments.

Example:

Example:

addPads(pads)

This method is used to configure inputs/outputs of the HDL module into specific pads of the FPGA. The argument is a dictionary that associates the HDL input/output name to a dictionary, which can contain some keys (location, type, weakTermination, slewRate, termination, inputDelayLine, outputDelayLine, differential, terminationReference, turbo) as defined in addPad(name, parameters).

Arguments:

Example:

Example:

addPin(name, location)

This method allow user to configure an input/output of the HDL module into specific pin of the embedded FPGA. This method is reserved to embedded variants of FPGA.

Arguments

Example:

addPins(pins)

This method allow user to configure inputs/outputs of the HDL module into specific pins of the embedded FPGA. This method is reserved to embedded variants of FPGA.

Arguments:

Example:

addParameter(name, value)

This method allows user to specify the value of the top design generic parameters.

Arguments:

Example:

addParameters(parameters)

In case of a large number of parameters, a parameter dictionary can be created consisting of the name of the parameter as a key and its respective value. Both name and value must be string.

Arguments:

Example:

addPLLLocation(pattern, location)

This method is used to set the spot in which a PLL should be set.

Placement of PLL elements can also be done during instantiation (with location generic in source code).

Arguments:

Example:

addRAMLocation(pattern, place)

This method is used to select the spot in which a RAM should be placed. This method must be used and declared before launching Place step execution.

Arguments:

RAM must be placed into selected CGB element with place argument.

Wildcard symbol is accepted for pattern argument.

Example:

addRingLocation(name, location)

This method is used to place an instance in the I/O ring of the FPGA. addRingLocation can be used instead of addPLLLocation, addWFGLocation or addPin.

Example:

Example:

addRingLocations(dictionary)

In case of a large number of instances to be placed in the I/O Ring, a dictionary can be created consisting in the name of the instance as a key and its association location. Both name and location must be string.

Arguments:

Example:

addVerilogIncludeDirectory(directory)

This method is used to add an extra directory containing Verilog files to the project. This is used when the included files are external to the working directory.

Arguments:

Example:

addVerilogIncludeDirectories(directoryList)

This method is used to add several extra directories containing Verilog files to the project. This is used when the included files are external to the working directory.

Arguments:

Example:

addVlogDefine(name,value)

This method is used to add a parameter definition for Verilog files.

Arguments:

Example:

addVlogDefines(dictionnary)

This method is used to add parameters definition for Verilog files.

Arguments:

Example:

addWFGLocation(name, location)

This method is used to set the spot in which a WFG should be set.

Placement of WFG elements can also be done during instantiation (with location generic in source code).

Arguments:

Valid locations depend on the variant: