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Creates a clock and defines its waveform.
create_clock [-add]
...
name clock_name]
[-period float]
[-waveform <edge_list>]
...
Arguments:
Name | Description | -add | Allows to specify multiple clocks on the same source for simultaneous analysis with different clock waveforms. Not supported by Nxmap|
-name | Specifies the name of the clock. | ||
-period | Specifies the length of the clock period. | ||
-waveform | Specifies the rise and fall edge times of the clock waveform over one clock period. The first value corresponds to the first rising transition after time zero. The numbers should represent one full clock period. | ||
source | The query which specifies how to get a clock related point. A valid query can be: | ||
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Examples:
The following example creates two clocks on ports clk1 and clk2 with a period of 8, a rising edge at 0, and a falling edge at 4:
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Creates a new clock signal from the clock waveform of a given pin in the design.
create_generated_clock [-add]
...
_clock
...
[-divide_by integer]
[-duty_cycle float]
[-edge_shift float list]
...
Arguments:
Name | Description | ||
-add | Allows to specify multiple clocks on the same source for simultaneous analysis with different clock waveforms. Not supported by NXmap | ||
-master_clock | Derives the generated (target) clock from the specified clock. Must be used with | ||
-divide_by | Determines the frequency of the new clock by dividing the frequency of the source clock by this factor. The value must be greater or equal to 1. Default value is 1 | ||
-duty_cycle | Specifies the duty cycle (high pulse width) as a percentage of the clock period. The range must be between 1 and 99. Default value is 50.0 | ||
-edge_shift | Specifies how much each edge specified with the | ||
-edges | Selects a list of edges from the source clock that form the edges of the derived clock. You must specify an odd number of edges. The last edge represents the first edge of the next clock period.
| ||
-invert | Inverts the resulting waveform of the generated clock. | ||
-multiply_by | Determines the frequency of the new clock by multiplying the frequency of the source clock with this factor. The value must be greater or equal to 1. Default value is 1 | ||
-name | Specifies the name of the generated clock. | ||
-offset | Specifies the offset for the rising edge. | ||
-phase | Specifies the phase of the generated clock. The range must be from 0 to 359 | ||
-source | Specifies the name of the pin from which the clock must be derived. A valid argument can be: | ||
target | Specifies how to get a clock related point. A valid argument can be: | ||
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Examples:
The following example creates a generated clock on pin register_1 with a period twice as long as the period at the reference port clock
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| Code Block |
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create_generated_clock –divide_by 3 –multiply_by 4 -source [get_ports {clock}] [get_nets {ck}] |
set_clock_groups
Specifies the groups of clocks between which timing analysis will not be done.
set_clock_groups [-asynchronous]
[-exclusive]
[-group]
Arguments:
Name | Description |
asynchronous | Defines clock group with asynchronous clocks. Asynchronous clocks have no specified phase relationship. |
exclusive | Defines clock group with clocks that cannot exist in the design at the same time. |
group | Specifies a group of clocks. |
Examples:
| Code Block |
|---|
create_clock -period 10 -name "clk1" [get_ports clk_1]
create_clock -period 12 -name "clk2" [get_ports clk_2]
create_clock -period 15 -name "clk3" [get_ports clk_3]
set_clock_groups -asynchronous -group [get_clocks clk1] -group [get_clocks clk2]
set_clock_groups -exclusive -group [get_clocks clk1] -group [get_clocks clk3] |
set_false_path
Identifies false paths in a design, and breaks or disables specific instance timing arcs in a design resulting in them not being timed.
set_false_path [-from source_name]
[-to target_name]
[-group]
Arguments:
Name | Description | ||
|---|---|---|---|
from | Specifies how to get a timing path starting points. A valid timing starting point is an input port or a register. A valid argument can be: | ||
to | Specifies how to get a timing path ending points. A valid timing ending point is an output port or a register. A valid argument can be: | ||
group | Specifies a group of clocks. Specify at least two clocks. | ||
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-from and -to options apply the constraint to both the rising and falling edges
Examples:
| Code Block |
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set_fase_path -from [get_ports cpt_in*] -to [get_clocks clk2] |