This document aims to list all the the nxpython methods available to apply timing constraints on a design
addFalsePath(from_list, to_list)
/ ! \ DEPRECATED / ! \ Please use setFalsePath instead, with the same key arguments
This method is used to specify the false path for the timing paths. This constraint is used by timing driven algorithms and static timing analysis.
Arguments:
Name | Type | Description |
from_list | string | the command which specifies how to get a timing path starting points. A valid timing starting point is an input port or a register. A valid command can be: getPort(port_name), getPorts(name_expression), getRegister(register_name), getRegisters(name_expression), getRegistersByClock(clock_name) |
to_list | string | the command which specifies how to get a timing path ending points. A valid timing ending point is an output port or a register. A valid command can be: getPort(port_name), getPorts(name_expression), getRegister(register_name), getRegisters(name_expression), getRegistersByClock(clock_name) |
Example:
project = createProject()
project.load('routed.nym')
project.addFalsePath('getRegister('UUT1|Gen_seq[3].seq_i|temp_reg[1]')','getRegister('UUT2|dout_reg[61]')')
project.addFalsePath('getRegistersByClock(clk1)','getRegistersByClock(clk2)')
project.addFalsePath('getRegister(cpt_in_p_reg[0])','')
project.addFalsePath('getPort(cpt_in[0])','getRegisters("cpt_in_p_reg[`[0-3]`]")')
project.addFalsePath('getPorts("cpt_in[`[0-3]`]")', 'getRegistersByClock(clk2)')
project.addFalsePath('getRegistersByClock(clk1)', 'getWFGOutput(i_WFG_0)')
In order to match with all registers, it is possible to specify empty string ('') for parameters from_list or to_list.
addMaxDelayPath(from_list, to_list, delay)
/ ! \ DEPRECATED / ! \ Please use setMaxDelay instead, with the same key arguments
This method is used to specify the maximum delay path for the timing paths. It is used by timing driven algorithms and static timing analysis.
Arguments:
Name | Type | Description |
from_list | string | the command which specifies how to get a timing path starting points. A valid timing starting point can be either an input port or a register. A valid command can be: getPort(port_name), getPorts(name_expression), |
to_list | string | the command which specifies how to get a timing path ending points. A valid timing ending point can be either an output port or a register. A valid command can be: getPort(port_name), getPorts(name_expression), |
delay | float | the required maximum delay value in ns for specified paths. |
Example:
project = createProject()
project.load('routed.nym')
project.addMaxDelayPath('getRegister('UUT1|Gen_seq[3].seq_i|temp_reg[1]')', 'getRegister('UUT2|dout_reg[61]')', 3.9)
project.addMaxDelayPath('getPort(cpt_in[0])', 'getRegister(i_cpt_1|s_cpt_out_reg[1])', 8.0)
project.addMaxDelayPath('getRegister(i_cpt_0|s_cpt_out_reg[0])','getRegister(i_cpt_1|s_cpt_out_reg[1])', 4.0)
project.addMaxDelayPath('getPorts("cpt_in[`[1-3]`]")','getRegister(i_cpt_1|s_cpt_out_reg[1])', 8.0)
project.addMaxDelayPath('getRegisters("i_cpt_0\|s_cpt_out_reg[`[1-3]`]")', 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', 8.0)
addMinDelayPath(from_list, to_list, delay)
/ ! \ DEPRECATED / ! \ Please use setMinDelay instead, with the same key arguments.
This method is used to specify the minimum delay path for the timing paths. It is used by timing driven algorithms and static timing analysis.
Arguments:
Name | Type | Description |
from_list | string | the command which specifies how to get a timing path starting points. A valid timing starting point can be either an input port or a register. A valid command can be: getPort(port_name), getPorts(name_expression), |
to_list | string | the command which specifies how to get a timing path ending points. A valid timing ending point can be either an output port or a register. A valid command can be: getPort(port_name), getPorts(name_expression), |
delay | float | the required minimum delay value in ns for specified paths. |
Example:
project = createProject()
project.load('routed.nym')
project.addMinDelayPath(getRegister('UUT1|Gen_seq[3].seq_i|temp_reg[23]'), getRegister('UUT1|Gen_seq[3].seq_i|temp_reg[22]'), 1.2)
project.addMinDelayPath(getPort(cpt_in[0]), getRegister(i_cpt_1|s_cpt_out_reg[1]), 8.0)
project.addMinDelayPath(getRegister(i_cpt_0|s_cpt_out_reg[0]), getRegister(i_cpt_1|s_cpt_out_reg[1]), 8.0)
project.addMinDelayPath(getPorts("cpt_in[`[1-3]`]"), getRegister(i_cpt_1|s_cpt_out_reg[1]), 8.0)
project.addMinDelayPath(getRegisters("i_cpt_0\|s_cpt_out_reg[`[1-3]`]"), getRegister(i_cpt_1\|s_cpt_out_reg[1]), 8.0)
addMulticyclePath(from_list, to_list, cycle_count)
/ ! \ DEPRECATED / ! \ Please use setMulticyclePath instead, with the same key arguments.
This method is used to specify the multicycle path for the timing paths. It is used by timing driven algorithms and static timing analysis.
Arguments:
Name | Type | Description |
from_list | string | the command which specifies how to get a timing path starting points. A valid timing starting point can be either an input port or a register. A valid command can be: getPort(port_name), getPorts(name_expression), |
to_list | string | the command which specifies how to get a timing path ending points. A valid timing ending point can be either an output port or a register. A valid command can be: getPort(port_name), getPorts(name_expression), |
cycle_count | unsigned | An unsigned value that represents a number of cycles the data path must have for setup check. |
Example:
project = createProject()
project.load('routed.nym')
project.addMulticyclePath('getRegister('UUT1|Gen_seq[3].seq_i|temp_reg[1]')', 'getRegister('UUT2|dout_reg[61]')', 2)
project.addMulticyclePath('getRegisters("i_cpt_0\|s_cpt_out_reg[`[1-3]`]")', 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', 2)
createClock( )
This method is used to create a clock constraint at a timing point. This constraint is used by timing driven algorithms and static timing analysis. Depending on the unit defined in the project, timings are in ns or ps.
Signatures:
createClock(target, name, period)
createClock(target, name, period, rising)
createClock(target, name, period, rising, falling)
Arguments:
Name | Type | Description |
target | string | the query which specifies how to get a clock related point. A valid query can be: getPort(port_name), getRegisterClock(register_name) or getRegister(register_name), getClockNet(clock_net_name). |
name | string | user clock name of the created clock. |
period | float | the period value. |
rising | float | specific rising edge for clock waveform. Range [0, period[ (the default value is 0) |
falling | float | specific falling edge for clock waveform. Range ]rising, rising + period] (default value is period/2) |
The name of the clock net is case sensitive
Example:
In the example above, to define a 100MHz clock for net “Clk”, the following three commands are equivalent :
project = createProject()
project.load('routed.nym')
project.createClock('getRegisterClock(reg1)', 'clk', 10)
or
project.createClock('getPort(Clk)', 'clk', 10)
or
project.createClock('getClockNet(Clk)', 'clk', 10, 0, 5)
createClock( target = ‘target', name = ‘name’, period = ]0, ], rising = [0,period[, falling = ]rising, rising+period] )
This method is used to create a clock constraint at a timing point. This constraint is used by timing driven algorithms and static timing analysis. Depending on the unit defined in the project, timings are in ns or ps.
Arguments:
Name | Type | Description |
target | string | Mandatory. The query which specifies how to get a clock related point. A valid query can be: getPort(port_name), getRegisterClock(register_name) or getRegister(register_name), getClockNet(clock_net_name). |
name | string | Optional. User clock name of the created clock, default name is target_str |
period | float | Mandatory. Period for the clock waveform. Must be positive, default value is period/2 |
rising | float | Mandatory if falling is defined. Otherwise, it is optional. Rising edge for the clock waveform. The range is defined as [0, period[ The default value is 0. |
falling | float | Optional. Falling edge for the clock waveform. The range is defined as ]rising, rising + period]. The default value is period/2. |
Example:
In the example above, to define a 100MHz clock for net “Clk”, the following three commands are equivalent :
project = createProject()
project.load('routed.nym')
project.createClock(target = 'getRegisterClock(reg1)', name = 'Clk', period = 10)
or
project.createClock(target = 'getPort(Clk)', name = 'Clk', period = 10)
or
project.createClock(target = 'getClockNet(Clk)', name = 'Clk', period = 10, rising = 0, falling = 5)
createGeneratedClock(source, target, name, relationship)
This method is used to create an internal generated clock constraint at a timing point. This constraint is used by timing driven algorithms and static timing analysis.
Arguments:
Name | Type | Description |
source | string | The command which specifies how to get a source clock related point. A valid command can be: getClock(), getPort(port_name), getRegisterClock(register_name), getRegister(register_name), getClockNet(clock_net_name), getWFGOutput(wfg_name) |
target | string | The command which specifies how to get a clock related point. A valid command can be: getRegisterClock(register_name), getRegister(register_name)), getClockNet(clock_net_name) |
name | string | User clock name of the generated clock |
relationship | dictionary | The relationship for computing clock wave of the generated clock from the master clock. All valid parameter can be: MultiplyBy : unsigned DivideBy : unsigned DutyCycle : unsigned (1 to 99) Phase : unsigned (0 to 359) Offset : integer (delay in ns) Edges : list [unsigned, unsigned, unsigned] (in non-decreasing order) EdgeShift : list [integer, integer, integer] (delay in ns) |
Frequency-based and edge-based relationships are mutually exclusive.
Example:
In the example above, the master clock "Clk" was created as 100MHz and the generated clock "clk1" is divided by 2 from the master clock. But note that the "clk_reg" is driven by the falling edge of master clock, the relation between the master clock and the generated clock is shown in the diagram below:
project = createProject()
project.load('routed.nym')
project.createClock(getPort('Clk'), 'Clk', 10)
project.createGeneratedClock('getRegisterClock(clk_reg)', 'getRegisterClock(reg2)', 'clk1', {'DivideBy': 2})
or
project.createGeneratedClock('getClock(Clk)', 'getRegisterClock(reg2)', 'clk1', {'Edges': [2, 4, 6]})
The following script is incorrect in this case:
########### INCORRECT SCRIPT ##########
project.createGeneratedClock(getClock('Clk'),getRegisterClock('reg2'), 'clk1', {'DivideBy': 2})
The diagram of the above command would be:
