$ make pll_calculator_interface
pll_calculator_interface
Please set the variant ?
 1 - NG-MEDIUM 
 2 - NG-LARGE 
 3 - NG-ULTRA 
3
How the reference clock is generated ?
 1 - External 
 2 - Internal (internal oscillator)
1
What is the reference clock frequency in MHz ?
50
Do you want to set a VCO frequency or let the tool research automatically ?
 1 - Set VCO frequency 
 2 - Automatical research with 1st output clk
2
How many output clocks do you want to generate in the range [0;9] ?
2
What is the frequency of the output clock 0 in MHz ?
400
What is the frequency of the output clock 1 in MHz ?
200

//////////PLL setting//////////
|Signal |Frequency (MHz)|
|------ |-------------- |
|Ref    |50.0           |
|Ref_int|50.0           |
|VCO    |800.0          |
|------ |-------------- |
|DIVD5  |400.0          |
|DIVD4  |200.0          |

//////////PLL parameters//////////
ref_osc_on       => '0'                                             ,
ref_intdiv       => 0                                               ,
fbk_int_div      => 7                                               ,
clk_outdiv1      => to_bitvector(conv_std_logic_vector(0,3))        ,
clk_outdiv2      => to_bitvector(conv_std_logic_vector(0,3))        ,
clk_outdiv3      => to_bitvector(conv_std_logic_vector(0,3))        ,
clk_outdiv4      => to_bitvector(conv_std_logic_vector(0,3))        ,
clk_outdivd1     => to_bitvector(conv_std_logic_vector(0,4))        ,
clk_outdivd2     => to_bitvector(conv_std_logic_vector(0,4))        ,
clk_outdivd3     => to_bitvector(conv_std_logic_vector(0,4))        ,
clk_outdivd4     => to_bitvector(conv_std_logic_vector(1,4))        ,
clk_outdivd5     => to_bitvector(conv_std_logic_vector(0,4))        

$ make wfg_calculator_interface
wfg_calculator_interface
What is the input clock frequency in MHz ?
100
What is the output clock frequency in MHz. It has to be input clock frequency divided by power of 2 in the range [6.25;100.0]?
25
For how many input clock cycles do you want to shift output clock in the range [0;2] ?
1
On which edge of input clock do you want to generate output clock ?
 1 - Rising edge 
 2 - Falling edge
1

//////////WFG parameters//////////
mode             => '1'                                             ,
wfg_edge         => '1'                                             ,
pattern          => "0110011001100110"                              ,
pattern_end      => 15   

$ make constrain_modules HIERARCHY_FILE=~/fae/tool/tool/hierarchy.rpt HIERARCHY_LEVEL_MAX=2 EXCLUSIVE=False
constrain_modules HIERARCHY_FILE=/home/users/kchopier/fae/tool/tool/hierarchy.rpt HIERARCHY_LEVEL_MAX=2 EXCLUSIVE=False

#New sub-module
p.addModule('RAM(X6AAF88E9)','g_loop_depth4[0].i_RAM_example','RAM(X6AAF88E9)_MOD0-%')
#New sub-module
p.addModule('RAM(X6AAF88E9)','g_loop_depth4[1].i_RAM_example','RAM(X6AAF88E9)_MOD1-%')
#New sub-module
p.addModule('RAM(X5A5D25DC)','g_loop_depth8[0].i_RAM_example','RAM(X5A5D25DC)_MOD0-%')
#New sub-module
p.addModule('RAM(X5A5D25DC)','g_loop_depth8[1].i_RAM_example','RAM(X5A5D25DC)_MOD1-%')

p.createRegion('RAM(X6AAF88E9)_REG0',,,,,False)
p.createRegion('RAM(X6AAF88E9)_REG1',,,,,False)
p.createRegion('RAM(X5A5D25DC)_REG0',,,,,False)
p.createRegion('RAM(X5A5D25DC)_REG1',,,,,False)

p.confineModule('RAM(X6AAF88E9)_MOD0-0','RAM(X6AAF88E9)_REG0')
p.confineModule('RAM(X6AAF88E9)_MOD1-0','RAM(X6AAF88E9)_REG1')
p.confineModule('RAM(X5A5D25DC)_MOD0-0','RAM(X5A5D25DC)_REG0')
p.confineModule('RAM(X5A5D25DC)_MOD1-0','RAM(X5A5D25DC)_REG1')