{"type":"doc","content":[{"type":"extension","attrs":{"layout":"default","extensionType":"com.atlassian.confluence.macro.core","extensionKey":"toc","parameters":{"macroParams":{"minLevel":{"value":"1"},"maxLevel":{"value":"7"}},"macroMetadata":{"macroId":{"value":"e09ae8ceb6bced12e4fda23749ee98d1"},"schemaVersion":{"value":"1"},"title":"Table of Contents"}},"localId":"1b5addb0-d730-4b83-9857-1378b31763a3"}},{"type":"heading","attrs":{"level":1},"content":[{"text":"Copyright","type":"text"}]},{"type":"paragraph","content":[{"text":"All the contents of this document are protected by the copyright law. They may not be disclosed to third parties or copied or duplicated in any form without consent of NanoXplore.","type":"text"}]},{"type":"heading","attrs":{"level":1},"content":[{"text":"Introduction","type":"text"}]},{"type":"heading","attrs":{"level":2},"content":[{"text":"Aim of document","type":"text"}]},{"type":"paragraph","content":[{"text":"This document is intended to guide users on Impulse software best practice.","type":"text"}]},{"type":"paragraph","content":[{"text":"The aim is to ease Impulse using and get the best recommendations in order to implement a project into NanoXplore components.","type":"text"}]},{"type":"paragraph","content":[{"text":"For any assistance, please contact NanoXplore support team at ","type":"text"},{"text":"support@nanoxplore.com","type":"text","marks":[{"type":"link","attrs":{"href":"mailto:support@nanoxplore.com"}}]},{"text":".","type":"text"}]},{"type":"heading","attrs":{"level":2},"content":[{"text":"Content","type":"text"}]},{"type":"paragraph","content":[{"text":"All recommendations are divided in several categories depending on product development phase.","type":"text"}]},{"type":"paragraph","content":[{"text":"They are based mainly on NXpython methods but some of them can be applied in the GUI.","type":"text"}]},{"type":"heading","attrs":{"level":1},"content":[{"text":" Design","type":"text"}]},{"type":"heading","attrs":{"level":2},"content":[{"text":"NanoXplore primitive instantiation","type":"text"}]},{"type":"paragraph","content":[{"text":"All NanoXplore primitives are listed in ","type":"text"},{"text":"nxLibrary-.vhdp","type":"text","marks":[{"type":"em"}]},{"text":" available in the release archive. A documentation is also available in order to get information about all generics and io in ","type":"text"},{"type":"inlineCard","attrs":{"url":"https://nanoxplore-wiki.atlassian.net/wiki/spaces/NAN/pages/357467638"}},{"text":" .","type":"text"}]},{"type":"panel","attrs":{"panelType":"note"},"content":[{"type":"paragraph","content":[{"text":"It is recommended to only add the nxpackage in the work library and not component declarations as they are already declared in the package.","type":"text"}]}]},{"type":"heading","attrs":{"level":2},"content":[{"text":"Net Network","type":"text"}]},{"type":"paragraph","content":[{"text":"Basically, there are 2 kind of net networks in NX chips :","type":"text"}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Common: Used to connect data like signal, most of the time signals with a low fanout","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"System: Used to connect clock/reset signal, most of the time signals with a high fanout. This network is composed of 2 sub categories:","type":"text"}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Global low-skew network is used to spread signals through the whole fabric with a low skew between all paths","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Local low-skew network is used to spread signals through a TILE with a low skew between all paths","type":"text"}]}]}]}]}]},{"type":"paragraph","content":[{"text":" ","type":"text"}]},{"type":"paragraph","content":[{"text":"There are instances to go from one world to the other one :","type":"text"}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"CSC: Common to System Converter","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"SCC : System to Common Converter","type":"text"}]}]}]},{"type":"paragraph","content":[{"text":"Depending on the chip, CSC are implemented in different kinds of primitives.","type":"text"}]},{"type":"paragraph","content":[{"text":" ","type":"text"}]},{"type":"paragraph","content":[{"text":"Each instance in the design has:","type":"text"}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Pins with net coming from the Common network OR/AND","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Pins with net coming from the System network OR/AND","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Pins with net coming from either Common network or System network","type":"text"}]}]}]},{"type":"paragraph","content":[{"text":"For example, a NX_DFF has the following pins and associated connected networks:","type":"text"}]},{"type":"table","attrs":{"layout":"default","width":760.0,"localId":"3119aad2-5e57-44bc-8da0-f3de27a93168"},"content":[{"type":"tableRow","content":[{"type":"tableCell","attrs":{"colspan":1,"rowspan":1},"content":[{"type":"paragraph","content":[{"text":"Pin","type":"text","marks":[{"type":"strong"}]}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1},"content":[{"type":"paragraph","content":[{"text":"Common","type":"text","marks":[{"type":"strong"}]}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1},"content":[{"type":"paragraph","content":[{"text":"System","type":"text","marks":[{"type":"strong"}]}]}]}]},{"type":"tableRow","content":[{"type":"tableCell","attrs":{"colspan":1,"rowspan":1},"content":[{"type":"paragraph","content":[{"text":"CK","type":"text","marks":[{"type":"strong"}]}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1},"content":[{"type":"paragraph","content":[{"text":"No","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1},"content":[{"type":"paragraph","content":[{"text":"Yes","type":"text"}]}]}]},{"type":"tableRow","content":[{"type":"tableCell","attrs":{"colspan":1,"rowspan":1},"content":[{"type":"paragraph","content":[{"text":"R","type":"text","marks":[{"type":"strong"}]}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1},"content":[{"type":"paragraph","content":[{"text":"Yes","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1},"content":[{"type":"paragraph","content":[{"text":"Yes","type":"text"}]}]}]},{"type":"tableRow","content":[{"type":"tableCell","attrs":{"colspan":1,"rowspan":1},"content":[{"type":"paragraph","content":[{"text":"L","type":"text","marks":[{"type":"strong"}]}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1},"content":[{"type":"paragraph","content":[{"text":"Yes","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1},"content":[{"type":"paragraph","content":[{"text":"Yes","type":"text"}]}]}]},{"type":"tableRow","content":[{"type":"tableCell","attrs":{"colspan":1,"rowspan":1},"content":[{"type":"paragraph","content":[{"text":"D","type":"text","marks":[{"type":"strong"}]}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1},"content":[{"type":"paragraph","content":[{"text":"Yes","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1},"content":[{"type":"paragraph","content":[{"text":"No","type":"text"}]}]}]},{"type":"tableRow","content":[{"type":"tableCell","attrs":{"colspan":1,"rowspan":1},"content":[{"type":"paragraph","content":[{"text":"Q","type":"text","marks":[{"type":"strong"}]}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1},"content":[{"type":"paragraph","content":[{"text":"Yes","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1},"content":[{"type":"paragraph","content":[{"text":"No","type":"text"}]}]}]}]},{"type":"paragraph","content":[{"text":" ","type":"text"}]},{"type":"panel","attrs":{"panelType":"warning"},"content":[{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"NX_DFR.CK is only connected to the Common network","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"NX_DFR.R is only connected to the Common network","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"NX_WFG.ZI is only connected to the Common network if coming from the Fabric ","type":"text"}]}]}]}]},{"type":"heading","attrs":{"level":2},"content":[{"text":"Clock management","type":"text"}]},{"type":"paragraph","content":[{"text":"NanoXplore FPGAs contain a low-skew network in order to spread signal with high fanout like clock, reset and load signals.","type":"text"}]},{"type":"paragraph","content":[{"text":"The user must be very careful about the way to spread clock through the design. It is advised to follow the following rules sorted by level of recommendation:","type":"text"}]},{"type":"orderedList","attrs":{"order":1},"content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Use a pad directly connected to the closest CKG (these pads are suffixed by _CLK). Either the user instantiates a PLL or a WFG in the design or the tool instantiates automatically a WFG in bypass mode.","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph"},{"type":"orderedList","attrs":{"order":1},"content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"MEDIUM/LARGE: Use a common pad or internal logic and use a buffer NX_BD in ","type":"text"},{"text":"global_lowskew","type":"text","marks":[{"type":"em"}]},{"text":" mode.","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"ULTRA: Use a common pad or internal logic and use a NX_GCK_U in Common to System Converter ","type":"text"},{"text":"CSC ","type":"text","marks":[{"type":"em"}]},{"text":"mode.","type":"text"}]}]}]}]}]},{"type":"paragraph","content":[{"text":"Please have a look at ","type":"text"},{"type":"inlineCard","attrs":{"url":"https://nanoxplore-wiki.atlassian.net/wiki/pages/createpage.action?spaceKey=NAN&title=NxDesignSuite%2023.5%20Training%20Package%20%3A%20Application%20Note&linkCreation=true&fromPageId=357467616"}},{"text":" Design/LowskewManagement project.","type":"text"}]},{"type":"panel","attrs":{"panelType":"info"},"content":[{"type":"paragraph","content":[{"text":"PLL outputs are connected to WFG of the same CKG. User can either instantiate a WFG or let the tool instantiate a WFG in bypass mode. ","type":"text"}]},{"type":"paragraph","content":[{"text":"WFG outputs are connected to the low-skew network. ","type":"text"}]}]},{"type":"panel","attrs":{"panelType":"warning"},"content":[{"type":"paragraph","content":[{"text":"Do not use NX_BD(global_lowskew) or NX_GCK(CSC) with connected input already in low-skew network.","type":"text"}]}]},{"type":"paragraph","content":[{"text":"In case of clock gating or clock mux, it is recommended to implement the following architecture:","type":"text"}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Clock Gating:","type":"text"}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"MEDIUM/LARGE: Use a NX_CKS to gate a clock system signals with a command common signal.","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"ULTRA: Use a NX_GCK_U in Clock Switch ","type":"text"},{"text":"CKS ","type":"text","marks":[{"type":"em"}]},{"text":"mode to gate a clock system signals with a command common signal.","type":"text"}]}]}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Clock MUX:","type":"text"}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"ULTRA: Use a NX_GCK_U in Clock MUX ","type":"text"},{"text":"MUX ","type":"text","marks":[{"type":"em"}]},{"text":"mode to switch between 2 clock system signals with a command common signal.","type":"text"}]}]}]}]}]},{"type":"paragraph","content":[{"text":"Please have a look at ","type":"text"},{"type":"inlineCard","attrs":{"url":"https://nanoxplore-wiki.atlassian.net/wiki/pages/createpage.action?spaceKey=NAN&title=NxDesignSuite%2023.5%20Training%20Package%20%3A%20Application%20Note&linkCreation=true&fromPageId=357467616"}},{"text":" Component/ClockSwitch project.","type":"text"}]},{"type":"panel","attrs":{"panelType":"warning"},"content":[{"type":"paragraph","content":[{"text":"It is highly recommended to not cascade GCK as it is not natively supported by the architecture. User can cascade GCK anyway by allowing the associated option leading to a longer clock insertion path.","type":"text"}]}]},{"type":"heading","attrs":{"level":2},"content":[{"text":"Reset management","type":"text"}]},{"type":"paragraph","content":[{"text":"Like clocks, reset are generally spread to the whole design through the low-skew network because of high fanout too. ","type":"text"}]},{"type":"paragraph","content":[{"text":"Reset can be asynchronous or synchronous as registers of NanoXplore FPGAs are compliant with both.","type":"text"}]},{"type":"heading","attrs":{"level":2},"content":[{"text":"Global signals management","type":"text"}]},{"type":"paragraph","content":[{"text":"There are some signals with high fanout can be mapped into low-skew network and introduced some important delays. It could be the problem with synchronous signals load, set, reset, … ","type":"text"}]},{"type":"paragraph","content":[{"text":"In order to avoid this issue, use ","type":"text"},{"text":"rejectLowskew ","type":"text","marks":[{"type":"em"}]},{"text":"method.","type":"text"}]},{"type":"codeBlock","attrs":{"language":"python"},"content":[{"text":"p.rejectLowskew('inst1|reset_sync')","type":"text"}]},{"type":"heading","attrs":{"level":2},"content":[{"text":"Memory initialization","type":"text"}]},{"type":"paragraph","content":[{"text":"There are several ways to initialize a memory (attribute, generic, python method).","type":"text"}]},{"type":"paragraph","content":[{"text":"It is recommended to rather use python method ","type":"text"},{"text":"addMemoryInitialization ","type":"text","marks":[{"type":"em"}]},{"text":"described in ","type":"text"},{"type":"inlineCard","attrs":{"url":"https://nanoxplore-wiki.atlassian.net/wiki/pages/createpage.action?spaceKey=NAN&title=NxDesignSuite%2023.5%20NxPython%20Specification&linkCreation=true&fromPageId=357467616"}},{"text":" as it is compliant with inferred and instantiated memories.","type":"text"}]},{"type":"paragraph","content":[{"text":"Please have a look at ","type":"text"},{"type":"inlineCard","attrs":{"url":"https://nanoxplore-wiki.atlassian.net/wiki/pages/createpage.action?spaceKey=NAN&title=NxDesignSuite%2023.5%20Training%20Package%20%3A%20Application%20Note&linkCreation=true&fromPageId=357467616"}},{"text":" Init/Ram project.","type":"text"}]},{"type":"heading","attrs":{"level":2},"content":[{"text":"Memory Inference","type":"text"}]},{"type":"paragraph","content":[{"text":"In order to infer a memory instead of instantiating a NanoXplore primitive (advantage is the user can choose with the same RTL code to map this memory in RF, RAM, RAM_ECC, … thanks to NXpython constraints), it is recommended to follow TrainingPackage Design/MemInfer examples providing inference for ROM, SRAM, DPRAM with and without ECC.","type":"text"}]},{"type":"paragraph","content":[{"text":"Please have a look at ","type":"text"},{"type":"inlineCard","attrs":{"url":"https://nanoxplore-wiki.atlassian.net/wiki/pages/createpage.action?spaceKey=NAN&title=NxDesignSuite%2023.5%20Training%20Package%20%3A%20Application%20Note&linkCreation=true&fromPageId=357467616"}},{"text":" Design/MemInfer project.","type":"text"}]},{"type":"heading","attrs":{"level":2},"content":[{"text":"Hierarchy ","type":"text"}]},{"type":"paragraph","content":[{"text":"It is recommended to divide the design in well sized modules depending on the function they are responsible for.","type":"text"}]},{"type":"paragraph","content":[{"text":"It will be very helpful to constrain the design by module then.","type":"text"}]},{"type":"heading","attrs":{"level":2},"content":[{"text":"Logic depth","type":"text"}]},{"type":"paragraph","content":[{"text":"It is highly recommended to avoid large logic depth between registers as it will limit the maximum frequency of the design.","type":"text"}]},{"type":"paragraph","content":[{"text":"In addition, when a LUT is used, the DFF from the same Functionnal Element will be used either as a register or a buffer so adding pipeline in the design will not consume any additional instance.","type":"text"}]},{"type":"heading","attrs":{"level":1},"content":[{"text":"Project creation","type":"text"}]},{"type":"paragraph","content":[{"text":"Impulse is based on Python scripts that is to consider a project as a class and all options and constraints are methods associated to this class.","type":"text"}]},{"type":"paragraph","content":[{"text":"The user can either create a project based on a NanoXplore template (recommended) or start it from scratch. ","type":"text"}]},{"type":"paragraph","content":[{"text":"To use a NanoXplore template, please ask NanoXplore support team at ","type":"text"},{"text":"support@nanoxplore.com","type":"text","marks":[{"type":"link","attrs":{"href":"mailto:support@nanoxplore.com"}}]},{"text":".","type":"text"}]},{"type":"paragraph","content":[{"text":"In case of starting from scratch, it can be easier to create a project using the GUI in order to get the right basic NXpython methods.","type":"text"}]},{"type":"paragraph"},{"type":"paragraph","content":[{"text":"The project needs the following database: ","type":"text"}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Top cell library and top cell name","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"All files added to associated library","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Options and constraints","type":"text"}]}]}]},{"type":"panel","attrs":{"panelType":"warning"},"content":[{"type":"paragraph","content":[{"text":"Never add a nxLibrary file to your project. Impulse tool already get the needed files with NX primitives.","type":"text"}]}]},{"type":"paragraph"},{"type":"paragraph","content":[{"text":"Whatever the project base, it is recommended to comply with the following rules:","type":"text"}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Set options before any progress.","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Set IO pads locations and parameters before any progress.","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Save your project after each progress step.","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Separate your project in categories (setup,synthesis, placing, routing, sta) and set your constraints at the right place.","type":"text"}]}]}]},{"type":"heading","attrs":{"level":1},"content":[{"text":"Project check","type":"text"}]},{"type":"paragraph","content":[{"text":"Once the project is launched, it is necessary to check logs and reports in order to be sure there is not any issue leading to errors, undesired optimizations, …","type":"text"}]},{"type":"heading","attrs":{"level":2},"content":[{"text":"Logs and report files analysis","type":"text"}]},{"type":"heading","attrs":{"level":3},"content":[{"text":"Errors and warnings","type":"text"}]},{"type":"paragraph","content":[{"text":"First of all, check the project is successful until the required progress step. ","type":"text"}]},{"type":"paragraph","content":[{"text":"If not, a message appears in the console. Sometimes, the message is clear enough, but it could not be. So ","type":"text"},{"text":"errors.rpt ","type":"text","marks":[{"type":"em"}]},{"text":"and","type":"text"},{"text":" warning.rpt","type":"text","marks":[{"type":"em"}]},{"text":" reports can be very useful in order to grab the issue.","type":"text"}]},{"type":"paragraph","content":[{"text":"Note there reports are generated only if there are messages to report to the user.","type":"text"}]},{"type":"paragraph","content":[{"text":"If reported messages are not clear enough to solve the issue, contact the NanoXplore support team at ","type":"text"},{"text":"support@nanoxplore.com","type":"text","marks":[{"type":"link","attrs":{"href":"mailto:support@nanoxplore.com"}}]},{"text":" giving the archive in order to reproduce the issue (RTL sources + scripts).","type":"text"}]},{"type":"paragraph","content":[{"text":"Even though the project is successful, it is advised to parse these files.","type":"text"}]},{"type":"heading","attrs":{"level":3},"content":[{"text":"Complexity","type":"text"}]},{"type":"paragraph","content":[{"text":"After errors and warnings are solved or understood, check","type":"text"},{"text":" hierarchy.rpt","type":"text","marks":[{"type":"em"}]},{"text":" and ","type":"text"},{"text":"progress.rpt ","type":"text","marks":[{"type":"em"}]},{"text":"in order to check the number of instances if it is relevant with the estimation.","type":"text"}]},{"type":"paragraph","content":[{"text":"In order to get complexity module by module without confining it in a region, it is possible to use ","type":"text"},{"text":"addModule ","type":"text","marks":[{"type":"em"}]},{"text":"method described in ","type":"text"},{"text":"NXPython User Manual","type":"text","marks":[{"type":"link","attrs":{"href":"https://nanoxplore-wiki.atlassian.net/wiki/spaces/NAN/pages/357466248"}}]},{"text":".","type":"text"}]},{"type":"paragraph","content":[{"text":"Refer to ","type":"text"},{"text":"#Floor_planning_Complexity","type":"text","marks":[{"type":"link","attrs":{"href":"#Floor_planning_Complexity"}}]},{"text":" for more details.","type":"text"}]},{"type":"heading","attrs":{"level":3},"content":[{"text":"IO Location","type":"text"}]},{"type":"paragraph","content":[{"text":"Check in ","type":"text"},{"text":"progress.rpt ","type":"text","marks":[{"type":"em"}]},{"text":"none IO has been automatically placed by the design. It is marked with an exclamation sign.","type":"text"}]},{"type":"heading","attrs":{"level":3},"content":[{"text":"Common Errors","type":"text"}]},{"type":"paragraph","content":[{"text":"There are typical types of errors : ","type":"text"}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Oversize : Not enough instance capacity in the area","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Overflow : Not enough routing capacity in the area","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Blending Tile : Unable to route a path","type":"text"}]}]}]},{"type":"paragraph","content":[{"text":"These errors can be solved by changing the following parameters/options : ","type":"text"}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"If modules are constrained with ","type":"text"},{"text":"constrainModule ","type":"text","marks":[{"type":"em"}]},{"text":"method, increase area size","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Change the Seed used for P&R","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Change the following options: CongestionEffort, DensityEffort, RoutingEffort","type":"text"}]}]}]},{"type":"heading","attrs":{"level":1},"content":[{"text":"STA","type":"text"}]},{"type":"paragraph","content":[{"text":"Once the project is mature enough, Static Timing Analysis can be done in order to check how fast the design can operate.","type":"text"}]},{"type":"paragraph","content":[{"text":"STA tool can be launched from any step after Preparing (Placing 1/5) with the following example method:","type":"text"}]},{"type":"codeBlock","content":[{"text":"Timing_analysis = p.createAnalyzer()\nTiming_analysis.launch({'conditions': 'typical', 'maximumSlack': 500, 'searchPathsLimit': 10})","type":"text"}]},{"type":"panel","attrs":{"panelType":"note"},"content":[{"type":"paragraph","content":[{"text":"It is advised to launch a STA after Preparing as it shows up most critical paths and the maximum frequency with most optimistic hypothesis. If maximum frequencies are not higher enough at this step, the value will be less after routing.","type":"text"}]}]},{"type":"heading","attrs":{"level":3},"content":[{"text":"Clock creation","type":"text"}]},{"type":"paragraph","content":[{"text":"The input clock frequencies and other parameters must be informed to Impulse for STA.","type":"text"}]},{"type":"paragraph","content":[{"text":"Please refer to ","type":"text"},{"text":"createClock ","type":"text","marks":[{"type":"em"}]},{"text":"and ","type":"text"},{"text":"createGeneratedClock ","type":"text","marks":[{"type":"em"}]},{"text":"described in ","type":"text"},{"text":"NXPython Specification","type":"text","marks":[{"type":"link","attrs":{"href":"https://nanoxplore-wiki.atlassian.net/wiki/spaces/NAN/pages/357466248"}}]},{"text":" . ","type":"text"}]},{"type":"paragraph","content":[{"text":"If a PLL is used, PLL output clock frequencies are automatically computed by the software.","type":"text"}]},{"type":"heading","attrs":{"level":3},"content":[{"text":"Special path and clock domains relationship","type":"text"}]},{"type":"paragraph","content":[{"text":"Declare all false paths and multi cycle paths in order to not take into account some paths between registers in some particular cases.","type":"text"}]},{"type":"paragraph","content":[{"text":"Please refer to ","type":"text"},{"text":"addFalsePath ","type":"text","marks":[{"type":"em"}]},{"text":"and ","type":"text"},{"text":"addMultiCyclePath ","type":"text","marks":[{"type":"em"}]},{"text":"in ","type":"text"},{"text":"NXPython Specification","type":"text","marks":[{"type":"link","attrs":{"href":"https://nanoxplore-wiki.atlassian.net/wiki/spaces/NAN/pages/357466248"}}]},{"text":" . ","type":"text"}]},{"type":"paragraph","content":[{"text":"Clock groups can be created if clock domains are completely unrelated.","type":"text"}]},{"type":"heading","attrs":{"level":3},"content":[{"text":"Timing files analysis","type":"text"}]},{"type":"paragraph","content":[{"text":"When launching the STA tool, the following files are created : ","type":"text"}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Summary__.timing","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Violation__.timing","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Timing_Constraints_Report__.timing","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"DOMAIN_Input_to___.timing","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"DOMAIN__to___.timing","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"DOMAIN__to_Output__.timing","type":"text"}]}]}]},{"type":"paragraph","content":[{"text":"Use the first 3 timing files in order to get an overview of the project and other ones to analyze paths.","type":"text"}]},{"type":"heading","attrs":{"level":1},"content":[{"text":"Optimization","type":"text"}]},{"type":"heading","attrs":{"level":2},"content":[{"text":"Mapping","type":"text"}]},{"type":"heading","attrs":{"level":3},"content":[{"text":"Operator","type":"text"}]},{"type":"paragraph","content":[{"text":"Operators are divided in 3 categories : ","type":"text"}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Adder (ADD)","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"LessThan (LTN)","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Multiplier (MUL)","type":"text"}]}]}]},{"type":"panel","attrs":{"panelType":"note"},"content":[{"type":"paragraph","content":[{"text":"LessThan, LessThanOrEqual, GreaterThan and GreaterThanOrEqual are all considered as LessThan operators.","type":"text"}]}]},{"type":"paragraph","content":[{"text":"It is possible to map this operators in LUT, Carry or DSP using ","type":"text"},{"text":"addMappingDirective ","type":"text","marks":[{"type":"em"}]},{"text":"method described in ","type":"text"},{"text":"NXPython Specification","type":"text","marks":[{"type":"link","attrs":{"href":"https://nanoxplore-wiki.atlassian.net/wiki/spaces/NAN/pages/357466248"}}]},{"text":" . ","type":"text"}]},{"type":"paragraph","content":[{"text":"By default, adders are mapped into Carry and Multipliers in DSP. But it can sometimes be interesting to modify default mapping directives.","type":"text"}]},{"type":"paragraph","content":[{"text":"Check ","type":"text"},{"text":"#Mapping_Directive_Operator","type":"text","marks":[{"type":"link","attrs":{"href":"#Mapping_Directive_Operator"}}]},{"text":" for information about constraint setting.","type":"text"}]},{"type":"heading","attrs":{"level":3},"content":[{"text":"Memory","type":"text"}]},{"type":"paragraph","content":[{"text":"Memories can be mapped into logic elements (LUT/DFF), register files (RF), Memory Blocks (RAM) or Memory Blocks protected by EDAC correction using ","type":"text"},{"text":"addMappingDirective ","type":"text","marks":[{"type":"em"}]},{"text":"method described in ","type":"text"},{"text":"NXPython Specification","type":"text","marks":[{"type":"link","attrs":{"href":"https://nanoxplore-wiki.atlassian.net/wiki/spaces/NAN/pages/357466248"}}]},{"text":" . ","type":"text"}]},{"type":"paragraph","content":[{"text":"By default, small memories (equal or less than 64x16) will be mapped into RF and bigger ones mapped into RAM. But it can sometimes be interesting to modify default mapping directives.","type":"text"}]},{"type":"paragraph","content":[{"text":"It is highly recommended to size the design according to available depths and heights. Otherwise, too many memories will be instantiated and will affect the routing and STA performances.","type":"text"}]},{"type":"paragraph","content":[{"text":"In case of memory with reset assertion, the memory has to be mapped into DFF as RF or RAM does not have a reset input pin.","type":"text"}]},{"type":"paragraph","content":[{"text":"Check ","type":"text"},{"text":"#Mapping_Directive_Memory","type":"text","marks":[{"type":"link","attrs":{"href":"#Mapping_Directive_Memory"}}]},{"text":" for information about constraint setting.","type":"text"}]},{"type":"heading","attrs":{"level":2},"content":[{"text":"Placing","type":"text"}]},{"type":"heading","attrs":{"level":3},"content":[{"text":"Placing Constraint","type":"text"}]},{"type":"paragraph","content":[{"text":"In order to improve the maximum clock frequency for each clock domain, it is advised to follow the following steps:","type":"text"}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Define a floorplan for the design depending on module relationships and pinout. ","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Apply the floorplan to your Impulse project using ","type":"text"},{"text":"constrainModule ","type":"text","marks":[{"type":"em"}]},{"text":"described in ","type":"text"},{"text":"NXPython Specification","type":"text","marks":[{"type":"link","attrs":{"href":"https://nanoxplore-wiki.atlassian.net/wiki/spaces/NAN/pages/357466248"}}]},{"text":" . Check ","type":"text"},{"text":"#Floor_planning_Constrain_module","type":"text","marks":[{"type":"link","attrs":{"href":"#Floor_planning_Constrain_module"}}]},{"text":" for information about constraint setting.","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"If needed, repeat this process going deeper and deeper in the design hierarchy.","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"For last most critical paths, use ","type":"text"},{"text":"constrainPath ","type":"text","marks":[{"type":"em"}]},{"text":"described in ","type":"text"},{"text":"NXPython Specification","type":"text","marks":[{"type":"link","attrs":{"href":"https://nanoxplore-wiki.atlassian.net/wiki/spaces/NAN/pages/357466248"}}]},{"text":" in order to create a region with only a few elements contained into the specified path. Check ","type":"text"},{"text":"#Floor_planning_Constrain_path_between_registers","type":"text","marks":[{"type":"link","attrs":{"href":"#Floor_planning_Constrain_path_between_registers"}}]},{"text":" for information about constraint setting.","type":"text"}]}]}]},{"type":"paragraph","content":[{"text":"It can also have a very positive impact to create unitary projects and reuse the routed projects as a blackbox in your final top project using ","type":"text"},{"text":"addBlackBox ","type":"text","marks":[{"type":"em"}]},{"text":"described in ","type":"text"},{"text":"NXPython Specification","type":"text","marks":[{"type":"link","attrs":{"href":"https://nanoxplore-wiki.atlassian.net/wiki/spaces/NAN/pages/357466248"}}]},{"text":" . ","type":"text"}]},{"type":"paragraph"},{"type":"paragraph","content":[{"text":"It is also possible to place manually instances in a specified using the following NXpython methods all described in ","type":"text"},{"text":"NXPython Specification","type":"text","marks":[{"type":"link","attrs":{"href":"https://nanoxplore-wiki.atlassian.net/wiki/spaces/NAN/pages/357466248"}}]},{"text":" :","type":"text"}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"addPLLLocation ","type":"text","marks":[{"type":"em"}]},{"text":"for PLL instance in a CKG. Check ","type":"text"},{"text":"#Instance_placing_Ring_placing","type":"text","marks":[{"type":"link","attrs":{"href":"#"}}]},{"text":" for information about constraint setting.","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"addWFGLocation ","type":"text","marks":[{"type":"em"}]},{"text":"for WFG instance in a CKG and a WFG spot. Check ","type":"text"},{"text":"#Instance_placing_Ring_placing","type":"text","marks":[{"type":"link","attrs":{"href":"#Instance_placing_Ring_placing"}}]},{"text":" for information about constraint setting.","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"addRAMLocation ","type":"text","marks":[{"type":"em"}]},{"text":"for RAM instance in a CGB. Check ","type":"text"},{"text":"#Instance_placing_Ram_placing","type":"text","marks":[{"type":"link","attrs":{"href":"#Instance_placing_Ram_placing"}}]},{"text":" for information about constraint setting.","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"addDSPLocation ","type":"text","marks":[{"type":"em"}]},{"text":"for DSP instance in a CGB and a DSP spot. Check ","type":"text"},{"text":"#Instance_placing_Dsp_placing","type":"text","marks":[{"type":"link","attrs":{"href":"#"}}]},{"text":" for information about constraint setting.","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"setSite ","type":"text","marks":[{"type":"em"}]},{"text":"for LUT/DFF/CY in a TILE. Check ","type":"text"},{"text":"#Instance_placing_Tile_placing","type":"text","marks":[{"type":"link","attrs":{"href":"#Instance_placing_Tile_placing"}}]},{"text":" for information about constraint setting.","type":"text"}]}]}]},{"type":"heading","attrs":{"level":3},"content":[{"text":"Placing Option","type":"text"}]},{"type":"paragraph","content":[{"text":"Some options impact the placing and consequently the routing. In the end, STA performances are directly affected. The following options are concerned: ","type":"text"}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"DensityEffort","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"CongestionEffort","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"PolishingEffort","type":"text"}]}]}]},{"type":"paragraph","content":[{"text":"Increasing efforts may optimize placing for STA.","type":"text"}]},{"type":"paragraph","content":[{"text":"Check ","type":"text"},{"text":"NXPython Specification","type":"text","marks":[{"type":"link","attrs":{"href":"https://nanoxplore-wiki.atlassian.net/wiki/spaces/NAN/pages/357466248"}}]},{"text":" for more details about these options.","type":"text"}]},{"type":"panel","attrs":{"panelType":"warning"},"content":[{"type":"paragraph","content":[{"text":"Optimizing placing options for STA can lead to congestion errors. It is usually a trade-off to balance these options.","type":"text"}]}]},{"type":"heading","attrs":{"level":2},"content":[{"type":"inlineExtension","attrs":{"extensionType":"com.atlassian.confluence.macro.core","extensionKey":"anchor","parameters":{"macroParams":{"":{"value":"Design_complexity"},"legacyAnchorId":{"value":"NxDesignSuite23.5BestPractice-Design_complexity"}},"macroMetadata":{"macroId":{"value":"ba17a912997f49e6ec993e221efe1aa7"},"schemaVersion":{"value":"1"},"title":"Anchor"}},"localId":"84b3185e-9ff2-44a5-bc6f-f4a844ead95f"}},{"text":"Design Complexity","type":"text"}]},{"type":"paragraph","content":[{"text":"The logic depth of a design must be controlled. the method ","type":"text"},{"text":"reportDesignComplexity","type":"text","marks":[{"type":"em"}]},{"text":" and reportHierarchyComplexity are very helpful to have an overview.","type":"text"}]},{"type":"paragraph","content":[{"text":"Please have a look at ","type":"text"},{"text":"NXPython Specification","type":"text","marks":[{"type":"link","attrs":{"href":"https://nanoxplore-wiki.atlassian.net/wiki/spaces/NAN/pages/357466248"}}]},{"text":" reportDesignComplexity and reportHierarchyComplexity methods.","type":"text"}]},{"type":"heading","attrs":{"level":3},"content":[{"type":"inlineExtension","attrs":{"extensionType":"com.atlassian.confluence.macro.core","extensionKey":"anchor","parameters":{"macroParams":{"":{"value":"Complexity"},"legacyAnchorId":{"value":"NxDesignSuite23.5BestPractice-Complexity"}},"macroMetadata":{"macroId":{"value":"814832b4ac42186cb3551bf757c385b5"},"schemaVersion":{"value":"1"},"title":"Anchor"}},"localId":"73616dde-ecd2-49e3-b41d-4c88f400c175"}},{"text":"Complexity","type":"text"}]},{"type":"paragraph","content":[{"text":"In order to get complexity for each module of the design, check the detailed hierarchy of the design.","type":"text"}]},{"type":"paragraph","content":[{"text":"Complexity is given for each module with the sum of the complexity of each sub-module and the module itself.","type":"text"}]},{"type":"paragraph","content":[{"text":"For instance:","type":"text"}]},{"type":"codeBlock","marks":[{"type":"breakout","attrs":{"mode":"wide"}}],"content":[{"text":"08:50:49:info | --------------------------------------------\n08:50:49:info | - Detailed Hierarchy Statistics -\n08:50:49:info | --------------------------------------------\n08:50:49:info | ~ hierarchical\n08:50:49:info | Resources:\n08:50:49:info | NX_LUT : 13\n08:50:49:info | NX_DFF : 73\n08:50:49:info | NX_IOB : 51\n08:50:49:info | NX_BFR : 99\n08:50:49:info | NX_WFG : 3\n08:50:49:info | ~ |-> row_col_pipe(X212B9C19) [ GEN_HIER0 ]\n08:50:49:info | |-> Resources:\n08:50:49:info | |-> NX_LUT : 3\n08:50:49:info | |-> NX_DFF : 23\n08:50:49:info | GEN_HIER0_ROW-0 | |-> timing_pipe(X2A98C8C6) [ GEN_HIER0|GEN_ROW[0].ROW_PIPE ]\n08:50:49:info | | |-> Resources:\n08:50:49:info | | |-> NX_DFF : 5\n08:50:49:info | ~ | |-> timing_pipe(X2A98C8C6) [ GEN_HIER0|GEN_ROW[1].ROW_PIPE ]\n08:50:49:info | | |-> Resources:\n08:50:49:info | | |-> NX_DFF : 5","type":"text"}]},{"type":"paragraph"},{"type":"heading","attrs":{"level":1},"content":[{"text":"How to use NXpython constraints methods","type":"text"}]},{"type":"heading","attrs":{"level":2},"content":[{"text":"Mapping directive","type":"text"}]},{"type":"heading","attrs":{"level":3},"content":[{"type":"inlineExtension","attrs":{"extensionType":"com.atlassian.confluence.macro.core","extensionKey":"anchor","parameters":{"macroParams":{"":{"value":"Mapping_directive_Operator"},"legacyAnchorId":{"value":"NxDesignSuite23.5BestPractice-Mapping_directive_Operator"}},"macroMetadata":{"macroId":{"value":"095ebb455b87babea6f8b3d6bb6cdfb8"},"schemaVersion":{"value":"1"},"title":"Anchor"}},"localId":"03f02496-6b72-4dbd-a750-d7d1b5f3e166"}},{"text":"Operator","type":"text"}]},{"type":"paragraph","content":[{"text":"In order to map an operator into LUT, CY or DSP, follow the following steps:","type":"text"}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Launch your design for the first time without constraint.","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Grab the operator model or instance in ","type":"text"},{"text":"operators.rpt ","type":"text","marks":[{"type":"em"}]},{"text":"report. For instance, “ | Operator 'add_3u_3u' | \t : add_L25\t(line 25 in …","type":"text"},{"text":"”","type":"text","marks":[{"type":"em"}]},{"text":", model name is ","type":"text"},{"text":"“add_3u_3u” ","type":"text","marks":[{"type":"em"}]},{"text":"and instance name is “add_L25”.","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Add the constraint specifying instance to map the operator, for instance ","type":"text"},{"text":"“","type":"text","marks":[{"type":"em"}]},{"text":" ","type":"text"},{"text":"p.addMappingDirective('getModels(add_3u_3u)','ADD','DSP')","type":"text","marks":[{"type":"em"}]},{"text":"” or p.addMappingDirective('getInstances(add_L25)','ADD','DSP')","type":"text"},{"text":"”","type":"text","marks":[{"type":"em"}]},{"text":", and relaunch the project. ","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Check in ","type":"text"},{"text":"operators.rpt ","type":"text","marks":[{"type":"em"}]},{"text":"report the constraint matched with the desired instance.","type":"text"}]}]}]},{"type":"paragraph","content":[{"text":"Please have a look at ","type":"text"},{"type":"inlineCard","attrs":{"url":"https://nanoxplore-wiki.atlassian.net/wiki/pages/createpage.action?spaceKey=NAN&title=NxDesignSuite%2023.5%20Training%20Package%20%3A%20Application%20Note&linkCreation=true&fromPageId=357467616"}},{"text":" MappingDirective/Operator project.","type":"text"}]},{"type":"heading","attrs":{"level":3},"content":[{"type":"inlineExtension","attrs":{"extensionType":"com.atlassian.confluence.macro.core","extensionKey":"anchor","parameters":{"macroParams":{"":{"value":"Mapping_directive_Memory"},"legacyAnchorId":{"value":"NxDesignSuite23.5BestPractice-Mapping_directive_Memory"}},"macroMetadata":{"macroId":{"value":"ec346ef91fd05badad25ea8a04e33561"},"schemaVersion":{"value":"1"},"title":"Anchor"}},"localId":"2ec41f2b-31bb-4bb7-8ad5-eb5aae8df36a"}},{"text":"Memory","type":"text"}]},{"type":"paragraph","content":[{"text":"In order to map an operator into FE, RF, RAM or RAM_ECC, follow the following steps:","type":"text"}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Launch your design for the first time without constraint.","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Grab the memory model in ","type":"text"},{"text":"memories.rpt ","type":"text","marks":[{"type":"em"}]},{"text":"report. For instance, “ | Ram 'RAM_s_mem' Analysis:","type":"text"},{"text":"”","type":"text","marks":[{"type":"em"}]},{"text":", model name is ","type":"text"},{"text":"“RAM_s_mem”","type":"text","marks":[{"type":"em"}]},{"text":".","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Add the constraint specifying instance to map the operator, for instance ","type":"text"},{"text":"“","type":"text","marks":[{"type":"em"}]},{"text":" ","type":"text"},{"text":"p.addMappingDirective('getModels(RAM_s_mem)','RAM','RAM_ECC')","type":"text","marks":[{"type":"em"}]},{"text":"”, and relaunch the project. ","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Check in ","type":"text"},{"text":"memories.rpt ","type":"text","marks":[{"type":"em"}]},{"text":"report the constraint matched with the desired instance.","type":"text"}]}]}]},{"type":"paragraph","content":[{"text":"Please have a look at ","type":"text"},{"type":"inlineCard","attrs":{"url":"https://nanoxplore-wiki.atlassian.net/wiki/pages/createpage.action?spaceKey=NAN&title=NxDesignSuite%2023.5%20Training%20Package%20%3A%20Application%20Note&linkCreation=true&fromPageId=357467616"}},{"text":" MappingDirective/Memory project.","type":"text"}]},{"type":"heading","attrs":{"level":2},"content":[{"text":"Instance placing","type":"text"}]},{"type":"heading","attrs":{"level":3},"content":[{"type":"inlineExtension","attrs":{"extensionType":"com.atlassian.confluence.macro.core","extensionKey":"anchor","parameters":{"macroParams":{"":{"value":"Instance_placing_Dsp_placing"},"legacyAnchorId":{"value":"NxDesignSuite23.5BestPractice-Instance_placing_Dsp_placing"}},"macroMetadata":{"macroId":{"value":"d0d09a0d40fae2f2a37d45ddab5f66bd"},"schemaVersion":{"value":"1"},"title":"Anchor"}},"localId":"2cc62195-4a0b-4a08-b085-90abcd477b56"}},{"text":"DSP placing","type":"text"}]},{"type":"paragraph","content":[{"text":"In order to place manually an inferred DSP in a CGB spot, follow the following steps:","type":"text"}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Launch your design for the first time without constraint.","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Grab the DSP name in ","type":"text"},{"text":"operators.rpt ","type":"text","marks":[{"type":"em"}]},{"text":"report. For instance, “","type":"text"},{"text":"in line : mult_L28\t(line 28 in […]”","type":"text","marks":[{"type":"em"}]},{"text":", name is ","type":"text"},{"text":"“mult_L28”","type":"text","marks":[{"type":"em"}]},{"text":".","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Add the constraint specifying DSP spot (CGB coordinates and L or R respectively for Left and Right), for instance ","type":"text"},{"text":"“p.addDSPLocation('DSP_mult_L28','CGB[8x8]:R')”","type":"text","marks":[{"type":"em"}]},{"text":", and relaunch the project. ","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Check in ","type":"text"},{"text":"preplaced.rpt ","type":"text","marks":[{"type":"em"}]},{"text":"report the constraint matched with the desired instance.","type":"text"}]}]}]},{"type":"panel","attrs":{"panelType":"info"},"content":[{"type":"paragraph","content":[{"text":"In case of direct primitive instance of the DSP, DSP name is the path to the DSP. For instance, ","type":"text"},{"text":"p.addDSPLocation('module0|submodule1|DSP_INST_0','CGB[28x4]:L')","type":"text","marks":[{"type":"em"}]},{"text":".","type":"text"}]}]},{"type":"paragraph","content":[{"text":"Please have a look at ","type":"text"},{"type":"inlineCard","attrs":{"url":"https://nanoxplore-wiki.atlassian.net/wiki/pages/createpage.action?spaceKey=NAN&title=NxDesignSuite%2023.5%20Training%20Package%20%3A%20Application%20Note&linkCreation=true&fromPageId=357467616"}},{"text":" PlacingConstraint/DspLocation project.","type":"text"}]},{"type":"heading","attrs":{"level":3},"content":[{"type":"inlineExtension","attrs":{"extensionType":"com.atlassian.confluence.macro.core","extensionKey":"anchor","parameters":{"macroParams":{"":{"value":"Instance_placing_Ram_placing"},"legacyAnchorId":{"value":"NxDesignSuite23.5BestPractice-Instance_placing_Ram_placing"}},"macroMetadata":{"macroId":{"value":"8919333285759dafccc3198d16841e3a"},"schemaVersion":{"value":"1"},"title":"Anchor"}},"localId":"b6638eaa-d582-4171-8e24-920b51088d12"}},{"text":"RAM placing","type":"text"}]},{"type":"paragraph","content":[{"text":"In order to place manually an inferred RAM in a CGB spot, follow the following steps:","type":"text"}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Launch your design for the first time without constraint.","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Grab the RAM name in ","type":"text"},{"text":"memories.rpt ","type":"text","marks":[{"type":"em"}]},{"text":"report. For instance,","type":"text"},{"text":"“ | RAM Generation for g_loop[0].i_RAM_example|s_mem”","type":"text","marks":[{"type":"em"}]},{"text":", name is “","type":"text"},{"text":"g_loop[0].i_RAM_example|s_mem|ram0_0_0_0","type":"text","marks":[{"type":"em"}]},{"text":"”.","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Add the constraint specifying RAM spot (CGB coordinates), for instance ","type":"text"},{"text":"“p.addRAMLocation('g_loop[0].i_RAM_example|s_mem|ram0_0_0_0','CGB[8x8]')”","type":"text","marks":[{"type":"em"}]},{"text":", and relaunch the project.","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Check in ","type":"text"},{"text":"preplaced.rpt ","type":"text","marks":[{"type":"em"}]},{"text":"report the constraint matched with the desired instance.","type":"text"}]}]}]},{"type":"panel","attrs":{"panelType":"info"},"content":[{"type":"paragraph","content":[{"text":"In case of direct primitive instance of the RAM, RAM name is the path to the RAM. For instance, ","type":"text"},{"text":"p.addRAMLocation('module0|submodule1|ram','CGB[28x4]')","type":"text","marks":[{"type":"em"}]},{"text":".","type":"text"}]}]},{"type":"paragraph","content":[{"text":"Please have a look at ","type":"text"},{"type":"inlineCard","attrs":{"url":"https://nanoxplore-wiki.atlassian.net/wiki/pages/createpage.action?spaceKey=NAN&title=NxDesignSuite%2023.5%20Training%20Package%20%3A%20Application%20Note&linkCreation=true&fromPageId=357467616"}},{"text":" PlacingConstraint/RamLocation project.","type":"text"}]},{"type":"heading","attrs":{"level":3},"content":[{"type":"inlineExtension","attrs":{"extensionType":"com.atlassian.confluence.macro.core","extensionKey":"anchor","parameters":{"macroParams":{"":{"value":"Instance_placing_Ring_placing"},"legacyAnchorId":{"value":"NxDesignSuite23.5BestPractice-Instance_placing_Ring_placing"}},"macroMetadata":{"macroId":{"value":"dfacd66f2087ee3dfce9344551c89426"},"schemaVersion":{"value":"1"},"title":"Anchor"}},"localId":"1f695461-d053-4220-a5e3-e51831bf0b58"}},{"text":"Ring placing","type":"text"}]},{"type":"paragraph","content":[{"text":"In order to place manually an automatically created WFG in a CKG spot, follow the following steps:","type":"text"}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Launch your design for the first time without constraint.","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Grab the RAM name in ","type":"text"},{"text":"lowskew.rpt ","type":"text","marks":[{"type":"em"}]},{"text":"report. For instance, ","type":"text"},{"text":"“rg~clk_divp2 from instance wfg_B_clk_divp2”","type":"text","marks":[{"type":"em"}]},{"text":", name is “","type":"text"},{"text":"wfg_B_clk_divp2","type":"text","marks":[{"type":"em"}]},{"text":"”.","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Add the constraint specifying RAM spot (CGB coordinates), for instance ","type":"text"},{"text":"“p.addRingLocation(' wfg_B_clk_divp2','CKG3.WFG_C1')”","type":"text","marks":[{"type":"em"}]},{"text":", and relaunch the project.","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Check in ","type":"text"},{"text":"preplaced.rpt ","type":"text","marks":[{"type":"em"}]},{"text":"report the constraint matched with the desired instance.","type":"text"}]}]}]},{"type":"panel","attrs":{"panelType":"info"},"content":[{"type":"paragraph","content":[{"text":"In case of direct primitive instance of the WFG or PLL, WFG or PLL name is the path to the WFG or PLL. For instance, ","type":"text"},{"text":"p.addRingLocation('module0|submodule1|PLL_INST0','CKG3.PLL1') or p.addRingLocation('module0|submodule1|WFG_INST0','CKG3.WFG_C1')","type":"text","marks":[{"type":"em"}]},{"text":".","type":"text"}]}]},{"type":"panel","attrs":{"panelType":"warning"},"content":[{"type":"paragraph","content":[{"text":"In order to place manually a WFG, location must comply with WFG type that is to say Core WFG (WFG_Cx) or Ring WFG (WFG_Rx). Mix WFG (WFG_Mx) can be chosen for either a Core or a Ring signal.","type":"text"}]}]},{"type":"paragraph","content":[{"text":"Please have a look at ","type":"text"},{"type":"inlineCard","attrs":{"url":"https://nanoxplore-wiki.atlassian.net/wiki/pages/createpage.action?spaceKey=NAN&title=NxDesignSuite%2023.5%20Training%20Package%20%3A%20Application%20Note&linkCreation=true&fromPageId=357467616"}},{"text":" PlacingConstraint/RingLocation project.","type":"text"}]},{"type":"heading","attrs":{"level":3},"content":[{"type":"inlineExtension","attrs":{"extensionType":"com.atlassian.confluence.macro.core","extensionKey":"anchor","parameters":{"macroParams":{"":{"value":"Instance_placing_Tile_placing"},"legacyAnchorId":{"value":"NxDesignSuite23.5BestPractice-Instance_placing_Tile_placing"}},"macroMetadata":{"macroId":{"value":"e406fef7ce2522306369e344dd68dd0a"},"schemaVersion":{"value":"1"},"title":"Anchor"}},"localId":"b5a3321d-795e-4678-8c0f-8cd26d4b924f"}},{"text":"Tile placing","type":"text"}]},{"type":"paragraph","content":[{"text":"In order to place manually an inferred TILE instance like DFF, LUT or CY, follow the following steps:","type":"text"}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Launch your design for the first time without constraint.","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Grab the register name in ","type":"text"},{"text":"RegisterSummary.rpt ","type":"text","marks":[{"type":"em"}]},{"text":"report or in timing files. For instance, ","type":"text"},{"text":"i_cpt_0|s_cpt_out_reg[5]”","type":"text","marks":[{"type":"em"}]},{"text":".","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Add the constraint specifying TILE spot (TILE coordinates), for instance ","type":"text"},{"text":"“p.setSite('i_cpt_0|s_cpt_out_reg[0]','TILE[2x2]'”","type":"text","marks":[{"type":"em"}]},{"text":", and relaunch the project.","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Check in ","type":"text"},{"text":"preplaced.rpt ","type":"text","marks":[{"type":"em"}]},{"text":"report the constraint matched with the desired instance.","type":"text"}]}]}]},{"type":"paragraph","content":[{"text":"Please have a look at ","type":"text"},{"type":"inlineCard","attrs":{"url":"https://nanoxplore-wiki.atlassian.net/wiki/pages/createpage.action?spaceKey=NAN&title=NxDesignSuite%2023.5%20Training%20Package%20%3A%20Application%20Note&linkCreation=true&fromPageId=357467616"}},{"text":" PlacingConstraint/Site project.","type":"text"}]},{"type":"heading","attrs":{"level":2},"content":[{"text":"Floor planning","type":"text"}]},{"type":"heading","attrs":{"level":3},"content":[{"type":"inlineExtension","attrs":{"extensionType":"com.atlassian.confluence.macro.core","extensionKey":"anchor","parameters":{"macroParams":{"":{"value":"Floor_planning_Constrain_module"},"legacyAnchorId":{"value":"NxDesignSuite23.5BestPractice-Floor_planning_Constrain_module"}},"macroMetadata":{"macroId":{"value":"34e22c3120cbc8612ddaba51e59fb7c8"},"schemaVersion":{"value":"1"},"title":"Anchor"}},"localId":"0cf97536-5503-4abf-8927-0086ab4cd6b6"}},{"text":"Constrain Module ","type":"text"}]},{"type":"paragraph","content":[{"text":"In order to confine a module (component of the design hierarchy) in a region containing TILE, CGB and MESH, follow the following steps:","type":"text"}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Launch your design for the first time without constraint.","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Grab the module name in ","type":"text"},{"text":"hierarchy.rpt ","type":"text","marks":[{"type":"em"}]},{"text":"report. For instance, ","type":"text"},{"text":"“| ~ |-> row_col_pipe(X212B9C19) [ GEN_HIER0 ]”","type":"text","marks":[{"type":"em"}]},{"text":", name is “","type":"text"},{"text":"|-> row_col_pipe(X212B9C19) [ GEN_HIER0 ]","type":"text","marks":[{"type":"em"}]},{"text":"”.","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Add the constraint specifying area coordinates, for instance ","type":"text"},{"text":"“p.constrainModule('|-> row_col_pipe(X212B9C19) [ GEN_HIER0 ]','GEN_HIER0_ROW_M','Soft',9,6,2,3,'GEN_HIER0_ROW_R',False)”","type":"text","marks":[{"type":"em"}]},{"text":", and relaunch the project.","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Check in ","type":"text"},{"text":"hierarchy.rpt ","type":"text","marks":[{"type":"em"}]},{"text":"report the constraint matched with the desired instance.","type":"text"}]}]}]},{"type":"paragraph","content":[{"text":"Please have a look at ","type":"text"},{"type":"inlineCard","attrs":{"url":"https://nanoxplore-wiki.atlassian.net/wiki/pages/createpage.action?spaceKey=NAN&title=NxDesignSuite%2023.5%20Training%20Package%20%3A%20Application%20Note&linkCreation=true&fromPageId=357467616"}},{"text":" PlacingConstraint/Region project.","type":"text"}]},{"type":"heading","attrs":{"level":3},"content":[{"type":"inlineExtension","attrs":{"extensionType":"com.atlassian.confluence.macro.core","extensionKey":"anchor","parameters":{"macroParams":{"":{"value":"Floor_planning_Constrain_path_between_register"},"legacyAnchorId":{"value":"NxDesignSuite23.5BestPractice-Floor_planning_Constrain_path_between_register"}},"macroMetadata":{"macroId":{"value":"aa021495f63084ef82cce08fa38a2f6c"},"schemaVersion":{"value":"1"},"title":"Anchor"}},"localId":"a2ff5365-3ce2-4fc4-bf1e-b0b5d8255d0f"}},{"text":"Constrain path between registers","type":"text"}]},{"type":"paragraph","content":[{"text":"In order to confine all instances in a path between 2 registers in a region containing TILE, CGB and MESH, follow the following steps:","type":"text"}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Launch your design for the first time without constraint.","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Grab the source and target register in ","type":"text"},{"text":"DOMAIN__to___.timing","type":"text","marks":[{"type":"em"}]},{"text":". For instance, ","type":"text"},{"text":"“module0|submodule0|pipe_reg[0].CK” ","type":"text","marks":[{"type":"em"}]},{"text":"and","type":"text"},{"text":" “module0|submodule0|pipe_reg[1].CK” ","type":"text","marks":[{"type":"em"}]},{"text":", names are “","type":"text"},{"text":"module0|submodule0|pipe_reg[0]","type":"text","marks":[{"type":"em"}]},{"text":"” and “","type":"text"},{"text":"module0|submodule0|pipe_reg[1]","type":"text","marks":[{"type":"em"}]},{"text":"”.","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Add the constraint specifying area coordinates, for instance ","type":"text"},{"text":"“p.constrainPath('|-> row_col_pipe(X212B9C19) [ GEN_HIER0 ]','PIPE_REG_M','Soft',9,6,2,3,'PIPE_REG_R',False)”","type":"text","marks":[{"type":"em"}]},{"text":", and relaunch the project.","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Check in ","type":"text"},{"text":"hierarchy.rpt ","type":"text","marks":[{"type":"em"}]},{"text":"report the constraint matched with the desired instance.","type":"text"}]}]}]},{"type":"paragraph","content":[{"text":"Please have a look at ","type":"text"},{"type":"inlineCard","attrs":{"url":"https://nanoxplore-wiki.atlassian.net/wiki/pages/createpage.action?spaceKey=NAN&title=NxDesignSuite%2023.5%20Training%20Package%20%3A%20Application%20Note&linkCreation=true&fromPageId=357467616"}},{"text":" PlacingConstraint/ConstrainPath project.","type":"text"}]},{"type":"heading","attrs":{"level":3},"content":[{"type":"inlineExtension","attrs":{"extensionType":"com.atlassian.confluence.macro.core","extensionKey":"anchor","parameters":{"macroParams":{"":{"value":"Floor_planning_Preplace_ip"},"legacyAnchorId":{"value":"NxDesignSuite23.5BestPractice-Floor_planning_Preplace_ip"}},"macroMetadata":{"macroId":{"value":"625e28a84eaf8466a090da0e4ae6b55a"},"schemaVersion":{"value":"1"},"title":"Anchor"}},"localId":"b7b92be8-f584-4730-b2c6-1b8ebd7acba0"}},{"text":"Preplace IP","type":"text"}]},{"type":"paragraph","content":[{"text":"In order to preplace a macro IP of a global design in order to reach design specifications (delays, maximum frequencies, …) in an area of the chip before integrating it in the global design, follow the following steps:","type":"text"}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Define the macro IP as the top cell.","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Define a minimum aperture and all needed constraints as it was a global project to reach specifications. Save the project file after routed steps.","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Run the project until Placing 3/5 step and use ","type":"text"},{"text":"saveIP ","type":"text","marks":[{"type":"em"}]},{"text":"method to save the preplaced IP.","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Do not declare the macro IP entity file in the global project. Instead, add the macro IP as a blackbox, specifying coordinates of the top left corner of the macro IP aperture in the global project, for instance ","type":"text"},{"text":"“","type":"text","marks":[{"type":"em"}]},{"text":"p.addBlackBox('switch_counter',IP','../switch_counter_preplaced.json','g_inst.i_switch_counter_0:1x8')","type":"text","marks":[{"type":"code"}]},{"text":"”","type":"text","marks":[{"type":"em"}]},{"text":".","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Check in log the constraint matched.","type":"text"}]}]}]},{"type":"paragraph","content":[{"text":"Please have a look at ","type":"text"},{"type":"inlineCard","attrs":{"url":"https://nanoxplore-wiki.atlassian.net/wiki/pages/createpage.action?spaceKey=NAN&title=NxDesignSuite%2023.5%20Training%20Package%20%3A%20Application%20Note&linkCreation=true&fromPageId=357467616"}},{"text":" PlacingConstraint/Preplace project.","type":"text"}]},{"type":"panel","attrs":{"panelType":"note"},"content":[{"type":"paragraph","content":[{"text":"In case of insufficient number of IO in the preplacing IP project, use can use the embedded variant of the same FPGA target. ","type":"text"}]}]},{"type":"heading","attrs":{"level":2},"content":[{"text":"STA constraints","type":"text"}]},{"type":"heading","attrs":{"level":3},"content":[{"type":"inlineExtension","attrs":{"extensionType":"com.atlassian.confluence.macro.core","extensionKey":"anchor","parameters":{"macroParams":{"":{"value":"Sta_constraints_Clock_declaration"},"legacyAnchorId":{"value":"NxDesignSuite23.5BestPractice-Sta_constraints_Clock_declaration"}},"macroMetadata":{"macroId":{"value":"23cd6f19df4814e4acefb24d2ceea221"},"schemaVersion":{"value":"1"},"title":"Anchor"}},"localId":"0076393b-51dc-4e3f-9e01-7e1755eb4630"}},{"text":"Clock declaration","type":"text"}]},{"type":"paragraph","content":[{"text":"In order to declare a clock in your project in order to get required frequencies in logs, follow the following steps:","type":"text"}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Launch your design for the first time without constraint.","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Grab the clock name in ","type":"text"},{"text":"lowskew.rpt","type":"text","marks":[{"type":"em"}]},{"text":". For instance, ","type":"text"},{"text":"“rg~clk_divp2 from instance wfg_B_clk_divp2”, name is “rg~clk_divp2”.","type":"text","marks":[{"type":"em"}]}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Add the constraint specifying clock parameters, for instance ","type":"text"},{"text":"“p.createClock('getClockNet(g~clk_divp2)','clk_div_p2',20000,5000,15000)”","type":"text","marks":[{"type":"em"}]},{"text":", and relaunch the project.","type":"text"}]}]}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Check in ","type":"text"},{"text":"Summary__.timing ","type":"text","marks":[{"type":"em"}]},{"text":"clock is renamed and required frequency is now mentioned.","type":"text"}]}]}]},{"type":"panel","attrs":{"panelType":"note"},"content":[{"type":"paragraph","content":[{"text":"developCKGs method is active by default, Impulse computes automatically PLL and WFG required frequencies if input clock is declared.","type":"text"}]}]},{"type":"paragraph","content":[{"text":"Please have a look at ","type":"text"},{"type":"inlineCard","attrs":{"url":"https://nanoxplore-wiki.atlassian.net/wiki/pages/createpage.action?spaceKey=NAN&title=NxDesignSuite%2023.5%20Training%20Package%20%3A%20Application%20Note&linkCreation=true&fromPageId=357467616"}},{"text":" StaConstraint/GeneratedClock project.","type":"text"}]},{"type":"heading","attrs":{"level":3},"content":[{"type":"inlineExtension","attrs":{"extensionType":"com.atlassian.confluence.macro.core","extensionKey":"anchor","parameters":{"macroParams":{"":{"value":"Sta_constraints_Generated_clock_declaration"},"legacyAnchorId":{"value":"NxDesignSuite23.5BestPractice-Sta_constraints_Generated_clock_declaration"}},"macroMetadata":{"macroId":{"value":"5cf4f1dd523a0a8d5ba83c2813138c7a"},"schemaVersion":{"value":"1"},"title":"Anchor"}},"localId":"c8845440-ac11-443b-b30a-b43b1cf52890"}},{"text":"Generated clock declaration","type":"text"}]},{"type":"paragraph","content":[{"text":"In order to declare a clock in your project in order to get required frequencies in logs, follow the following steps:","type":"text"}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Grab the clock name getting the hierarchy path to the generated clock.","type":"text"}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Add the constraint specifying clock parameters, for instance ","type":"text"},{"text":"“p.createGeneratedClock(getClock('clk_main'),getRegisterClock('i_clock_0|counter_reg[0]'), 'clk_fabric',{'DivideBy': 2})”","type":"text","marks":[{"type":"em"}]},{"text":".","type":"text"}]}]}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Check timing files are created for this new clock domain.","type":"text"}]}]}]},{"type":"paragraph","content":[{"text":"Please have a look at ","type":"text"},{"type":"inlineCard","attrs":{"url":"https://nanoxplore-wiki.atlassian.net/wiki/pages/createpage.action?spaceKey=NAN&title=NxDesignSuite%2023.5%20Training%20Package%20%3A%20Application%20Note&linkCreation=true&fromPageId=357467616"}},{"text":" StaConstraint/GeneratedClock project.","type":"text"}]},{"type":"heading","attrs":{"level":3},"content":[{"type":"inlineExtension","attrs":{"extensionType":"com.atlassian.confluence.macro.core","extensionKey":"anchor","parameters":{"macroParams":{"":{"value":"Sta_constraints_Constrain_path_between_registers"},"legacyAnchorId":{"value":"NxDesignSuite23.5BestPractice-Sta_constraints_Constrain_path_between_registers"}},"macroMetadata":{"macroId":{"value":"777bd66483f927282e493c8b9a87b605"},"schemaVersion":{"value":"1"},"title":"Anchor"}},"localId":"f381f503-41cf-49bf-9658-f5f7bbd311c7"}},{"text":"Constrain path between registers","type":"text"}]},{"type":"paragraph","content":[{"text":"In order to declare a path between 2 registers as a false path, multi-cycle path, min or max delay path, follow the following steps:","type":"text"}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Launch your design for the first time without constraint.","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Grab the source and target register in ","type":"text"},{"text":"DOMAIN__to___.timing","type":"text","marks":[{"type":"em"}]},{"text":". For instance, ","type":"text"},{"text":"“module0|submodule0|pipe_reg[0].CK” ","type":"text","marks":[{"type":"em"}]},{"text":"and","type":"text"},{"text":" “module0|submodule0|pipe_reg[1].CK” ","type":"text","marks":[{"type":"em"}]},{"text":", names are “","type":"text"},{"text":"module0|submodule0|pipe_reg[0]","type":"text","marks":[{"type":"em"}]},{"text":"” and “","type":"text"},{"text":"module0|submodule0|pipe_reg[1]","type":"text","marks":[{"type":"em"}]},{"text":"”.","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Add the constraint specifying area coordinates, for instance ","type":"text"},{"text":"“p.addFalsePath('getRegisters(module0|submodule0|pipe_reg[0])','getRegisters(module0|submodule0|pipe_reg[0])')”","type":"text","marks":[{"type":"em"}]},{"text":", and relaunch the project.","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Check in ","type":"text"},{"text":"DOMAIN__to___.timingt ","type":"text","marks":[{"type":"em"}]},{"text":"report the path no longer appears.","type":"text"}]}]}]},{"type":"paragraph","content":[{"text":"Please have a look at ","type":"text"},{"type":"inlineCard","attrs":{"url":"https://nanoxplore-wiki.atlassian.net/wiki/pages/createpage.action?spaceKey=NAN&title=NxDesignSuite%2023.5%20Training%20Package%20%3A%20Application%20Note&linkCreation=true&fromPageId=357467616"}},{"text":" StaConstraint/FalsePath project.","type":"text"}]},{"type":"heading","attrs":{"level":1},"content":[{"text":"How to improve STA results","type":"text"}]},{"type":"heading","attrs":{"level":2},"content":[{"text":"STA tool","type":"text"}]},{"type":"paragraph","content":[{"text":"It is recommended to launch the STA tool after Placing 1/5 step named “Preparing”. It allows to witness the number of logic elements crossed and check if it is possible to reach performances when the margin in the most optimistic scenario is high enough.","type":"text"}]},{"type":"heading","attrs":{"level":2},"content":[{"text":"ClockCreation","type":"text"}]},{"type":"paragraph","content":[{"text":"Before launching STA tool, all constraints must be defined.","type":"text"}]},{"type":"paragraph","content":[{"text":"The user must define:","type":"text"}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"createClock for clock coming from a port. Refer to ","type":"text"},{"text":"#Sta_constraints_Clock_creation","type":"text","marks":[{"type":"link","attrs":{"href":"#Sta_constraints_Clock_creation"}}]},{"text":".","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"createGeneratedClock if a clock is generated inside the fabric. Refer to ","type":"text"},{"text":"#Sta_constraints_Generated_clock_creation","type":"text","marks":[{"type":"link","attrs":{"href":"#Sta_constraints_Generated_clock_creation"}}]},{"text":".","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"addFalsePath in order to remove paths to ignore. Refer to ","type":"text"},{"text":"#Sta_constraints_Path_between_registers","type":"text","marks":[{"type":"link","attrs":{"href":"#Sta_constraints_Path_between_registers"}}]},{"text":".","type":"text"}]}]}]},{"type":"heading","attrs":{"level":2},"content":[{"text":"TimingDriven","type":"text"}]},{"type":"paragraph","content":[{"text":"TimingDriven option can be set with the following constraint:","type":"text"}]},{"type":"codeBlock","content":[{"text":"p.setOption('TimingDriven','Yes')","type":"text"}]},{"type":"paragraph","content":[{"text":"In addition, the number of iterations in a row to achieve timing goals can be modified through TimingEffort option with the example following constraint:","type":"text"}]},{"type":"codeBlock","content":[{"text":"p.setOption('TimingEffort','Medium')","type":"text"}]},{"type":"paragraph","content":[{"text":"Analysis conditions must be set before launching the tool with the example following constraint:","type":"text"}]},{"type":"codeBlock","content":[{"text":"p.setAnalysisConditions('typical')","type":"text"}]},{"type":"paragraph","content":[{"text":"The number of iterations complies with the following association:","type":"text"}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Low: TimingDriven is disabled","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Medium: 3 iterations","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"High: 6 iterations","type":"text"}]}]}]},{"type":"paragraph","content":[{"text":"The higher the number of iterations is, the higher STA performances can be. However, higher is the runtime.","type":"text"}]},{"type":"panel","attrs":{"panelType":"warning"},"content":[{"type":"paragraph","content":[{"text":"All clocks must be created before launching Place&Route with TimingDriven option. Otherwise, the tool does not get performances to reach.","type":"text"}]}]},{"type":"panel","attrs":{"panelType":"warning"},"content":[{"type":"paragraph","content":[{"text":"The TimingDriven efficiency is in continuous development and improvement.","type":"text"}]}]},{"type":"heading","attrs":{"level":2},"content":[{"text":"Floor planning","type":"text"}]},{"type":"paragraph","content":[{"text":"In order to give indications to the tool, the user can set up a floor-planning and pass it through the tool working directly on the whole design or working with unitary runs before integrating in the top design as specified in ","type":"text"},{"text":"#Floor_planning_Preplace_ip","type":"text","marks":[{"type":"link","attrs":{"href":"#Floor_planning_Preplace_ip"}}]},{"text":".","type":"text"}]},{"type":"paragraph","content":[{"text":"First of all, ConstrainModule method as explained in ","type":"text"},{"text":"#Floor_planning_Constrain_module","type":"text","marks":[{"type":"link","attrs":{"href":"#Floor_planning_Constrain_module"}}]},{"text":" must be applied in order to concentrate parts of the design and place them close to other ones if there are interconnections between them.","type":"text"}]},{"type":"paragraph","content":[{"text":"In addition, ConstraintPath method as explained in ","type":"text"},{"text":"#Floor_planning_Constrain_path_between_registers","type":"text","marks":[{"type":"link","attrs":{"href":"#Floor_planning_Constrain_path_between_registers"}}]},{"text":" must be applied if some paths go trough multiple modules or for critical paths.","type":"text"}]},{"type":"panel","attrs":{"panelType":"warning"},"content":[{"type":"paragraph","content":[{"text":"With this solution, the user must pay attention to interconnections between modules and between modules and the ring device.","type":"text"}]}]},{"type":"heading","attrs":{"level":2},"content":[{"text":"Logic depth reducing","type":"text"}]},{"type":"paragraph","content":[{"text":"The highest the required frequency is, the lowest the number of combinatorial elements between 2 registers must be. ","type":"text"}]},{"type":"paragraph","content":[{"text":"It can be iterative to control the logic depth of a design by using the method explained in ","type":"text"},{"text":"#Design_complexity","type":"text","marks":[{"type":"link","attrs":{"href":"#Design_complexity"}}]},{"text":" and adapt the code if the required frequency cannot be achieved.","type":"text"}]}],"version":1}

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