Table of Content

This document aims at giving guidelines on how to use the provided NX components in VHDL source code for NXmap3. Its purpose is to explain how to correctly instantiate the different supported NX components provided by NanoXplore for NXmap3 synthesis and implementation tools.

For each NX component, the reader will find a quick introduction and a description of both the generics and ports. He will also find a diagram of the component with an instantiation example in VHDL.

Clocks distribution and management

NX_BD

Description

The NX_BD component describes a Buffer Driver circuit that allows the user to direct the routing of a signal to the general routing or low-skew network.

Generics

mode

type string

default value “local_lowskew”

If mode is set to “local_lowskew”, the output signal is routed to local low skew network at TILE level.

If mode is set to “global_lowskew”, the output signal is routed to global low skew network of fabric.

Ports

Ports	Direction	Type	Description
I	input	std_logic	Input signal
O	output	std_logic	Output signal

Example

This documentation only provides the instantiation of the component.

BD_0 : NX_BD

port map (

      I => CK_GEN

    , O => CK_LS

);

NX_CKS

Description

The NX_CKS component describes a ClocK Switch circuit that allows glitch free clock generation. It can be used to enable/disable the clock to part of the user’s logic – providing that the output signal will be glitch free – and the delay from the main clock to the generated one is un-significant.

See the following figure for a detailed chronogram.

The NX_CKS can be used exclusively by instantiation. The current version of NXmap does not yet support inference for this device.

CKS chronograms

The blue internal signals are CMD signal sampled on rising edge (SPL1) and then sampled on falling edge (SPL0). SPL0 is the final enable.

Ports

Ports	Direction	Type	Description
CKI	input	std_logic	Input clock
CMD	input	std_logic	Command
CKO	output	std_logic	Output clock

Example

This documentation only provides the instantiation of the component.

CKS_0 : NX_CKS

port map (

      CKI => CK

    , CMD => ENABLE

    , CKO => CKG

);

NX_PLL (NG-MEDIUM)

Description

The NX_PLL component describes a Phase Locked Loop circuit available in NG-MEDIUM. The PLL just as the WaveForm Generators (WFG) is part of the ClocK Generator block (also called CKG). There are 4 CKG blocks, on in each corner of the FPGA die.

Each CKG is composed of one PLL and eight WFG.

Simplified PLL block diagram

PLL inputs:

REF: input reference clock. The input reference clock enters in the REF pin.
FBK: The feedback can be external (via clock tree connected to the FBK pin) for phase controlled outputs, or internal to the PLL (no phase control or adjustment of the generated clocks with the REF pin).

If REF pin is connected to a PAD, please declare the pad with Turbo mode enabled.

PLL outputs:

VCO: the output of the VCO
D1, D2 and D3 : three outputs generated by frequency division of the VCO output
OSC: Internal 200 MHz oscillator output (used for delays calibration on the PLL feedback path, WFG internal delays and input/output delays). OSC output can also be used as auxiliary clock.
RDY: status pin. Goes high when the PLL is locked

PLL detailed description and settings:

The next figure shows a more detailed view of the PLL, and the attributes used to configure its functionality.

PLL block diagram and settings

The PLL can generate a set of user’s defined clocks which frequencies are based on the REFerence input clock, with multiply and/or divide factors.

The PLL outputs connect directly with the WaveForm Generators (WFG) of the same ClocK Generator (CKG) for clock buffering and added clock generation flexibility.

The REFerence clock can be optionally divided by 2. This divider can be used for example to maintain the VCO input frequency in the allowed range (20 to 100 MHz): Assuming that F(ref) = 150 MHz, setting the divider by 2 allows the VCO to see a 75 MHz frequency.

FeedBacK (FBK pin): The feedback can be internal or external.

When external, the feedback must be done by using a clock tree (low skew network). The internally generated clocks can be rising edge aligned with the reference clock input pad (highly recommended to optimize the communications with external components like memories, ADCs, DACs). An optional divider by 2 is included in the external feedback path (user’s selected by setting the “vco_fbkdiv” generic to ‘1’)

If internal feedback is chosen, the FBK input pin must be left open. The internal feedback path includes three dividers.

Divider by 2 (cannot be bypassed)
User’s programmable integer divider (nDiv – can divide in the range 2 to 31). See fbk_intdiv generic explanations.
Additional optional divider by 2 (user’s selected by setting the “vco_fbkdiv” generic to ‘1’). This divider is also included in the external feedback path.

A user’s programmable delay chain allows to delay the feedback to the VCO feedback. This feature can be used to fine tune the rising edge alignment of the generated clocks with the REFerence input pad, when external feedback is used – with clock tree. Each delay step is 159 ps. The user can select 0 to 63 steps.

VCO (PLL core)
- The VCO generates a frequency in the range 200 MHz to 1200 MHz.
- There are 3 frequency ranges, 200 MHz to 425 MHz, 400 MHz to 850 MHz and 800 to 1200 MHz.
- The VCO range is defined by the “vco_range” attribute. NanoXplore recommends to choose preferably the lowest possible range when the VCO frequency value is in the overlap between two ranges.

Divided outputs
- There are 3 additional outputs (D1, D2 and D3). Each output has a programmable divider by powers of 2, in the range 1 to 128 (1, 2, 4, 8, 16, 32, 64 or 128).

Internal 200 MHz oscillator (precision and stability over PVT around 10%)
- Can be used as auxiliary clock
- In addition, this oscillator is used by NXmap to calibrate the programmable delays available in :
  - PLL feedback path
  - WFG (to delay the clocks)
  - IOs input, output and tri-state command paths (complex IO banks only)

Generics

location

type string

default value “” (no location constraint)

This generic allows to define the NX_PLL location directly in the source code (instead of with the addPLLLocation method)

Example : location => “CKG2.PLL1”,

vco_range (1)

type integer (range 0 to 2)

default value 0

This generic configures the VCO frequency range. The value must be in range 0 to 2 according to the following ranges:

vco_range	VCO frequency		Unit
vco_range	Min	Max	Unit
0	200	425	MHz
1	400	850	MHz
2	800	1200	MHz

ref_div_on (2)

type bit

default value ‘0’

This generic configures whether the input reference frequency is divided by 2 (vco_refdiv = ‘1’) or not (vco_refdiv = ‘0’).

It can be useful to maintain the input reference clock, and the VCO frequencies into their respective ranges.

ref_div_on	Reference frequency range		Unit
ref_div_on	Min	Max	Unit
‘0’	20	100	MHz
‘1’	40	200	MHz

ext_fbk_on (3)

type bit

default value ‘0’

When ‘0’, the internal feedback path is selected. The nDivider whose value is defined by fbk_intdiv and associated pre-divider by 2 are then used.

When ‘1’, the external feedback path is selected. This can be useful to ensure rising edges alignment of the REFerence input clock pad and internal clock trees for fully synchronous behavior with external source and destination components.

fbk_div_on (4)

type bit

default value ‘0

This generic configures whether the VCO feedback frequency is divided by 2 (‘1’) or not (‘0’). See also fbk_intdiv to set the global division factor on the internal feedback path.

fbk_delay_on (5)

type bit

default value ‘0’

This generic configures whether the delay of the feedback path is active (‘1’) or not (‘0’).

fbk_delay (6)

type integer (range 0 to 63)

default value 0

The number of delay taps on the feedback path (internal or external) can be adjusted to meet the required phase on the VCO outputs. When using external feedback, it can be used to compensate the delay on the reference clock input to the REF pin of the PLL via the semi-dedicated clock input pin and associated direct routing.

The delay can be selected or not (see fbk_delay_on). When selected, it can be adjusted from 340 ps (fbk_delay = 0) to 10 400 ps (fbk_delay = 63) by steps of 160 ps.

fbk_intdiv (7)

type integer (range 1 to 15 or 2 to 31)

default value 0

This generic allows to define (together with fbk_div_on) the division factor of the VCO frequency on the internal feedback path.

fbk_intdiv (nDivider)	fbk_div_on	Division factor on feedback path
0	‘0’	Not allowed
1	‘0’	Not allowed
2	‘0’	4
3	‘0’	6
...	‘0’	...
30	‘0’	60
31	‘0’	62

0	‘1’	Not allowed
1	‘1’	4
2	‘1’	8
3	‘1’	12
...	‘1’	...
14	‘1’	56
15	‘1’	60
16 to 31	‘1’	Not allowed

clk_outdiv1 (8)

type integer (range 0 to 7)

default value 0

This generic allows to define the divider value of the D1 output. There are 8 possible values, 1, 2, 4, 8, 16, 32, 64 and 128 (2**clk_outdiv(1))

If clk_outdiv(1) = 0 (default value)

D1_output_frequency = Fvco/(2**0) = Fvco

If clk_outdiv(1) = 7

D1_output_frequency = Fvco/(2**7) = Fvco/128

clk_outdiv2 (9)

type integer (range 0 to 7)

default value 0

This generic allows to define the divider value of the D2 output. There are 8 possible values, 1, 2, 4, 8, 16, 32, 64 and 128 (2**clk_outdiv(2))

If clk_outdiv(2) = 0 (default value)

D2_output_frequency = Fvco/(2**0) = Fvco

If clk_outdiv(2) = 7

D2_output_frequency = Fvco/(2**7) = Fvco/128

clk_outdiv3 (10)

type integer (range 0 to 7)

default value 0

This generic allows to define the divider value of the D3 output. There are 8 possible values, 1, 2, 4, 8, 16, 32, 64 and 128 (2**clk_outdiv(3))

If clk_outdiv(3) = 0 (default value)

D3_output_frequency = Fvco/(2**0) = Fvco

If clk_outdiv(3) = 7

D3_output_frequency = Fvco/(2**7) = Fvco/128

Notes about user’s adjustable delays on NG-MEDIUM:

The PLL have a user’s selectable and adjustable (no delay or 0 to 63 x 160 ps +/- 5% delay taps) on the feedback path. A similar delay chain is available in each WFGs. Finally the IO banks have input, output and tri-state command 64-tap delay chains.

All the delay chain taps are calibrated with the same procedure and hardware resources.

The procedure is transparent to the user.

The delays calibration system uses the PLL 200 MHz oscillator output as reference clock to calibrate all delays: feedback path in the PLL itself, WFG delays in same CKG), and IO delays in the two neighboring complex and simple IO banks:

CKG1 oscillator calibrates the delays in CKG1 (PLL + WFGs) and IO banks 0, 12 and 11
CKG2 oscillator calibrates the delays in CKG2 (PLL + WFGs) and IO banks 1, 2 and 3
CKG3 oscillator calibrates the delays in CKG3 (PLL + WFGs) and IO banks 4, 5, 6 and 7
CKG4 oscillator calibrates the delays in CKG4 (PLL + WFGs) and IO banks 8, 9 and 10

The calibration procedure takes about 10 µs at startup. No status is available on NG-MEDIUM.

Ports

Ports

Direction

Type

Description

REF

In

std_logic

Reference clock input

Connectivity: semi-dedicated clock inputs, clock trees (low skew network)

Note: If REF pin is connected to a PAD, please declare the pad with Turbo mode enabled.

FBK

In

std_logic

External FeedBack input

Connectivity: semi-dedicated clock inputs, clock trees (low skew network)

VCO

Out

std_logic

VCO output : Fvco = fbk_intdiv * 2**(fbk_div_on - ref_div_on + 1) * clk_ref_freq

Connectivity: WFG inputs

D1…D3

Out

std_logic

Divided clocks. Fvco frequency divided by 1, 2, 4, 8, 16, 32, 64 or 128

Important note: D1, D2 and D3 outputs are reset while PLL RDY is not asserted.

Connectivity: WFG inputs

OSC

Out

std_logic

Internal 200 MHz oscilator

Connectivity :WFG inputs, delay calibration system

RDY

Out

std_logic

High when PLL is locked

Connectivity: RDY inputs of WFGs, fabric…

Instantiation Example

This documentation only provides the instantiation of the component.

-- targetFreq = (refFreq * (2 * fbk_intdiv)) / (2^clk_outdiv1)) 

-- 12.5 MHz = (25 MHz * (2 * 4) / (2^4)) 

-- 50 MHz = (25 MHz * (2 * 4) / (2^2)) 

-- 

-- Please note that (refFreq * (2 * fbk_intdiv)) must be above 200 MHz and below 1200 MHz 

PLL_0 : NX_PLL 

   generic map ( 

        location    => “CKG1.PLL1”

      ,  fbk_intdiv  => 4 

      , clk_outdiv1 => 4  -- Divide by 2**4 = 16

      , clk_outdiv2 => 2  -- Divide by 2**2 = 4

   ) 

port map ( 

      REF => ck25MHz 

    , FBK => OPEN 

    , VCO => OPEN,

    , D1  => ck12_5MHz

    , D2  => ck50MHz

    , D3  => OPEN 

    , OSC => OPEN 

    , RDY => OPEN 

  );

Simulation

The NX_PLL VHDL simulation model is included in the NxLibrary (NxPackage.vhd). It allows to simulate any one of the possible NX_PLL configurations.

NX_PLL_L (NG-LARGE)

Description

The NX_PLL_L component describes a Phase Locked Loop circuit available in NG-LARGE The PLL just as the WaveForm Generators (WFG) is part of the ClocK Generator block (also called CKG). There are 4 CKG blocks, on in each corner of the FPGA die.

Each CKG is composed of one PLL and ten WFG.

NG-LARGE CKG block diagram

The next figure shows a block diagram of the NX_PLL_L and the user’s settings (in yellow).

Simplified NG-LARGE PLL block diagram

PLL inputs:

REF: input reference clock. The input reference clock enters in the REF pin. (20MHz to 50MHz max)
FBK: The feedback can be external (via clock tree connected to the FBK pin) for phase controlled outputs, or internal to the PLL (no phase control or adjustment of the generated clocks with the REF pin).

If REF pin is connected to a PAD, please declare the pad with Turbo mode enabled.

PLL outputs:

VCO: the output of the VCO
DIVP1, DIVP2 and DIVP3 : three outputs generated by frequency division (power of 2) of the VCO output
DIVO1 and DIVO2 : two additional outputs generated by frequency division (odd ratio) of the VCO output
LDFO : This is the output of the internal feedback divider (divides by (fbk_intdiv + 2) * 2 ). Note that LDFO output can be also directed to WFG for clock generation, and the used as external feedback.

OSC: 200 MHz output coming from 400MHz internal oscillator (used for delays calibration on the PLL feedback path, WFG internal delays and input/output delays). OSC output can also be used as auxiliary clock.

PLL_LOCKED: status pin. Goes high when the PLL is locked
CAL_LOCKED : this output goes high when the automatic process of delay calibration has completed (PLL and internal delays as well as neighboring IO banks delay)

Generics

location

type string

default value “”

This generic allows to define the NX_PLL_L location directly in the source code (instead of with the nxpython addPLLLocation method).

Example : location => “CKG2.PLL1”

cfg_use_pll

type bit

default value '1'

Set to 1 to enable the PLL. When set to 0, the PLL is bypassed with Fvco = Frefo.

ref_intdiv

type integer (range 0 to 31)

default value 0

The REFerence frequency can be divided by factors ranging from 1 to 32 be fore reaching the VCO input. This allows to give more flexibility of the PLL generated output frequency, and increase the PLL input frequency range.

ref_intdiv value	Vco input frequency	REF frequency range
0	Fref	20 to 50 MHz
1	Fref / 2	40 to 100 MHz
2	Fref / 3	60 to 150 MHz
3	Fref / 4	80 to 200 MHz

29	Fref / 30
30	Fref / 31
31	Fref / 32

ref_osc_on

type bit

default value ‘0’

This generic configures the source of the PLL reference.

If ref_osc_on is set to ‘0’, the input reference of the pll is the REF input pin.

If set to ‘1’, the internal oscillator is used as reference of the PLL.

ext_fbk_on

type bit

default value ‘0’

When ‘0’, the internal feedback path is selected. The output of the FBK_INTDIV divider is used as feedback source. The VCO output frequency is divided by (fbk_intdiv + 2) * 2

When ‘1’, the external feedback path is selected. This is particularly useful for “zero delay” clock generation.

fbk_intdiv

type Integer range 0 to 31

default value 2

fbk_intdiv	Division factor on internal feedback path
0	4
1	6
2	8
3	10
...	...
30	64
31	66

fbk_delay_on

type bit

default value ‘0’

This generic configures whether the delay of the feedback path is active (‘1’) or not (‘0’).

fbk_delay

type integer (range 0 to 63)

default value 0

The number of delay taps on the feedback path (internal or external) can be adjusted to meet the required phase on the VCO outputs. When using external feedback, it can be used to compensate the delay on the reference clock input to the REF pin of the PLL via the semi-dedicated clock input pin and associated direct routing.

The delay can be selected or not (see fbk_delay_on). When selected, it can be adjusted from 340 ps (fbk_delay = 0) to 10 400 ps (fbk_delay = 63) by steps of 160 ps.

clk_outdivp1 : applies to DIVP1

type integer (range 0 to 7)

default value 0

This generic allows to define the divider value of the DIVP1 output. There are 8 possible values, 1, 2, 4, 8, 16, 32, 64 and 128 (2**clk_outdivp1)

If clk_outdivp1 = 0 (default value)

DIVP1_output_frequency = Fvco/(2**0) = Fvco

If clk_outdivp1 = 7

DIVP1_output_frequency = Fvco/(2**7) = Fvco / 128

clk_outdivp2 : applies to DIVP2

type integer (range 0 to 7)

default value 0

This generic allows to define the divider value of the DIVP2 output. There are 8 possible values, 2, 4, 8, 16, 32, 64, 128 and 256 (2**(clk_outdivp2 + 1))

If clk_outdivp2 = 0 (default value)

DIVP2_output_frequency = Fvco/(2**(0 + 1)) = Fvco / 2

If clk_outdivp2 = 7

DIVP2_output_frequency = Fvco/(2**(7 + 1)) = Fvco / 256

clk_outdivp3o2 : applies to DIVP3 and DIVO2 dividers

type integer (range 0 to 7)

default value 0

This generic allows to define the divider value of both DIVP3 and DIVO2 outputs. There are 8 possible values for each divider :

DIVP3 division ratio = 4, 8, 16, 32, 64, 128, 256 and 512 (2**(clk_outdivp3o2 + 2))

If clk_outdivp3 = 0 (default value)

DIVP3_output_frequency = Fvco/(2**(0 + 2)) = Fvco / 4

If clk_outdivp3 = 7

DIV3_output_frequency = Fvco/(2**(7 + 2)) = Fvco / 512

DIVO2 division ratio = 5, 7, 9, 11, 13, 15, 17 and 19 ((2 * clk_outdivp3o2) + 5)

If clk_outdivp3o2 = 0 (default value)

DIVO2_output_frequency = Fvco/((2 * 0) + 5) = Fvco / 5

If clk_outdivp3o2 = 7

DIVO2_output_frequency = Fvco/((2 * 7) + 5) = Fvco / 19

clk_outdivo1 : applies to DIVO1

type integer (range 0 to 7)

default value 0

This generic allows to define the divider value of the DIVO1 output. There are 8 possible values, 3, 5, 7, 9, 11, 13, 15 and 17 ((2*clk_outdivo1) + 3)

If clk_outdivo1 = 0 (default value)

DIVO1_output_frequency = Fvco/((2 * 0) + 3) = Fvco / 3

If clk_outdivo1 = 7

DIVO1_output_frequency = Fvco/((2 * 7) + 3) = Fvco / 17

Notes about user’s adjustable delays on NG-LARGE:

The PLL have a user’s selectable and adjustable delay line (no delay or 0 to 63 x 160 ps +/- 5% delay taps) on the feedback path. A similar delay chain is available in each WFGs. Finally the IO banks have input, output and tri-state command 64-tap delay chains.

All the delay chain taps are calibrated with the same automatic process and hardware resources.

The procedure is transparent to the user.

The delays calibration system uses the PLL 200 MHz output coming from oscillator as reference clock to calibrate all delays: feedback path in the PLL itself, WFG delays in same CKG), and IO delays in the two neighboring complex and simple IO banks:

CKG1 oscillator calibrates the delays in CKG1 (PLL + WFGs)
- Banks 19 to 23 (complex)
CKG2 oscillator calibrates the delays in CKG2 (PLL + WFGs)
- Banks 0 to 5 (simple)
CKG3 oscillator calibrates the delays in CKG3 (PLL + WFGs)
- Banks 6 to 10 (complex)
CKG4 oscillator calibrates the delays in CKG4 (PLL + WFGs)
- Banks 11 to 18 (simple)

The calibration procedure takes about 10 µs at startup. The “CAL_LOCKED” output goes high when the delay calibration process is complete. Can be used as status bit.

Ports

Ports

Direction

Type

Description

Library guide NG-MEDIUM/NG-LARGE

Table of Content

List of figures

Introduction

Clocks distribution and management

NX_BD

Description

Generics

Ports

Example

NX_CKS

Description

Ports

Example

NX_PLL (NG-MEDIUM)

Description

Generics

Ports

Instantiation Example

Simulation

NX_PLL_L (NG-LARGE)

Description

Generics

Ports