DevKitV2 User Guide
Revision | Date | Originator | Comments |
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1.04 | 04/04/2018 | Hervé Baier | Added notes about interfaces dictionary |
1.03 | 03/14/2018 | Christian Magne | Minor changes |
1.02 | 02/21/2018 | Christian Magne | Added missing FMC J/K columns |
1.01 | 01/08/2018 | Christian Magne | Corrected some typo errors, J3 pinout |
1.0 | 10/10/2017 | Christian Magne | DevKit V1 - > V2 evolution |
Table of Content
- 1 Table of Content
- 2 List of figures
- 3 Introduction
- 4 Background and Objectives
- 5 DevKit board overview
- 5.1 Board geometry
- 5.2 Board hardware overview
- 5.2.1 Configuration interfaces
- 5.2.2 Clocking options
- 5.2.3 Supervision functions
- 5.2.4 On-board devices
- 5.2.5 Expansion connectors
- 5.3 Brave chip implementation
- 5.3.1 Socket capability
- 5.3.2 Banks repartition
- 5.4 Detailed board features
- 5.4.1 User clocks
- 5.4.2 User input devices
- 5.4.3 User LEDs
- 5.5 Connectors pinouts
List of figures
Introduction
Scope of the document
This document describes NanoXplore BRAVE/NX1H35 CLGA625 Development Kit, V2 board.
Applicable and Reference Document
Applicable and Reference Document (ADs)
Reference Documents (RDs)
Background and Objectives
General Background
The DevKit is a demonstration board for Brave NG_MEDIUM CLGA625 chip.
Board has been upgraded from V0 to V1 for 2 reasons:
- mechanical dimensions had to be increased to ease production : surface-mount connectors were too close to the board edge.
- FMC connector orientation was wrong.
Board has been upgraded from V1 to V2 in September 2017, with the following changes:
- Due to an early documentation error, SpaceWire I/Os distribution on complex banks were erroneous, so DevKit V1 SpaceWire performance won’t reach the 400Mbit/S target. On DevKit V2, User1 and User2 SpaceWire connectors have access to the integrated SpaceWire-enhanced functions of the complex bank.
- The correction for the not-fully-asynchronous JTAG reset has been integrated (schottky diode providing a single JTAG clock pulse on RST_N rising edge).
- Calibration resistors have been added on 3 complex banks’ D06N_CAL I/O.
- VDDSENSE voltage measurement has been added.
- Primary 12V input current measurement has been added.
Three V0 boards have been produced in November 2016, using 1st run NG_MEDIUM silicon.
Thirty V1 boards have been produced with 2nd run chips, after mask fix.
Objectives of the Document
DevKit board overview
Board geometry
Brave NG_MEDIUM CLGA625 DevKit V2 is a 153 x 130 mm board
Board hardware overview
Configuration interfaces
The DevKit is an evaluation board to be used either interactively through JTAG, or standalone from an EEPROM board. The board configuration mode is thus selected by on-board jumpers.
The JTAG connector receives a 26-pin ribbon cable from NanoXplore Angie USB-JTAG interface, providing:
- The 5 JTAG signals TRST-, TMS, TCK, TDI, TDO
- An I²C interface
- A target RST_N signal
- A connection to the mode bits, for readback and optionnal override
JTAG slave configuration is available in any other mode.
A 10-pin HE10 connector is provided to receive an EEPROM memory board (Atmel Dump Mode EEPROM or standard SPI EEPROM).
An optional SpaceWire connector allows SpaceWire configuration
Clocking options
Brave DevKit provides the following clocking options:
- Osc0 – U3 25MHz clock oscillator
- Osc1 – U4 Clam-shell socket for a user-supplied 2.5V 7x5mm clock oscillator
- Clk0 – J8 external SMA clock input
- Clk1 – J9 external SMA clock input
Supervision functions
The I²C interface is used for misc control and supervision functions.
- board identification: 24LC128 I²C serial identification EEPROM
- power supply voltages and current monitoring:
two ADG728 I²C analog muxes
one ADS1115 4-channel I²C ΔΣ A/D converter
- temperature measurement: LM73 I²C temp sensor
On-board devices
The board provides:
- a 128Mx16 DDR2 memory chip (Micron MT47H128M16RT)
- 6 switches
- 5 pushbuttons
- 19 LEDS
- a 2.5V, 7x5mm, 25 MHz clock oscillator
- a socket for a user-selected 2.5V, 7x5mm clock oscillator
Expansion connectors
The board provides:
- two optional user SpaceWire connectors
- one Altera HSMC mezzanine connector
- one VITA-57 FMC connector
Brave chip implementation
Socket capability
Brave DK625 DevKit board may be delivered with either a soldered chip or an Ironwood spring-pin clam-shell CLGA625 socket.
Banks repartition
All Brave I/Os are connected on the board.
Simple Banks 0 and 1 are 3.3V powered
Complex Banks 2, 3, 4 and 5 (J6 HSMC connector) are powered with HSMC supply, factory-set to 2.5V with VDD/2 termination voltage
Simple Banks 6, 7, 8 and Complex Bank 9 (J7 FMC connector) are powered with FMC supply, factory-set to 2.5V with VDD/2 termination voltage
Complex Banks 10 and 11 are 1.8V powered with VDD/2 termination voltage, and dedicated to the DDR2 memory chip and input switches
Complex Bank 12 is 2.5V powered with VDD/2 termination voltage, and handles both user SpaceWire connectors and the clock oscillators.
Detailed board features
The user can find all the pads definition for NX1H35 development kit board DK625V2 in the provided NX1H35_EK_V2.py file.
User clocks
DK625 board clock sources | ||||
Source | Voltage | Frequency | Signal | FPGA I/O |
U3 oscillator | 2.5V | 25 MHz | OSC0 | IO_B12D09P |
U4 oscillator socket | 2.5V | User def. | OSC1 | IO_B12D08P |
J8 ext SMA input | 3.3V | User def. | CLK0 | IO_B0D10P |
J9 ext SMA input | 3.3V | User def. | CLK1 | IO_B0D11P |
User input devices
Switches and pushbuttons use Bank10 I/Os (1.8V powered)
Switches |
| Pushbuttons | |||||
S5 |
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| S6 |
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| S11 |
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S1 | S2 | S3 | S4 |
| S8 | S9 | S10 |
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| S12 |
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Switches |
| Pushbuttons | ||||
Sw | Signal | FPGA I/O |
| Sw | Signal | FPGA I/O |
S1 | PA09 | IO_B10D09P |
| S8 | PA07 | IO_B10D07P |
S2 | PA03 | IO_B10D03P |
| S9 | PA12 | IO_B10D12P |
S3 | NA03 | IO_B10D03N |
| S10 | NA07 | IO_B10D07N |
S4 | PA04 | IO_B10D04P |
| S11 | NA12 | IO_B10D12N |
S5 | NA09 | IO_B10D09N |
| S12 | PA14 | IO_B10D14P |
S6 | NA04 | IO_B10D04N |
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User LEDs
User LEDs – Banks 0 and 1 | ||||||
LED | Signal | FPGA I/O |
| LED | Signal | FPGA I/O |
1 | LD1_N | IO_B0D01P |
| 5 | LD5_N | IO_B1D05P |
2 | LD2_N | IO_B0D03N |
| 6 | LD6_N | IO_B1D06N |
3 | LD3_N | IO_B0D03P |
| 7 | LD7_N | IO_B1D06P |
4 | LD4_N | IO_B1D05N |
| 8 | LD8_N | IO_B1D02N |
User LEDs – Prog Bank (added on DK625V1 board) | |||
LED | Signal | FPGA I/O | Interface |
9 | LD9_N | D0 | USER_D0 |
10 | LD10_N | D1 | USER_D1 |
11 | LD11_N | D2 | USER_D2 |
12 | LD12_N | D3 | USER_D3 |
13 | LD13_N | D4 | USER_D4 |
14 | LD14_N | D5 | USER_D5 |
15 | LD15_N | D6 | USER_D6 |
16 | LD16_N | D7 | USER_D7 |
17 | LD17_N | CS_N | USER_CS_N |
18 | LD18_N | WE_N | USER_WE_N |
19 | LD19_N | DATA_OE | USER_DATA_OE |
Unlike standard FPGA I/Os, declared in pads dictionary, these LEDs are accessed through direct connections to the fabric, declared in interfaces dictionary.
Connectors pinouts
Flash expansion connector
J2 Serial PROM expansion connector | ||||
Pin | Pad | Dump Mode | SPI Mode | SPI VCC Mode |
1 | D9 | CLOCK | CLOCK | CLOCK |
2 | D12 | RDY | Prog LED | Prog LED |
3 | GND | GND | GND | GND |
4 | D11 | RST/OE | MOSI | MOSI |
5 | D13 | SER_EN | - | Vcc0 |
6 | VCC | VCC | VCC | Unused |
7 | D15 | - | - | Vcc2 |
8 | D14 | Prog LED | - | Vcc1 |
9 | D10 | MISO | MISO | MISO |
10 | D8 | CS_N | CS_N | CS_N |
SpaceWire interfaces
J3 – Configuration SpaceWire connector – Prog Bank (2.5V) | ||||||
Pin | Signal | FPGA I/O |
| Pin | Signal | FPGA I/O |
1 | DINP | DIN_P |
| 6 | DINN | DIN_N |
2 | SINP | SIN_P |
| 7 | SINN | SIN_N |
3 | Shield |
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4 | SOUN | SOUT_N |
| 8 | SOUP | SOUT_P |
5 | DOUN | DOUT_N |
| 9 | DOUP | DOUT_P |
J4 – User1 SpaceWire connector – Bank 12 (2.5V) | ||||||
Pin | Signal | FPGA I/O |
| Pin | Signal | FPGA I/O |
1 | U1DIP | IO_B12D03P |
| 6 | U1DIN | IO_B12D03N |
2 | U1SIP | IO_B12D04P |
| 7 | U1SIN | IO_B12D04N |
3 | Shield |
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4 | U1SON | IO_B12D02N |
| 8 | U1SOP | IO_B12D02P |
5 | U1DON | IO_B12D01N |
| 9 | U1DOP | IO_B12D01P |
J5 – User2 SpaceWire connector – Bank 12 (2.5V) | ||||||
Pin | Signal | FPGA I/O |
| Pin | Signal | FPGA I/O |
1 | U2DIP | IO_B12D14P |
| 6 | U2DIN | IO_B12D14N |
2 | U2SIP | IO_B12D15P |
| 7 | U2SIN | IO_B12D15N |
3 | Shield |
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4 | U2SON | IO_B12D13N |
| 8 | ||
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