Synopsys Design Constraint (SDC)
create_clock
Creates a clock and defines its waveform.
create_clock [-name clock_name]
[-period float]
[-waveform <edge_list>]
<source>
Arguments:
Name | Description |
-name | Specifies the name of the clock. |
-period | Specifies the length of the clock period. |
-waveform | Specifies the rise and fall edge times of the clock waveform over one clock period. The first value corresponds to the first rising transition after time zero. The numbers should represent one full clock period. |
source | The query which specifies how to get a clock related point. A valid query can be: |
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Examples:
The following example creates two clocks on ports clk1 and clk2 with a period of 8, a rising edge at 0, and a falling edge at 4:
create_clock -period 8 clk1
create_clock –period 8 –waveform {0 4} {clk2}The following example creates a clock on port clk3 with a period of 7, a rising edge at 2, and a falling edge at 4:
create_clock –period 7 –waveform {2 4} [get_ports {clk3}]Please note that virtual clocks are not handled by Nxmap.
create_generated_clock
Creates a new clock signal from the clock waveform of a given pin in the design.
create_generated_clock [-divide_by integer]
[-duty_cycle float]
[-edge_shift float list]
[-edges integer list]
[-invert]
[-multiply_by integer]
[-name clock_name]
[-offset float]
[-phase unsigned]
[-source {port | pin}]
<target>
Arguments:
Name | Description |
-divide_by | Determines the frequency of the new clock by dividing the frequency of the source clock by this factor. The value must be greater or equal to 1. Default value is 1 |
-duty_cycle | Specifies the duty cycle (high pulse width) as a percentage of the clock period. The range must be between 1 and 99. Default value is 50.0 |
-edge_shift | Specifies how much each edge specified with the |
-edges | Selects a list of edges from the source clock that form the edges of the derived clock. You must specify an odd number of edges. The last edge represents the first edge of the next clock period. You cannot specify this option with either the |
-invert | Inverts the resulting waveform of the generated clock. |
-multiply_by | Determines the frequency of the new clock by multiplying the frequency of the source clock with this factor. The value must be greater or equal to 1. Default value is 1 |
-name | Specifies the name of the generated clock. |
-offset | Specifies the offset for the rising edge. |
-phase | Specifies the phase of the generated clock. The range must be from 0 to 359 |
-source | Specifies the name of the pin from which the clock must be derived. A valid argument can be: |
target | Specifies how to get a clock related point. A valid argument can be: |
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Examples:
The following example creates a generated clock on pin register_1 with a period twice as long as the period at the reference port clock
create_generated_clock –divide_by 2 –source [get_ports {clock}] [get_registers {register_1}]The following example creates a generated clock at the pin ck with a period ¾ of the period at the reference port clock
set_clock_groups
Specifies the groups of clocks between which timing analysis will not be done.
set_clock_groups [-asynchronous]
[-exclusive]
[-group]
Arguments:
Name | Description |
asynchronous | Defines clock group with asynchronous clocks. Asynchronous clocks have no specified phase relationship. |
exclusive | Defines clock group with clocks that cannot exist in the design at the same time. |
group | Specifies a group of clocks. |
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Examples:
set_false_path
Identifies false paths in a design, and breaks or disables specific instance timing arcs in a design resulting in them not being timed.
set_false_path [-from source_name]
[-to target_name]
[-group]
Arguments:
Name | Description |
|---|---|
from | Specifies how to get a timing path starting points. A valid timing starting point is an input port or a register. A valid argument can be: |
to | Specifies how to get a timing path ending points. A valid timing ending point is an output port or a register. A valid argument can be: |
group | Specifies a group of clocks. Specify at least two clocks. |
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Examples:
set_input_delay
Constrains input and in/out (bidirectional) ports, port busses, and pins (that are valid start points) within the design relative to a clock edge. If you omit both the -min and -max options, the delay is assumed to apply for both setup and hold analysis.
set_input_delay [-clock clock_name]
[-clock_fall ]
[-max float]
[-min float]
<delay>
<ports>
Arguments:
Name | Description |
|---|---|
clock | Specifies the clock reference to which the specified input delay is related. This is a mandatory argument. |
clock_fall | Specifies that input delay is relative to the falling edge of the clock. When it is not set, the delay is applied on the rising edge of the clock. |
max | Applies value as minimum data delay, it refers to the longest path. The default value is max if the max is defined, otherwise it is set to 0. |
min | Applies value as minimum data delay, it refers to the longest path. The default value is max if the max is defined, otherwise it is set to 0. |
delay | Specifies the arrival time in nanoseconds or picoseconds that represents the amount of time for which the signal is available at the specified input after a clock edge. |
ports | Provides a list of input ports in the current design to which |
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Examples:
If cpt_in is a bus of 4 bits, the constraint should be written as below :
set_output_delay
Constrains output and in/out (bidirectional) ports, port busses, and pins (that are valid start points) within the design relative to a clock edge. If you omit both the -min and -max options, the delay is assumed to apply for both setup and hold analysis.
set_output_delay [-clock clock_name]
[-clock_fall ]
[-max float]
[-min float]
<delay>
<ports>
Arguments:
Name | Description |
|---|---|
clock | Specifies the clock reference to which the specified input delay is related. This is a mandatory argument. |
clock_fall | Specifies that input delay is relative to the falling edge of the clock. When it is not set, the delay is applied on the rising edge of the clock. |
max | Applies value as minimum data delay, it refers to the longest path. The default value is max if the max is defined, otherwise it is set to 0. |
min | Applies value as minimum data delay, it refers to the longest path. The default value is max if the max is defined, otherwise it is set to 0. |
delay | Specifies the arrival time in nanoseconds or picoseconds that represents the amount of time for which the signal is available at the specified input after a clock edge. |
ports | Provides a list of output ports in the current design to which |
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Examples:
If cpt_out is a bus of 4 bits, the constraint should be written as below :
set_min_delay
Specifies a minimum delay exception for a given path.
set_min_delay [-from string]
[-to string]
<delay>
Arguments:
Name | Description |
|---|---|
from | The argument which specifies how to get a timing path starting points. A valid timing starting point can be either an input port or a register. A valid argument can be: |
to | The argument which specifies how to get a timing path ending points. A valid timing ending point can be either an output port or a register. A valid argument can be: |
delay | The required minimum delay value in ns for specified paths. |
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Examples:
set_max_delay
Specifies a maximum delay exception for a given path.
set_max_delay [-from string]
[-to string]
<delay>
Arguments:
Name | Description |
|---|---|
from | The argument which specifies how to get a timing path starting points. A valid timing starting point can be either an input port or a register. A valid argument can be: |
to | The argument which specifies how to get a timing path ending points. A valid timing ending point can be either an output port or a register. A valid argument can be: |
delay | The required maximum delay value in ns for specified paths. |
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Examples:
set_multicycle_path
Specifies a multicycle exception for a given set of paths.
set_multicycle_path [-from string]
[-to string]
<delay>
Arguments:
Name | Description |
|---|---|
from | Specifies how to get a timing path starting points. A valid timing starting point is a register. A valid argument can be |
to | Specifies how to get a timing path ending points. A valid timing ending point is a register. A valid argument can be |
delay | The required maximum delay value in ns for specified paths. |
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Examples:
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