NX Design Constraint (NXDC)

Owned by Samah
Last updated: 19 Sept, 2022
17 min read

This document aims to list all the the nxpython methods available to apply timing constraints on a design.

createClock( )

/ ! \ DEPRECATED / ! \ Please use createClock(target = ‘target', name = ‘name’, period = ]0, ], rising = [0,period[, falling = ]rising, rising+period]) instead. This method is described immediately below.

This method is used to create a clock constraint at a timing point. This constraint is used by timing driven algorithms and static timing analysis. Depending on the unit defined in the project, timings are in ns or ps.

Signatures:

createClock(target, name, period)

createClock(target, name, period, rising)

createClock(target, name, period, rising, falling)

Arguments:

Name

Type

Description

target

string

Specifies how to get a clock related point. A valid argument can be: getPort(port_name), getRegisterClock(register_name) or getRegister(register_name), getClockNet(clock_net_name).

name

string

User clock name of the created clock.

period

float

The period value.

rising

float

Specifies the rising edge for clock waveform. Range [0, period[ (the default value is 0)

falling

float

Specifies the falling edge for clock waveform. Range ]rising, rising + period] (default value is period/2)

The name of the clock net is case sensitive

 

Examples:

In the example above, to define a 100MHz clock for net “Clk”, the following three commands are equivalent :

project = createProject() project.load('routed.nym') project.createClock('getRegisterClock(reg1)', 'clk', 10) or project.createClock('getPort(Clk)', 'clk', 10) or project.createClock('getClockNet(Clk)', 'clk', 10, 0, 5)

 

createClock( target = ‘target', name = ‘name’, period = ]0, ], rising = [0,period[, falling = ]rising, rising+period] )

This method is used to create a clock constraint at a timing point. This constraint is used by timing driven algorithms and static timing analysis. Depending on the unit defined in the project, timings are in ns or ps.

Arguments:

Name

Type

Description

target

string

Mandatory. The argument that specifies how to get a clock related point. A valid argument can be: getPort(port_name), getRegisterClock(register_name) or getRegister(register_name), getClockNet(clock_net_name).

name

string

Optional. User clock name of the created clock, default name is target_str

period

float

Mandatory. Period for the clock waveform. Must be positive, default value is period/2

rising

float

Mandatory if falling is defined. Otherwise, it is optional. Rising edge for the clock waveform. The range is defined as [0, period[ The default value is 0.

falling

float

Optional. Falling edge for the clock waveform. The range is defined as ]rising, rising + period]. The default value is period/2.

Examples:

 

In the example above, to define a 100MHz clock for net “Clk”, the following three commands are equivalent :

project = createProject() project.load('routed.nym') project.createClock(target = 'getRegisterClock(reg1)', name = 'Clk', period = 10) or project.createClock(target = 'getPort(Clk)', name = 'Clk', period = 10) or project.createClock(target = 'getClockNet(Clk)', name = 'Clk', period = 10, rising = 0, falling = 5)

 

createGeneratedClock(source, target, name, relationship)

/ ! \ DEPRECATED / ! \ Please use createGeneratedClock(source = ‘source', target = ‘target’, name = 'name', key = value) instead. This method is described immediately below.

This method is used to create an internal generated clock constraint at a timing point. This constraint is used by timing driven algorithms and static timing analysis.

Arguments:

Name

Type

Description

source

string

Specifies how to get a source clock related point. A valid argument can be: getClock(clock_name), getPort(port_name), getRegisterClock(register_name), getRegister(register_name), getClockNet(clock_net_name), getWFGOutput(wfg_name)

target

string

Specifies how to get a clock related point. A valid argument can be: getRegisterClock(register_name), getRegister(register_name), getClockNet(clock_net_name)

name

string

User clock name of the generated clock

relationship

dictionary

The relationship for computing clock wave of the generated clock from the master clock. A valid parameter can be:

MultiplyBy : unsigned

DivideBy : unsigned

DutyCycle : unsigned (1 to 99)

Phase : unsigned (0 to 359)

Offset : integer  (delay in ns)

Edges : list  [unsigned, unsigned, unsigned] (in non-decreasing order)

EdgeShift : list  [integer, integer, integer] (delay in ns)

Frequency-based and edge-based relationships are mutually exclusive.

Examples:

In the example above, the master clock "Clk" was created as 100MHz and the generated clock "clk1" is divided by 2 from the master clock. However note that the "clk_reg" is driven by the falling edge of master clock, the relation between the master clock and the generated clock is shown in the diagram below:

project = createProject() project.load('routed.nym') project.createClock(getPort('Clk'), 'Clk', 10) project.createGeneratedClock('getRegisterClock(clk_reg)', 'getRegisterClock(reg2)', 'clk1', {'DivideBy': 2}) or project.createGeneratedClock('getClock(Clk)', 'getRegisterClock(reg2)', 'clk1', {'Edges': [2, 4, 6]})

The following script is incorrect in this case:

########### INCORRECT SCRIPT ##########

project.createGeneratedClock(getClock('Clk'),getRegisterClock('reg2'), 'clk1', {'DivideBy': 2})

The diagram of the above command would be:

 

createGeneratedClock(source = ‘source', target = ‘target’, name = 'name', key = value)

This method is used to create an internal generated clock constraint at a timing point. This constraint is used by timing driven algorithms and static timing analysis.

Arguments:

Name

Type

Description

source

string

Mandatory. Specifies how to get source clock related point. A valid argument can be: getClock(clock_name), getPort(port_name), getRegisterClock(register_name), getRegister(register_name), getClockNet(clock_net_name), getWFGOutput(wfg_name)

target

string

Mandatory. Specifies how to get a clock related point. A valid argument can be: getRegisterClock(register_name), getRegister(register_name), getClockNet(clock_net_name)

name

string

User clock name of the generated clock

 

Parameters for computing clock wave of generated clock from master clock are described below:

Key

Type

Description and value

multiplyBy

int

Period multiplication factor. The value must be greater or equal to 1. Default value is 1

divideBy

int

Period division factor. The value must be greater or equal to 1. Default value is 1

dutyCycle

int

Duty cycle of clock period. The range must be from 1 to 99. Default value is 50.0

phase

unsigned

The range must be from 0 to 359

invert

boolean

Invert the clock signal (~ phase = 180)

offset

float

Offset for rising edge

edges

int list

Specifies the edges of the master clock to use in defining transitions on the generated clock. List in non-decreasing order. Mutually exclusive with 'multiplyBy' or 'divideBy'

edgeShift

float list

Shifts the edges of the generated clock by the specified values relative to the master clock. Mutually exclusive with 'multiplyBy' or 'divideBy'

 

Examples:

In the example above, the master clock "Clk" was created as 100MHz and the generated clock "clk1" is divided by 2 from the master clock. However note that the "clk_reg" is driven by the falling edge of master clock, the relation between the master clock and the generated clock is shown in the diagram below:

The diagram of the above command would be:

 

setClockGroup(group1_list, group2_list, option)

/ ! \ DEPRECATED / ! \ Please use setClockGroup(group1 = ‘group1’, group2 = ‘group2', option = 'option’) instead. This method is described immediately below.

This method is used to specify which clocks are not related. This constraint is used by timing driven algorithms and static timing analysis. 

Arguments:

Name

Type

Description

group1_list

string

Specifies how to get a group of clocks. A valid clock should be a clock created by command createClock. A valid argument can be: getClock(clock_name) and getClocks(name_expression).

group2_list

string

Same as the argument "group1_list"

option

string

A valid option can be 'asynchronous' or 'exclusive': Asynchronous clocks are those that are completely unrelated. Exclusive clocks are not actively used in the design at the same time.

Examples:

setClockGroup(group1 = ‘group1', group2= ‘group2’, option = 'option’)

This method is used to specify which clocks are not related. This constraint is used by timing driven algorithms and static timing analysis. 

Arguments:

Name

Type

Description

group1

string

Mandatory. Specifies how to get a group of clocks. A valid clock should be a clock created by command createClock. A valid argument can be: getClock(clock_name) and getClocks(name_expression).

group2

string

Mandatory. Same as the argument "group1"

option

string

Mandatory. A valid option can be 'asynchronous' or 'exclusive': Asynchronous clocks are those that are completely unrelated. Exclusive clocks are not actively used in the design at the same time

Examples:

 

addMaxDelayPath(from_list, to_list, delay)

/ ! \ DEPRECATED / ! \ Please use setMaxDelay instead, with the same key arguments. This method is described immediately below.

This method is used to specify the maximum delay path for the timing paths. It is used by timing driven algorithms and static timing analysis.

Arguments:

Name

Type

Description

from_list

string

Specifies how to get a timing path starting points. A valid timing starting point can be either an input port or a register. A valid argument can be: getPort(port_name), getPorts(name_expression), getRegister(register_name), getRegisters(name_expression), getRegistersByClock(clock_name)

to_list

string

Specifies how to get a timing path ending points. A valid timing ending point can be either an output port or a register. A valid argument can be: getPort(port_name), getPorts(name_expression), getRegister(register_name), getRegisters(name_expression), getRegistersByClock(clock_name)

delay

float

The required maximum delay value in ns for specified paths.

Examples:

 

setMaxDelay(source = ‘source', target = ‘target’, delay = 'delay’)

This method is used to specify the maximum delay path for the timing paths. It is used by timing driven algorithms and static timing analysis.

Arguments:

Name

Type

Description

source

string

Specifies how to get a timing path starting points. A valid timing starting point can be either an input port or a register. A valid argument can be: getPort(port_name), getPorts(name_expression), getRegister(register_name), getRegisters(name_expression), getRegistersByClock(clock_name)

target

string

Specifies how to get a timing path ending points. A valid timing ending point can be either an output port or a register. A valid argument can be: getPort(port_name), getPorts(name_expression), getRegister(register_name), getRegisters(name_expression), getRegistersByClock(clock_name)

delay

float

The required maximum delay value in ns for specified paths.

Examples:

 

addMinDelayPath(from_list, to_list, delay)

/ ! \ DEPRECATED / ! \ Please use setMinDelay instead, with the same key arguments. This method is described immediately below.

This method is used to specify the minimum delay path for the timing paths. It is used by timing driven algorithms and static timing analysis.

Arguments:

Name

Type

Description

from_list

string

Specifies how to get a timing path starting points. A valid timing starting point can be either an input port or a register. A valid argument can be: getPort(port_name), getPorts(name_expression), getRegister(register_name), getRegisters(name_expression), getRegistersByClock(clock_name)

to_list

string

Specifies how to get a timing path ending points. A valid timing ending point can be either an output port or a register. A valid argument can be: getPort(port_name), getPorts(name_expression), getRegister(register_name), getRegisters(name_expression), getRegistersByClock(clock_name)

delay

float

The required minimum delay value in ns for specified paths.

Examples:

 

setMinDelay(source = ‘source', target = ‘target’, delay = 'delay’)

This method is used to specify the minimum delay path for the timing paths. It is used by timing driven algorithms and static timing analysis.

Arguments:

Name

Type

Description

source

string

Specifies how to get a timing path starting points. A valid timing starting point can be either an input port or a register. A valid argument can be: getPort(port_name), getPorts(name_expression), getRegister(register_name), getRegisters(name_expression), getRegistersByClock(clock_name)

target

string

Specifies how to get a timing path ending points. A valid timing ending point can be either an output port or a register. A valid argument can be: getPort(port_name), getPorts(name_expression), getRegister(register_name), getRegisters(name_expression), getRegistersByClock(clock_name)

delay

float

The required minimum delay value in ns for specified paths.

Examples:

 

addMulticyclePath(from_list, to_list, cycle_count)

/ ! \ DEPRECATED / ! \ Please use setMulticyclePath instead, with the same key arguments. This method is described immediately below.

This method is used to specify the multicycle path for the timing paths. It is used by timing driven algorithms and static timing analysis.

Arguments:

Name

Type

Description

from_list

string

Specifies how to get a timing path starting points. A valid timing starting point is a register. A valid argument can be: getRegister(register_name), getRegisters(name_expression), getRegistersByClock(clock_name).

to_list

string

Specifies how to get a timing path ending points. A valid timing ending point is a register. A valid argument can be: getRegister(register_name), getRegisters(name_expression), getRegistersByClock(clock_name).

cycle_count

unsigned

An unsigned value that represents a number of cycles the data path must have for setup check.

Examples:

setMulticyclePath(source = 'source', target = 'target', pathMultiplier = 'pathMultiplier')

This method is used to specify the multicycle path for the timing paths. It is used by timing driven algorithms and static timing analysis.

Arguments:

Name

Type

Description

source

string

Mandatory. Specifies how to get a timing path starting points. A valid timing starting point is a register. A valid argument can be: getRegister(register_name), getRegisters(name_expression), getRegistersByClock(clock_name).

target

string

Mandatory. Specifies how to get a timing path ending points. A valid timing ending point is a register. A valid argument can be: getRegister(register_name), getRegisters(name_expression), getRegistersByClock(clock_name).

pathMultiplier

integer

Mandatory. A value that represents a number of cycles. Must be greater than 1.

Examples:

 

addFalsePath(from_list, to_list)

/ ! \ DEPRECATED / ! \ Please use setFalsePath instead, with the same key arguments. This method is described immediately below.

This method is used to specify the false path for the timing paths. This constraint is used by timing driven algorithms and static timing analysis.

Arguments:

Name

Type

Description

from_list

string

Specifies how to get a timing path starting points. A valid timing starting point is an input port or a register. A valid argument can be: getPort(port_name), getPorts(name_expression),  getRegister(register_name), getRegisters(name_expression),  getRegistersByClock(clock_name)

to_list

string

Specifies how to get a timing path ending points. A valid timing ending point is an output port or a register. A valid argument can be: getPort(port_name), getPorts(name_expression),  getRegister(register_name), getRegisters(name_expression),  getRegistersByClock(clock_name)

Examples:

setFalsePath(source = ‘source', target = 'target’)

This method is used to specify the false path for the timing paths. This constraint is used by timing driven algorithms and static timing analysis.

Name

Type

Description

source

string

Mandatory. Specifies how to get a timing path starting points. A valid timing starting point is an input port or a register. A valid argument can be: getPort(port_name), getPorts(name_expression),  getRegister(register_name), getRegisters(name_expression),  getRegistersByClock(clock_name)

target

string

Mandatory. Specifies how to get a timing path ending points. A valid timing ending point is an output port or a register. A valid argument can be: getPort(port_name), getPorts(name_expression),  getRegister(register_name), getRegisters(name_expression),  getRegistersByClock(clock_name)

Examples:

 

setInputDelay(clock, clock_mode, minimum_delay, maximum_delay, port_list)

/ ! \ DEPRECATED / ! \ Please use setInputDelay(clock = ‘clock', clockMode = ‘clockMode’, min = ‘min’, max = ‘max’, ports = 'ports’) instead. This method is described immediately below.

This method specifies the data arrival times at the specified input ports relative to the clock. The clock must refer to a clock name in the design. This constraint is used by timing driven algorithms and static timing analysis. Depending on the unit define in the project, timings are in ns or ps.

Arguments:

Name

Type

Description

clock

string

Specifies how to get a clock specified. A valid clock should be a clock created by command createClock. The valid argument is getClock(clock_name).

clock_mode

string

Specifies that input delay is relative to the falling or rising edge of the clock. It must be "rise"' or "fall".

minimum_delay

float

Applies value as minimum data arrival time.

maximum_delay

float

Applies value as maximum data arrival time.

port_list

string

Specifies how to get a list of input pads. A valid argument can be: getPort(port_name), getPorts(name_expression).

Examples:

 

setInputDelay(clock = ‘clock', clockMode = ‘clockMode’, min = ‘min’, max = ‘max’, ports = 'ports’)

This method specifies the data arrival times at the specified input ports relative to the clock. The clock must refer to a clock name in the design. This constraint is used by timing driven algorithms and static timing analysis. Depending on the unit define in the project, timings are in ns or ps.

Arguments:

Name

Type

Description

clock

string

Mandatory. Specifies how to get a clock specified. A valid clock should be a clock created by command createClock. The valid argument is getClock(clock_name).

clockMode

string

Optional. Specifies that input delay is relative to the falling or rising edge of the clock. It must be "rise"' or "fall". Default value is rise.

min

float

Optional. Applies value as minimum data delay, it refers to the longest path. The default value is max if the max is defined, otherwise it is set to 0.

max

float

Optional. Applies value as maximum data delay, it refers to the shortest path. The default value is min if the min is defined, otherwise it is set to 0.

ports

string

Mandatory. Specifies how to get a list of input pads. A valid argument can be: getPort(port_name), getPorts(name_expression).

Examples:

 

setOutputDelay(clock, clock_mode, minimum_delay, maximum_delay, port_list)

/ ! \ DEPRECATED / ! \ Please use setOutputDelay(clock = ‘clock', clockMode = ‘clockMode’, min = ‘min’, max = ‘max’, ports = 'ports’) instead. This method is described immediately below.

This method specifies the data arrival times at the specified output ports relative to the clock. The clock must refer to a clock name in the design. This constraint is used by timing driven algorithms and static timing analysis.

Arguments:

Name

Type

Description

clock

string

Specifies how to get a clock specified. A valid clock should be a clock created by command createClock. A valid argument can be: getClock(clock_name).

clock_mode

string

Specifies that output delay is relative to the falling or rising edge of the clock. It must be "rise"' or "fall".

minimum_delay

integer

Applies value as minimum data arrival time.

maximum_delay

integer

Applies value as maximum data arrival time.

port_list

string

Specifies how to get a list of output pads. A valid argument can be: getPort(port_name), getPorts(name_expression).

Examples:

 

setOutputDelay(clock = ‘clock', clockMode = ‘clockMode’, min = ‘min’, max = ‘max’, ports = 'ports’)

This command specifies the data required times at the specified output ports relative to the clock. The clock must refer to a clock defined in the design. This constraint is used by timing driven algorithms and static timing analysis. Depending on the unit defined in the project, timings could be in ns or ps.

Arguments:

Name

Type

Description

clock

string

Mandatory. Specifies how to get a clock specified. A valid clock should be a clock created by command createClock. A valid argument can be: getClock(clock_name).

clockMode

string

Optional. Specifies that output delay is relative to the falling or rising edge of the clock. It must be "rise"' or "fall". The default value is “rise”.

min

float

Optional. Applies value as minimum data delay, it refers to the longest path. The default value is max if the max is defined, otherwise it is set to 0.

max

float

Optional. Applies value as maximum data delay, it refers to the shortest path. The default value is min if the min is defined, otherwise it is set to 0.

ports

string

Mandatory. Specifies how to get a list of input pads. A valid argument can be:getPort(port_name), getPorts(name_expression).

Examples:

 

developCKGs()

This method automatically creates a generated clock constraint on each output of the PLLs and WFGs in current project. This constraint is used by timing driven algorithms and static timing analysis.

This method takes no argument.

 

Examples:

 

setAnalysisConditions(conditions)

/ ! \ DEPRECATED / ! \ Please use setAnalysisConditions(conditions = 'conditions') instead.

This method is used to specify the chip conditions for static timing analysis. This constraint is used by timing driven algorithms and static timing analysis.

Arguments:

Name

Type

Description

conditions

string

Specifies the conditions for static timing analysis.

Example:

 

setAnalysisConditions(conditions = 'conditions')

This method is used to specify the chip conditions for the static timing analysis. This constraint is used by timing driven algorithms and static timing analysis.

Arguments:

Name

Type

Description

conditions

string

Specifies the conditions for static timing analysis.

Example:

 

setCaseAnalysis(value, net_list)

/ ! \ DEPRECATED / ! \ Please use setCaseAnalysis(value = ‘value', netList = 'netList’) instead. This method is described immediately below.

This method is used to specify a constant logic value to the given tests. This constraint is used by timing driven algorithms and static timing analysis.

Arguments:

Name

Type

Description

value

unsigned

The valid constant. Values can be 0 or 1

net_list

string

Specifies how to get one or several nets. A valid argument can be getNet(net_name), getNets(net_name_expression), getPort(port_name), getPorts(port_name_expression)

Example:

In the example above, two clocks (clk[0] and clk[1]) are connected to the inputs of the multiplexer. However, only clk[1] is propagated through the output after setting the constant value on the selection signal (sel).

 

setCaseAnalysis(value = ‘value', netList = 'netList’)

This method is used to specify a constant logic value to the given tests. This constraint is used by timing driven algorithms and static timing analysis.

Arguments:

Name

Type

Description

Name

Type

Description

value

unsigned

The valid constant. Values can be 0 or 1

netList

string

Specifies how to get one or several nets. A valid argument can be: getNet(net_name), getNets(net_name_expression), getPort(port_name), getPorts(port_name_expression)

Example:

In the example above, two clocks (clk[0] and clk[1]) are connected to the inputs of the multiplexer, but only clk[1] is propagated through the output after setting the constant value on the selection signal (sel).

 

addReportTimingPath(source = ‘source_reg', target = 'target_reg’)

This method gives the shortest and the longest delays of a path. This constraint is used by timing driven algorithms and static timing analysis.

Timing log files will only contain paths found between sources and targets from these queries.

Arguments:

Name

Type

Description

Name

Type

Description

source_reg

string

Specifies the starting points of the timing paths to be analyzed. A valid argument can only be a register : getRegister(register_name), getRegisters(name_expression)

target_reg

string

Specifies the ending points or destination objects of timing paths to be analyzed. A valid argument can be: getRegister(register_name), getRegisters(name_expression)

Example:

This method should be launched after creating an Analyzer, as follow :

 

removeDesignConstraint(id= ‘id')

This method is used to remove a design constraint from the current project.
Remove constraint can be clocks, generated clocks, derived clocks of PLLs and WFGs, input delays, output delays, clock groups, analysis case, false paths, multicycle paths, min delay paths, and max delays paths.

Arguments:

Name

Type

Description

Name

Type

Description

id

unsigned

The id of the design constraint to remove

Example:

This method is used before launching a Static Timing Analysis or using TimingDriven:

 

resetTimingConstraints()

This method is used to reset all design constraints from the current project.
Reseted constraints can be clocks, generated clocks, derived clocks of PLLs and WFGs, input delays, output delays, clock groups, analysis case, false paths, multicycle paths, min delay paths, and max delays paths.

This method takes no argument.

Example:

This method is used before launching a Static Timing Analysis or using TimingDriven:

 

addReportPath(source = ‘source_reg', target = 'target_reg’)

This method gives the shortest and the longest delays of a path. This constraint is used by timing driven algorithms and static timing analysis.

Timing log files will still contain all paths. In addition, A file is create with shortest and longest paths found between sources and targets from each query.

Arguments:

Name

Type

Description

Name

Type

Description

source_reg

string

Specifies the starting points of the timing paths to be analyzed. A valid argument can only be a register : getRegister(register_name), getRegisters(name_expression)

target_reg

string

Specifies the ending points or destination objects of timing paths to be analyzed. A valid argument can be: getRegister(register_name), getRegisters(name_expression)

Example:

This method should be launched after creating an Analyzer, as follow :

 

 

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