Version Published Changed By Comment Actions
CURRENT (v. 15) 11 Oct, 2022 14:45  
v. 14 06 Sept, 2022 12:10 WFG : SYnchronization is made with the same source clock.
v. 13 05 Sept, 2022 15:09 Synchronized WFG must get the same pattern_end value
v. 12 11 Mar, 2022 09:54
v. 11 18 Feb, 2022 17:16 add REFO et change OSC frequency to 200MHz in NX_PLL_L diagram
v. 10 18 Feb, 2022 17:00 add cfg_use_pll generic to NX_PLL_L
v. 9 03 Jan, 2022 09:59 NX_IOB_x : termination is also affected by "locked" generic
v. 8 09 Dec, 2021 16:50 - Figures updated
- Layout updated
v. 7 17 Nov, 2021 14:41 change frequency range for NX_PLL_L
v. 6 17 Nov, 2021 14:20
v. 5 15 Nov, 2021 18:06 - Suppression numéros de figures
- Mise en page
v. 4 05 Nov, 2021 17:58 if a REF pin of a PLL is connected to a PAD => Turbo mode of the pad must be enabled
v. 3 04 Nov, 2021 09:54 Add a note about termination : min and max values depend on variant and bank voltage
v. 2 03 Nov, 2021 16:37 NX_RFB => Update architecture
=> Rename mem_context in mem_ctxt
NX_RAM => Rename mem_context in mem_ctxt
=> Fix examples of mem_ctxt values
NX_IOB(_I/_O) => InputDelayOn + OutputDelayOn description
NX_DSP(_L) => Rename A by Y and B by X in ALU operations
v. 1 18 Oct, 2021 16:35

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