Version Published Changed By Comment Actions
CURRENT (v. 13) 20 Jun, 2023 15:30  
v. 12 20 Jun, 2023 14:58
v. 11 16 Jun, 2023 16:30 add bank 13 for DDFR
v. 10 04 May, 2023 12:00 termination range depends on variant and bank voltage
v. 9 20 Apr, 2023 10:40 step of 100ps for delay lines
v. 8 03 Apr, 2023 22:41
v. 7 24 Mar, 2023 09:42 add information about network from I/O of NX_GCK_U
v. 6 21 Feb, 2023 09:53 Add NX_IDDFR + NX_ODDFR + NX_DFR
v. 5 07 Feb, 2023 15:49 Fix schematics and description of Write Enable and Reset pins for pipre registers DSP_U
v. 4 30 Jan, 2023 17:34 correct error :
MUX_Z
Selection for Z output
‘0’ : PR_Y
‘1’ : ALU
v. 3 30 Jan, 2023 17:15
v. 2 05 Jan, 2023 14:30 update PLL simplified block diagram
v. 1 04 Jan, 2023 17:54

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