Product features

The NG-MEDIUM device (NX1H35AS) is a Radiation Hardened By Design Sram-based FPGA manufactured on STM C65 Space process with following resources.

Resources

Device architecture

The NG-MEDIUM FPGA (NX1H35AS) is based on NanoXplore patented interconnect architecture offering the highest logic density as well as high efficiency mapping. Application mapping is supported by NanoXplore tools based on proprietary algorithms tailored to the interconnect topology.

The device is composed of a central fabric embedding the programmable logic, RAM and DSP blocks, and peripheral I/O buffers. The fabric is covered with a grid of high level functional blocks interleaved with interconnect structures providing routing resources to realize the connections within the fabric and to the peripheral I/O buffers. The programmable logic resources are arranged in a hierarchical structure called a TILE with a specific local interconnect network. The I/O buffers are arranged into multiple banks. Each bank has its own I/O buffer supply voltage.

NX1H35AS die features :

- 5 “Simple” I/O Banks B0, B1, B6, B7 and B8

- 8 “Complex” I/O Banks B2, B3, B4, B5, B9, B10, B11 and B12

- 1 “Service” configuration bank Prog

- 4 PLL clock generators CG0, CG1, CG2 and CG3

Packaging solutions

The NG-Medium NX1H35As is assembled in either Ceramic/Hermetic packages for Traditional Space projects as well as Organic package for New Space missions.

Hereafter packaging options vs Quality assurance:

(*) Prototypes are just electrically tested at ambient temperature (+25°C), are not guaranteed. They are not recommended for EM, EQM, nor FM parts of course.

(**) FM Class-2 and Class-1 part numbers will be replaced very soon by SMD number (5962F20217) as soon as this specification will be approved by DLA.

Hereafter a summary of NX Quality flows

Please contact NX Marketing for more details about Quality Assurance process flows.

Package Technologies

Ceramic Multilayer packages

The NG-Medium is offered in either

• Ceramic Quad Flat Package 352pins / CQFP-352 referenced CQ352

• Ceramic Land Grid Array 625pins / CLGA-625 referenced LG625

CQFP package technology

The NG-Medium Ceramic Quad Flat Package is hermetic multilayer package with square body frame. The package leads are brazed on each side of the package.

Courtesy of NTK

NG-Medium CQFP-352 body

• The body size of the CQFP-352 is 48 x 48mm.

• The CQ352 package as well as the tie-bar are in ceramic, type BA-914.

• The CQ352 is a 8-layers package.

• The CQ352 has 2 finger layers on top of the cavity, for wire connections.

NG-Medium CQFP-352 lid

• The NG-Medium CQFP-352 is sealed with a lid.

• Lid dimensions are 16,64 x 23,00 x 0,254mm.

• Lid material is Kovar.

• The lid is connected to Ground.

NG-Medium CQFP-352 wires:

• Wire diameter is 20µm

• Wire material is gold.

NG-Medium CQFP-352 leads

• CQFP lead form can be flat or J-leaded. The NG-Medium CQFP-352 has flat leads.

• Lead counts are 352-pins, all connected to a non-conductive ceramic tie-bar.

• It is the maximum lead count for that technology, otherwise the body would be larger and coplanarity would not be controlled properly.

• Flat leads are gold plated with a 27,25mm length.

• Leads will need to be cut and formed later on, by the PCB Assembly contractor, after or before degolding and tinning process (depends of PCB assembly vendor).

• Hereafter a standard specification for lead forming:

The CQFP-352 dimensions becomes:

NG-Medium CQFP-352 weight

The NG-Medium CQFP-352 mass is 28,6gr.

CLGA package technology

The NG-Medium Ceramic Land Grid Array package is hermetic multilayer package with square body frame.

This surface mount package is the same as the Ceramic Pin Grid Array, except that the pins are replaced by pads. This package consists of a co-fired ceramic base that has a matrix of pads on the bottom of the base.

This IC package technology allows application and design engineers to maximize the performance characteristics of semiconductors.

CLGAs are designed for low inductance, enhanced thermal operation and capability.

NG-Medium CLGA-625 body

• The body size of the CLGA-625 is 29 x 29 x 3,4mm.

• The CLGA-625 package is in ceramic, type BA-914.

• The CLGA-625 is a 16-layers package.

• The LG625 has 2 finger layers on top of the cavity, for wire connections.

NG-Medium CLGA-625 lid

• The NG-Medium CLGA-625 is sealed with a lid.

• Lid dimensions are 19,30 x 23,63 x 0,254mm.

• Lid material is Kovar.

• The lid is connected to Ground.

NG-Medium CLGA-625 wires:

• Wire diameter is 20µm

• Wire material is gold.

NG-Medium CLGA-625 pads

• CLGA pads are formed by a 25 x 25 matrix

• The pad pitch is 1,00mm.

NG-Medium CLGA-625 weight

The NG-Medium CLGA-625 mass is 11,0gr.

Ceramic Column Grid Array

The NG-Medium assembled in CLGA-625 cannot be soldered on PCB as is.

In order to be soldered on PCB, we need to add either solder balls or solder columns.

Solder balls available only for prototypes. The CLGA-625 will become a CBGA-625 referenced CB625.

Solder columns available for production parts, Engineering Model (EM) or Flight Model (FM) parts. CLGA-625 will become a CCGA-625 referenced either CG625 or CS625.

NanoXplore proposes 2 types of solder columns, based on 2 subcontractors:

MICROSS CLASP technology (CS625)

(extracted from Micross CGA Colum Attach flyer dated February 13, 2017, revision 1.2)

The Micross CGA process uses original IBM columns and original IBM assembly equipment. IBM have 20 years of development / production expertise and a huge installed base supporting their design. Based on IBM test data the 10/90 materials used for the column allow superior long term performance.

Courtesy of Micross UK

Micross solutions

• 10/90 SnPb columns

• Column Attach w/ Palladium paste

• Precision coplanarity & pitch

Micross Solder Columns

• 1,00mm column pitch

• 0,5mm diameter column

• 2,21mm high

• Coplanarity: 150µm max

HCM-Serma Reinforced Columns (CG625)

(extracted from HCM-Serma ‘Columns Manufacturing & Assembly on Ceramic – Technical Spacifications, dated 30/08/2019, rev1)

HCM-Serma has developed the European Column Attach process under ESA ECI contract n° 107948/13/NL/Cbi. HCM-Serma has obtained the Capability Approval from ESA (European Space Agency) by end-2015. The relevant process is described in Document ‘HCM PID 11 issue B’.

This certificate does not serve as formal qualification, however, it is expected that certification will be granted following the issue of a suitable ESCC requirement specification.

The HCM-Serma technology consists of Reinforced columns based on Copper Ribbon wrapping on High-Lead SnPb wire.

Columns raw material

• Core material: Cu & 15/85 SnPb

• Solder paste: 63/37 SnPb

• Column winding step 0,432mm, Column ribbon thickness 0,038mm, Column ribbon width 0,254mm

Courtesy of HCM-Systrel

Column specifications

• Column diameter: 0,38mm (+/-0,05mm). (Option 0,51mm).

• Column length: 2,21mm (+/- 0,20mm).

• CCGA-625 column pitch: 1,00mm

• Coplanarity: 150µm max.

Courtesy of HCM-Systrel

Rework

• Rework process just allowed for EM parts,

• For FM parts, no rework allowed unless customer authorization.
  

Plastic / Organic package

The NG-Medium is offered in

Plastic Ball Grid Array 625pins / PBGA-625 referenced FG625

The PBGA-625 is a overmolded BGA package 625pins.

The NG-Medium PBGA-625 will be ballprint and pinout compatible with equivalent CLGA/CCGA-625 components in order to allow the flexibility of the user at the design level since the user will select the package and quality level at a later stage, according the quality assurance of the requested mission.

Hereafter a short description of the PBGA-625:

Hereafter characteristics of the package:

• Substrate: 4 layers

• Assembly technique: Die-bond and wire-bond

• Wire: Gold type 20µm diameter

• Solder balls: SACN305 diameter 0,6mm.

• Ball pitch: 1mm

Package Outline Assembly

CQFP-352

CQFP-352 outline – 75 x 75 x 3,5mm with tie-bar

CQFP-352 package structure:

It is delivered as is, with the non-conductive tie-bar.

CQFP-352 package dimensions:

Notes

• The total profile height (Dim.A) TYP is measured with: A1 TYP + Lid height TYP without the preform. Same method for A MAX and A MIN.

• The CQFP-352 lid is connected to Ground.
  

CLGA-625 outline

CLGA-625 outline – 29 x 29 x 4,02 F25x25 1,0mm pitch

CLGA-625 Picture

CLGA-625 Dimensions

Notes

• The total profile height (Dim.A) TYP is measured with: A1 TYP + Lid height TYP without the preform. Same method for A MAX and A MIN.

• The CLGA-625 lid is connected to ground.
  

CCGA-625 package

CCGA-625 outline

CCGA-625 picture

Courtesy of HCM-Systrel (SERMA Group)

CCGA-625 Dimensions (Micross)

Notes

The total profile height (Dim.A) MAX= A1 MAX + A2 MAX + A3 MAX. Same for A MIN and A TYP.

PBGA-625 outline

PBGA-625 outline

PBGA-625 Package dimensions

Notes

PBGA stands for Plastic Ball Grid Array.

The total profile height (Dim A) is measured from the seating plane “C” to the top of the component.

The maximum total package height is calculated by the RSS method (Root Sum Square):

A Max = A1 Typ + A2 Typ + A4 Typ + √ (A1² + A2² + A4² tolerance values).

The typical ball diameter before mounting is 0.60mm.

The tolerance of position that controls the location of the pattern of balls with respect to datums A and B.

For each ball there is a cylindrical tolerance zone eee perpendicular to datum C and located on true position with respect to datums A and B as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone.

The tolerance of position that controls the location of the balls within the matrix with respect to each other.

For each ball there is a cylindrical tolerance zone fff perpendicular to datum C and located on true position as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone.

Each tolerance zone fff in the array is contained entirely in the respective zone eee above

The axis of each ball must lie simultaneously in both tolerance zones.

The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink or metallized markings, or other feature of package body or integral heat slug.

A distinguishing feature is allowable on the bottom surface of the package to identify the terminal A1 corner. Exact shape of each corner is optional.

Package Thermal performances

Introduction

Thermal characterization of packages is critical for the performance and reliability of IC applications, especially for Critical Spaborne applications.

This chapter will give you access to standard thermal package properties:

Thermal calculations and references for more information on thermal management are provided.

Thermal management of semiconductors involves thermal resistance, which is an important figure of merit describing the heat transfer properties of material. In calculations, thermal resistance is identified as "Theta," derived from the Greek word for heat, "thermos." It is thermal resistance that particularly interests us.

The thermal resistance of a FPGA device is the measure of the package's ability to transfer heat generated by the FPGA die to the circuit board or the ambient. Given the temperatures at two points, the amount of heat flow from one point to the other is completely determined by the thermal resistance.

By knowing the thermal resistance of a package, one can calculate the IC's junction temperature for a given power dissipation and its reference temperature.

Definitions:

• Θ_JA is the thermal resistance from junction to ambient, measured as °C/W. Ambient is regarded as thermal "ground." Θ_JA depends on the package, board, airflow, radiation, and system characteristics.

• Θ_JC is the thermal resistance from junction to case. Case is a specified point on the outside surface of the package. Θ_JC depends on the package materials (the lead frame, mold compound, die attach adhesive) and on the specific package design (die thickness, exposed pad, internal thermal vias, and thermal conductivity of the metals used).

• Θ_CA is thermal resistance from case to ambient. Θ_CA includes thermal resistances for all heat paths from outside the package to ambient.
  
  Given the above definitions, we see that:

• Θ_JA =Θ_JC+Θ_CA

• Θ_JB is thermal resistance from junction to board. Θ_JB quantifies the junction-to-board thermal path and is typically measured on the board adjacent to the package near pin 1 (< 1mm from the package edge). Θ_JB includes thermal resistance from two sources: from the IC's junction to a reference point on the package bottom, and through the board under the package.

Thermal calculations:

Junction temperature

T_J = T_A + (Θ_JA × P) where

TJ= Junction temperature

TA : Anbient temperature

P : Power dissipation (W)
T_J can also be calculated by using Ψ_JB or Ψ_JT values as.

T_J = T_B + (Ψ_JB × P) where
T_B = board temperature measured within 1mm of the package

T_J = T_T + (Ψ_JT × P) where
T_T = temperature measured at the center of the top of package.

Note: The maximum junction temperature of the NG-Medium is +125°C.

Maximum allowable Power Dissipation

P_max =(T_J-max -T_A)/Θ_JA
Maxim listings of maximum allowable power assume an ambient temperature of +70°C and a maximum allowable junction temperature of +125°C.

Thermal characterization and measurement conditions

The thermal performance of an IC package must be measured with JEDEC-standard methodologies and equipment. Characterizations run with application-specific boards can yield different results. It is also understood that the JEDEC-defined configurations do not represent typical real-world systems. Instead, the JEDEC configurations allow standardized thermal analysis and measurements for consistency; they are most useful for comparing the thermal figures of merit among package variations.

Reference document :

JESD51 : Methodology for the Thermal measurement of component packages.

CQFP-352 Thermal performances

This first analysis done by NX supply-chain (STMicroelectronics), based on the model hypothesis described below, give the JEDEC thermal resistances.

Please note that these resistance values are only valid with JEDEC conditions, and don’t predict the performance of a package in an application specific environment. To predict the real thermal performances, the simulation of the environment with the real boundary conditions is necessary.

CQFP-352 Package informations

• Lid is 16,64 x 23,00 x 0,254mm. Lid material is Kovar with 17W/mK conductivity,

• Substrate is 48,33 x 48,33 max. Substrate material is Ceramic with 25W/mK conductivity,

• Die attach thickness is 30µm with 1,6W/mK conductivity,

• Gold Wires are 20µm diameter with 318W/mK conductivity,

• The gap between the package and the PCB is ensured by a thermal interface material,

• 88 peripheral plates are made of copper with 385W/mK conductivity,

CQFP-352 Thermal hypothesis

• Uniform die’s power of 2W,

• Ambient temperature of 25°C.

CQFP-352 Thermal performances results

Temperature in a conductive, convective and radiation environment, with a test fixture:

Junction temperature

• Max: 45,9°C

• Mean: 45,4°C

  • Theta JA: 11°C/W

  • Psi JB: 2,7°C/W

  • Psi JC: 2,1°C/W

Board clamped in a double cold plate fixture (only conduction)

Theta JB: 3,2°C/W

Temperature in an only conductive environment, with a top cold plate (TCP):

Junction temperature

• Max: 30,46°C

• Mean: 29,18°C

• Case temp: 25°C

  • Theta JC: 2,8°C/W

CLGA-625 and CCGA-625 Thermal performances

This first analysis done by NX supply-chain (STMicroelectronics), based on the model hypothesis described below, give the JEDEC thermal resistances.

CLGA-625 Package informations

• Substrate is 3,4mm height,

• Lid is 19,30 x 23,62 x 0,254mm. Lid material is Kovar with 17W/mK conductivity,

• Lid attach is 50µm height with 1,6W/mK conductivity,

• Die attach thickness is 50µm with 1,6W/mK conductivity,

• Gold Wires are 20µm diameter with 318W/mK conductivity.

Analysis outputs

• Temperature mapping at die level,

• Junction to Bottom thermal resistance, Rth JB,

• Junction to Case thermal resistance, Rth JC

CLGA-625 Thermal conditions

• 20°C applied respectively at the bottom (for Rth JB calculation) and at the top (for Rth JC calculation) of the package.

• Uniform die’s power of 2W,

CLGA-625 Thermal performances results

Thermal resistance Rth JB (Junction-Board)

Junction temperature: TJ= 23,7°C

• With columns: Rth_c= (23,7-20,0)/2= 1,85°C/W

• Without columns

  • Based on max temp: Rth_nc= (23,7-22,8)/2= 0,45°C/W

  • Based on min temp: Rth_nc= (23,7-20,9)/2= 1,4°C/W

Thermal resistance Rth JC (Junction-Case)

Junction temperature: TJ= 25,1°C

Rth JC= (25,1-20)/2= 2,55°C/W

PBGA-625 Thermal performances

This first analysis done by NX supply-chain (STMicroelectronics), based on the model hypothesis described below, give the JEDEC thermal resistances.

PBGA-625 Package hypothesis

• Substrate 4 layers 27*27mm

  • Top solder mask : 40µm

  • M1 : 23µm, copper coverage 80%

  • P1 : 23µm, copper coverage 80%

  • Core : 250µm

  • P2 : 23µm, copper coverage 80%

  • M2 : 23µm, copper coverage 80%

  • Bottom Solder mask : 40µm

• Assembly

  • Die attach (25µm) : 0,6W/mK

  • Die size : 15,3 * 10,96 * 0,38mm

  • Uniform power disspipated : 2W

  • Moding condictivity : 0,99W/mK

• 25*25 Solder Balls

  • Ball pitch : 1,00mm

  • Metal pad diameter : 0,62mm

  • Height : 0,46mm

  • Material : Sn96,5/Ag3,5

PBGA-625 Simulation environments

Uniform power used : 2W

NB : We can include a power map if the chip’s power density is not homogenous. In this case, please provide the corresponding floorplan. If needed, we can send one powermap’s template.

Please note that the thermal resistances values can significantly change if the powermap is included in the simulation or not.

Ambient temperature : 20°C

• Junction to Ambient environment :

• Package mounting on a standard PCB 2s2p with a test fixture.

• Junction to Board environment

• Board clamped in a double cold plate fixture.

• Junction to Case environment

• Package mounting on a standard PCB 2s2p with a top cold above.

PBGA-625 Thermal performances results

• Theta JA = 16°C/W

• Theta JB = 6,2°C/W

• Theta JC = 2,8°C/W

Recommendation for PCB Design rules

Recommandation for CQFP package

Please find hereafter the EIA standard board layout of soldered pad for CQFP packages :

Note :

Md, Me, Zd and Ze dimensions are based on trim and form data from Fancort Industries Inc. If you are using trim and form from another vendor, these dimensions could be different. It is for PCB layout reference only.

Recommendation for PBGA and CLGA packages

Pad pitch

All NG-Medium devices assembled in either PBGA or CCGA packages have a 1mm ball or column pitch.

It concerns respectively :

X= Quality level.

The ball/Column matrix is 25 x 25= 625pins.

PBGA/CCGA landing pads

There are 2 types of landing pads :

• NSMD pad (Non Solder Mask Defined) Recommended solution

• SMD pad (Solder Mask defined).

Number of routing layers

The number of Routing Layer (RL) is function of the number of Balls or Columns and how they are distributed between active signals versus power and ground pins.

For the NG-Medium PBGA-625 and CCGA-625 distributed within a 25*25 pad matrix, we have

• 374 user I/Os,

• 251 dedicated power and ground signals.

Routing Channels (RC) are the number of available routing paths out of the BGA area :

the number of BGA pins on one side minus one, times four sides=

(25-1)*4= 96 Routing Channels.

The number of Routing Layers will follow that equation :

The number of ‘Routes per Channel (RpC) depends on whether one or two signal are routes between BGA pads. So, it must be 1 or 2 routes per channel.

Conclusion :

The number of layer in case all 251 user I/Os are used, is either

• In case of 1 Route per channel : 374 user I/Os / (96 RC * 1 RpC)= 4 Routing Layers,

• In case of 2 Routes per channel : 374 user I/Os / (96 RC * 2RpC)= 2 Routing Layers.

Layout Dimensions within PBGA/CCGA area

The amount of space available for routing under the NG-Medium FPGA device is dependent on

• the area between the balls in the CCGA area, for top and bottom layers

• the area between microvias for inner layers.

Typical dimensions are shown hereafter : (for Micross column type)

Same figure would apply for PBGA package, except the ball pad will be 0,60mm.

Trace(s) between Package Balls/Columns

The Ball/Column pitch and PBGA/CCGA pad/via diameters determine how much space is available to route between pads or microvias. Standard PCB processes allow for as low as 0,09mm trace widths 0.09mm spacing. Advanced processes can allow for as low as 0.05mm trace widths with 0.05mm spacing.

Trace routing between Balls/Columns :

Typical Solder reflow for PBGA/CCGA devices

Time and Temperature profiles

(Extracted from IPC-7095C – Design and Assembly process implementation for PBGA/CCGAs).

Profile comparison between SnPb and RoHS devices:

Example of peak reflow temperatures at various locations at or near PBGA/CCGA packages :

Solder Reflow profile for Leaded / SnPb FPGA device :

Notes :

1. Max temperature range= 220°C (body). Minimum temperature range before 205°C (leads/balls).

2. Preheat drying transition rate 2-4°C/seconds

3. Preheat dwell 95-180°C for 120-180 seconds

4. IR reflow shall be performed on dry packages

Case of CCGA packages :

• Use solder reflow profile recommended by the paste supplier

• Recommended vendor profile, either Micross for CS625 or HCM-Serma for CG625, must be achievable with the thermal mass of the package & board.

• Recommended peak temperature of +220°C (same as PBGA) to limit melting of lead from column into the eutectic solder.

• Maintain specified solder paste volume to maximize column length.

Solder reflow profile for Lead-free / RoHS FPGA device (SAC)