Table of figures

Hierarchy report providing user modules detection

Unused pattern reported due to incorrect addModule arguments

Output tables from reportInstances() method

Report region

Data and clock delay between a source and destination register

Examples of timing domains D1, D2, D3 in a simple design

Hold/Setup time relationship for active high launch and active high latch clocks

Hold/Setup time relationship for acitve high launch and active low latch clocks

Hold/Setup time relationship for active low launch and active high latch clocks

Hold/Setup time relationship for active low launch and active low latch clocks

Summary.timing example

Example 1 of critical paths table

Example 2 of critical paths table

Example of path detail table

Copyright

All the contents of this document are protected by the copyright law. They may not be disclosed to third parties or copied or duplicated in any form without the written consent of NanoXplore.

Introduction

This document is intended to guide users of NanoXplore Impulse software through all the steps involved in the design flow and the options available in NanoXplore design suite:

• impulse is a graphical interface that allows user to view and compile an existing project.

• nxpython is a wrapper around Python executable that allows user to control impulse software as a wrapper. It fully supports Python syntax, structures and external modules.

• The creation of a new project can be performed with both impulse and nxpython tools.

All commands described in this document for NXpython can be applied to the provided VHDL examples in example folder.

Package description

The provided impulse archive contains the following directories:

• bin       folder contains binary files for each supported Linux distribution

• doc      folder contains documentation files in pdf format

• example folder contains several examples of different projects with design sources in VHDL

• lib64 folder contains dynamic libraries and Python modules for each supported Linux distribution and associated Python version

• share folder contains additional files (vhdl libraries, simulation libraries, etc...)

Installation

To install impulse, the user needs to unpack nxdesignsuite-VERSION.tar.gz file into the installation directory (e.g. /opt/NanoXplore) using the following command:

$> tar xzf nxdesignsuite-VERSION.tar.gz -C /opt/NanoXplore

To set the license, it is required to export the following shell variable:

$> export LM_LICENSE_FILE=27000@servername

Where servername is the hostname of the server running the license daemon and 27000 is the port the daemon listens to.

Run nxpython

To run nxpython, use the following command:

$> /opt/NanoXplore/impulse/VERSION/bin/nxpython

To use the nanoxmap module in python, user must first call the following command in nxpython:

from nxpython import *

Nxpython specification

Command list and context

Heraafter a table of all available nxpython commands and the context they affect:

General commands

This chapter presents the general purpose commands. These commands do not need any object to be called as they are directly defined in the impulse module.

createProject([workingDirectory])

This method is used to create an empty project object. The project can then be loaded or built.

 Arguments:

When no argument is supplied, the working directory will be the one nxpython is launched from.

 Example:

project = createProject("/path/to/working/directory/")

getErrorCount()

This function returns the number of errors issued during Synthesize, Place and Route flow steps.

This function takes no argument.

Example:

print ('Errors: ', getErrorCount())

Output:

Errors: 0

getRemarkCount()

This function returns the number of remarks issued during Synthesize, Place and Route flow steps.

This function takes no argument.

Example:

print ('Remarks: ', getRemarkCount())

Output:

Remarks: 10

getWarningCount()

This function returns the number of warnings issued during Synthesize, Place and Route flow steps.

This function takes no argument.

Example:

print ('Warnings: ', getWarningCount())

Output:

Warnings: 0

listOptions()

This method lists all available options for current project.

 This method takes no argument.

Example:

listOptions()

Output:

| Available project options are:
|   +---------------------------------------------------------------------------+
| | Global                                                                                     |
| +-------------------------------+----------+------------------------------+
| |  Autosave                     |      Yes |                       No Yes |
| | +ClearStack                   |       No |                       No Yes |
| |  Dynamic                      |       No |                       No Yes |
| | +InternalReport               |       No |                       No Yes |
| |  MaxRegisterCount             |     2500 |    Value must be an unsigned |
| | +TimingDriven                 |       No |                       No Yes |
| +-------------------------------+----------+------------------------------+
|   +---------------------------------------------------------------------------+
| | Synthesis (step 1/2)                                                    |
| +-------------------------------+----------+------------------------------+
| |  DefaultFSMEncoding           | OneHot   | Binary OneHot OneHotSafe    
                                                            OneHotSafeExtra |
| |  DefaultRAMMapping            |     AUTO |          AUTO RF RAM RAM_ECC |
| |  DefaultROMMapping            |     AUTO |      AUTO LUT RF RAM RAM_ECC |
| |  DisableAssertionChecking     |       No |                       No Yes |
| |  DisableKeepPortOrdering      |       No |                       No Yes |
| |  DisableRAMAlternateForm      |       No |                       No Yes |
| |  DisableROMFullLutRecognition |       No |                       No Yes |
| |  IgnoreRAMFlashClear          |       No |                       No Yes |
| |  ManageUnconnectedOutputs     |    Error |           Error Power Ground |
| |  ManageUnconnectedSignals     |    Error |           Error Power Ground |
| +-------------------------------+----------+------------------------------+
|   +---------------------------------------------------------------------------+
| | Synthesis (step 2/2)                                                    |
| +-------------------------------+----------+------------------------------+
| |  DisableAdderBasicMerge       |       No |                       No Yes |
| |  DisableAdderTreeOptimization |       No |                       No Yes |
| |  DisableAdderTrivialRemoval   |       No |                       No Yes |
| |  DisableDSPAluOperator        |       No |                       No Yes |
| |  DisableDSPFullRecognition    |       No |                       No Yes |
| |  DisableDSPPreOperator        |       No |                       No Yes |
| |  DisableDSPRegisters          |       No |                       No Yes |
| |  DisableLoadAndResetBypass    |       No |                       No Yes |
| |  DisableRAMRegisters          |       No |                       No Yes |
| |  ManageAsynchronousReadPort   |       No |                       No Yes |
| |  ManageUninitializedLoops     |       No |              No Power Ground |
| |  MappingEffort                |     High |              Low Medium High |
| |  OptimizedMux                 |      Yes |                       No Yes |
| | -SynthesizingEffort           |   Medium |              Low Medium High |
| | -UseSynthesisRetiming         |       No |                       No Yes |
| |  VariantAwareSynthesis        |      Yes |                       No Yes |
| +-------------------------------+----------+------------------------------+
|   +---------------------------------------------------------------------------+
| | Place (step 1/5)                                                        |
| +-------------------------------+----------+------------------------------+
| |  BypassingEffort              |   Medium |              Low Medium High |
| +-------------------------------+----------+------------------------------+
|   +---------------------------------------------------------------------------+
| | Place (step 2/5)                                                        |
| +-------------------------------+----------+------------------------------+
| | -SharingEffort                |   Medium |              Low Medium High |
| | -SharingFanout                |      100 |                          100 |
| +-------------------------------+----------+------------------------------+
|   +---------------------------------------------------------------------------+
| | Place (step 3/5)                                                        |
| +-------------------------------+----------+------------------------------+
| |  CongestionEffort             |     High |              Low Medium High |
| |  DensityEffort                |      Low |              Low Medium High |
| | -PartitioningEffort           |   Medium |              Low Medium High |
| |  RoutingEffort                |   Medium |              Low Medium High |
| | -UnificationEffort            |      Low |              Low Medium High |
| +-------------------------------+----------+------------------------------+
|   +---------------------------------------------------------------------------+
| | Place (step 4/5)                                                        |
| +-------------------------------+----------+------------------------------+
| |  PolishingEffort              |     High |              Low Medium High |
| +-------------------------------+----------+------------------------------+
|   +---------------------------------------------------------------------------+
| | Place (step 5/5)                                                        |
| +-------------------------------+----------+------------------------------+
| | -DoubleAccess                 |      Yes |                       No Yes |
| | -Permissive                   |      Yes |                       No Yes |
| +-------------------------------+----------+------------------------------+
|   +---------------------------------------------------------------------------+
| | Route (step 1/3)                                                        |
|   +---------------------------------------------------------------------------+
|   +---------------------------------------------------------------------------+
| | Route (step 2/3)                                                        |
|   +---------------------------------------------------------------------------+
|   +---------------------------------------------------------------------------+
| | Route (step 3/3)                                                        |
|   +---------------------------------------------------------------------------+
|   +---------------------------------------------------------------------------+
| | Bitstream                                                               |
| +-------------------------------+----------+------------------------------+
| |  ExhaustiveBitstream          |       No |  No Config Context 
                                                              ConfigContext |
| |  GenerateBitstreamCMIC        |       No |                       No Yes |
| | -MultiBlock                   |       No |                       No Yes |
| |  UnusedPads                   | Floating | Floating WeakPullUp 
                                                               WeakPullDown |
| | -noCfgCtx                     |       No |                       No Yes |
| | -noHeader                     |       No |                       No Yes |
| | -noRun                        |       No |                       No Yes |
| | -noThermalSensor              |       No |                       No Yes |
| | -noWorkaround                 |       No |                       No Yes |
| | -simpleFrames                 |       No |                       No Yes |
| +-------------------------------+----------+------------------------------+

printError(message)

This function is used to print an error message in the impulse output. This includes terminal output and log file if set. An error message is prefixed by ERROR string so it can be easily found.

When using this method, the global number of errors is incremented by 1.

Arguments:

Example:

printError("It's a trap!")

Output:

ERROR	|  It's a trap!

printRemark(message)

This function is used to print a remark message in the impulse output. This includes terminal output and log file if set. An error message is prefixed by REMARK string so it can be easily found.

When using this method, the global number of remarks is incremented by 1.

Arguments:

Example:

printRemark("This is a remark")

Output:

REMARK	|  This is a remark

printText([message])

This function is used to print a message in the impulse output. This includes terminal output and log file if set. When no message is given, method prints a new line in the impulse output.

Arguments:

Example:

printText('There is no spoon.')

Output:

| There is no spoon.

printWarning(message)

This function is used to print a warning message in the impulse output. This includes terminal output and log file if set. A warning message is prefixed by WARNING string so it can be easily found.

When using this method, the global number of warnings is incremented by 1.

Arguments:

Example:

printWarning('The cake is a lie.')

Output:

WARNING | The cake is a lie.

setCoreCount(core_count)

This function sets the number of core to use in multi-thread algorithm.

Minimum value is 1. The tool uses the number of logic cores of the computer as a maximum.

Arguments:

Example:

setCoreCount(2)

Output:

| Setting core count to 2

setDirAutoChange(change_project_dir)

This function allows to create a user-defined directory to stock the reports created during the execution of the flow.

Arguments:

Example:

p = createProject()
setDirAutoChange(False)
p.load('my_path/routed-auto.nym')

setLogDirectory(log_directory)

This function allows to create a user-defined directory to stock the reports created during the execution of the flow.

Arguments:

Example:

setLogDirectory(‘TestLogDirectory’)

Output:

| Setting log directory to TestLogDirectory

usage()

This method displays application usage.

This method takes no argument.

Example:

usage()

Output:

| Usage:
 |   $> nxpython3
 |     will run nxpython3 in interactive mode
 |     
 |   $> nxpython3 file.py
 |     will run the given python file in nxpython3 in batch mode
 |     
 |   options
 |     several options can be used when running nxpython3.
 |     Options must be placed before the file.py argument.
 |     Any option placed after will be passed to the file.py.
 |       -g or -gui        execute nxpython3 with graphical support
 |       -c or -core CORE  execute nxpython3 with maximum core number
 |       -v or -version    display nxpython3 version
 |       -h or -help       display this help

version()

This method displays application version.

This method takes no argument.

Example:

version()

Output:

| Copyright (C) 2010-2020, NanoXplore, All rights reserved

Expected expressions for NXpython methods

NxPython methods get a standardized format for arguments expecting a path.

This section describes the expression format specific to NX.

Impacted methods:

The following methods allow regular expressions / wildcard formats in order to match with multiple instances:

·       addModule

·       constrainPath

·       getInstances

·       getModels

·       getRegisters

·       setSite

·       …

Maintainability:

It is no longer necessary to escape (with the ‘\’ character) special characters for these methods.

Affected special characters are:

·       ‘[‘

·       ‘]’

·       ‘(‘

·       ‘)’

·       ‘|’

For instance, the constraint:

addModule('timing_pipe\(X2A98C8C6\)', 'GEN_HIER0.GEN_COL[0].COL_PIPE', 'GEN_HIER0_COL-%')

can be replaced by:

addModule('timing_pipe(X2A98C8C6)', 'GEN_HIER0.GEN_COL[0].COL_PIPE', 'GEN_HIER0_COL-%')

However, the old format is still compliant and still operates.

User use:

In a usual way, a copy/paste of a path from a log file works for the constraint.

In addition, it is comfortable to use ‘*’ and ‘+’ characters to match several paths.

‘*’ matches with any character: can be very useful to match with all paths beginning with a specified path.

‘+’ matches with any character but ‘|’: can be very useful to match with all paths beginning with a specified path without matching with lower hierarchy levels.

Hereafter an example with existing paths and constraints:

Note:

If the user needs to use regular expressions ignoring auto-escaping of special characters, it is possible to set the constraint using back quotes as follow:

addMappingDirective(getModels(“add_`[1-2][0-9]`u_*”), …)

Project related methods

This section presents the methods related to the project object.

addBank(name, dict)

The method addBank allows user to configure a specific bank of the FPGA. The pads inside the defined bank will be used first to configure inputs/outputs of the HDL module. For the given bank, the configuration has two basic arguments name and dict.

Arguments:

dict is a dictionary which can take the following keys:

The voltage must be one of the following values:

• 1.5

• 1.8

• 2.5

• 3.3

Example:

project.addBank('IOB0', {'voltage': '2.5'})

addBanks(dict)

The method addBanks allows user to configure several banks of the FPGA to be used for configuration of inputs/outputs of the HDL module. addBanks use a dictionary as an argument.

Arguments:

Example:

ioBanks = { 'IOB0'  : {'voltage': '2.5'}
                  , 'IOB1'  : {'voltage': '2.5'}
                  , 'IOB2'  : {'voltage': '2.5'}
                  , 'IOB3'  : {'voltage': '2.5'}
                  , 'IOB4'  : {'voltage': '2.5'}
                  , 'IOB5'  : {'voltage': '2.5'}
                  , 'IOB6'  : {'voltage': '2.5'}
                  , 'IOB7'  : {'voltage': '2.5'}
                  , 'IOB8'  : {'voltage': '2.5'}
                  , 'IOB9'  : {'voltage': '2.5'}
                  , 'IOB10' : {'voltage': '2.5'}
                  , 'IOB11' : {'voltage': '2.5'}
                  , 'IOB12' : {'voltage': '2.5'}
          }
project.addBanks(ioBanks)

addBlackBox(name, type, mapping, interface)

The method addBlackBox allows users to define customized mapping of certain HDL modules on the specific FPGA blocks and to dispose the interface of the blocks.

Arguments:

The type argument can only be overridden for specific object types. The available types are:

For each type, there are some specific instances in the FPGA onto which it can be mapped. This can be specified using mapping argument. The following table presents all the available mapping targets for each type:

The argument interface argument specifies the interface mapping between the HDL module and nxpython.

When setting ROM value for type argument, the nxpython interface is:

When setting RAM value for type argument, the nxpython interface depends on the mode RAM is being used in:

• RAM mode: Simple port

• RAM mode: Split read/write port (1 port for read and 1 port for write)

• RAM mode: True dual port (2 ports for read/write)

First port:

Second port:

Example:

If the HDL design contains a micro code ROM define in VHDL as:

component myMicroCode
port (
  addr	  : in std_logic_vector(5 downto 0);
  clk	  : in std_logic;
  micro : out std_logic_vector(5 downto 0)
);
end component;

User can add a black box to force nxpython to recognize this module as a ROM.

project.addBlackBox('myMicroCode', 'ROM', 'RF', 'AD(addr),DO(micro),CK(clk)')

addBlackBox() : for Preplaced IP

The idea is to offer the possibility to the user to reuse the result of an impulse flow as an IP in a top design.

For instance, the user will work on a design named IP with the desired performance.

The user can then reuse the result of this first flow in another design. named top, which instanciates the IP entity several times.

Impulse will use the result of synthesis and place from the first flow and replicate then in the top flow

To specify that an entity of the design top must be taken into account as a preplaced IP, the user has to add the following constraint before the synthesis

project.addBlackBox('m4000', 'IP', 'm4000_preplaced.nym', 'M1:1x2;M2:6x2')

• The first argument is the name of the VHDL entity

• The second argument must be ‘IP’

• The third argument is the .nym Preplace results of the IP

• The fourth argument is a string character which lists for each instanciation of the entity, the name of the instance followed by : and the region of the IP in fortmat (col x row). Instanciations are separated by the character ;

Limitations :

This functionality has some important limitations :

Variant

The variant on which the IP design is prepared must be strictly identical to the variant used for the design. For example, NG-MEDIUM in both cases.

Aperture

It is necessary that the IP design is placed/routed using minimal aperture.

addBlackBox

The method addBlackBox should be called only once by an entity in the top design.
For instance, it is not allowed to use the following lines :

project.addBlackBox('m4000', 'IP', 'm4000_preplaced1.nym', 'M1:1x2')
project.addBlackBox('m4000', 'IP', 'm4000_preplaced2.nym', 'M2:6x2')

Fabric instances

Among the instances of the ring, some are not supported yet :
CDC, CKS, FIFO, XFIFO

Ring instances

Among the instances of the ring, some are not supported yet :
PLL, WFG, CR5, SOC_IF, HSSL

addFalsePath(from_list, to_list)

This method is used to specify the false path for the timing paths. This constraint is used by timing driver algorithms and static timing analysis.

Arguments:

Example:

project = createProject()
project.load('routed.nym')
project.addFalsePath(getRegister('UUT1|Gen_seq[3].seq_i|temp_reg[1]'),getRegister('UUT2|dout_reg[61]'))

addFile([library], file)

This method is used to add a HDL source file to the project. The file can be added to a specific library by passing its name as the first optional library argument. The default library is work.

Arguments:

Example:

project.addFile('src/simple.vhd')
project.addFile('src/complex.vhd:VHDL_93')
project.addFile('src/simple_verilog.v:VERILOG_95')
or
project.addFile('myLib', 'src/simple.vhd')

addFiles([library], fileList)

This method is used to add several HDL source files to the project. The files can be added to a specific library by passing its name as the first optional library argument. The default library is work.

Arguments:

Example:

project.addFiles(['src/simple.vhd', 'src/test.vhd'])
or
project.addFiles('myLib', ['src/simple.vhd', 'src/test.vhd'])

addHSSLLocation(pattern,location)

This method is used to set the spot in which a HSSL should be set.

Placement of HSSL elements can also be done during instantiation (with location generic in source code).add

Arguments:

Example:

project.addHSSLLocation('i_hssl_esistream|i_HSSL_ONLY|i_NX_HSSL_FULL|ctrl', 'HSSL2')

addMappingDirective(name, type, mapping)

This method is used to add a mapping directive for Synthesis flow step which overrides the default nxpython mapping behavior for a specific HDL module or instance.

Arguments:

The name argument can be a regular expression matching a HDL module or instance name. In order to specify whether to search for module or instance, the user has to use the getModels(...) or getInstances(...) keyword.

The type argument can only be overridden for specific object types. For each type, there are some specific instances in the FPGA onto which it can be mapped. This can be specified using mapping argument. The following table presents all the available mapping targets for each type:

Example:

If the HDL design named myTest contains a small 3 write ports and 3 read ports FIFO named myFifo, nxpython cannot automatically map it into RF or RAM, but user can add a mapping directive to map it into DFF:

project.addMappingDirective(getModels('myTest_myFifo'), 'RAM', 'DFF')

addMaxDelayPath(from_list, to_list, delay)

This method is used to specify the maximum delay path for the timing paths. It is used by timing driver algorithms and static timing analysis.

Arguments:

Example:

project = createProject()
project.load('routed.nym')
project.addMaxDelayPath(getRegister('UUT1|Gen_seq[3].seq_i|temp_reg[1]'),
                        getRegister('UUT2|dout_reg[61]'), 3900)

addMemoryInitialization(name, type, file)

This method is used to specify a file that will be used to initialize a specific memory instance.
Arguments:

The name argument can be a regular expression matching a HDL module or instance name. In order to specify whether to search for module or instance, the user has to use the getModels(...) or getInstances(...) keyword.

The available file formats are:

The NX File format is a simple format in which initialization bits are written in ASCII. Each line of the file represents one vector in the memory. NULL MSBs and empty (only 0's) lines at the end of the file are NOT mandatory.

Example:

To initialize a memory called IMG_1' in a design called 'test_init' using data from a file called "initdata.nx", call:

Project.addMemoryInitialization('getModels(test_init_IMG_1)', 'NX', 'initdata.nx')

If you declare a memory array 'array(0 to 5) of std_logic_vector(0 to 3)' and want to load an identity matrix, the file should contain:

0000
1000
0100
0010
0001
0000

Since it is not mandatory to initialize:

• the end of the array if it contains only zeros

MSBs if they are null

The previous example can be written this way:

0000
1000
100
10
1

addMinDelayPath(from_list, to_list, delay)

This method is used to specify the minimum delay path for the timing paths. It is used by timing driver algorithms and static timing analysis.

Arguments:

Example:

project = createProject()
project.load('routed.nym')
project.addMinDelayPath(getRegister('UUT1|Gen_seq[3].seq_i|temp_reg[23]'),
                                     getRegister('UUT1|Gen_seq[3].seq_i|temp_reg[22]'), 1200)

addModule(model, instance, format)

This method is used to add a HDL module definition to the current project that contains all HDL logic elements including within the model given in argument.

Arguments:

Example:

project = createProject()
project.addModule('mCntrl',      'cntrl',    'cntrl-%')

nxpython reports user modules detection in the hierarchy.rpt (previous figure) file with detailed information including resources used for each module and detailed hierarchy of all modules defined in the current project.

hierarchy.rpt also allows to check if pattern expression provided for model and instance arguments have been fully accepted by nxpython tool. User can use the wildcard operator '*'. See full details with an example.

Example:

project = createProject()
project.addModule('mAlu*',         'alu',        'alu-%')
project.addModule('mCntrl',        'cntrl',      'cntrl-%')
project.addModule('mRegister*', 'register', 'cntrl-%')

addMulticyclePath(from_list, to_list, cycle_count)

This method is used to specify the multicycle path for the timing paths. It is used by timing driver algorithms and static timing analysis.

Arguments:

Example:

project = createProject()
project.load('routed.nym')
project.addMulticyclePath(getRegister('UUT1|Gen_seq[3].seq_i|temp_reg[1]'),
                          getRegister('UUT2|dout_reg[61]'), 2)

addPad(name, parameters)

This method allows user to configure an input/output of the HDL module into specific pad of the FPGA. For the given pad, the configuration has two basic argument (name and parameters).

Arguments:

The parameters argument is a dictionary which can take the following keys:

The standard key must respect the following values:

• LVCMOS (Default)

• LVDS

• LVDS_STR

• SSTL

• HSTL

LVDS is the nominal LVDS standard. LVDS_STR is a strong LVDS with higher voltage (ex : 550mVpp LVDS vs 900mVpp LVDS_STR for NG-LARGE variant).

The I/O differential (Default False) activation is conditioned depending on standard:

In case of differential mode, the user must only declare the “_P” pad. The associated differential “_N” pad will be automatically set by the software with the same parameters.

The drive key must respect the following values:

• 2mA (only allowed for LVCMOS standard - Default for LVCMOS standard)

• 4mA (only allowed for LVCMOS standard)

• 8mA (only allowed for LVCMOS standard)

• 12mA (only allowed for LVCMOS standard)

• 16mA (only allowed for LVCMOS standard)

• I (only allowed for SSTL and HSTL standard - Default for SSTL and HSTL standard)

• II (only allowed for SSTL and HSTL standard)

• Undefined (only allowed for LVDS standard - Default for LVDS standard)

As an example for NG-Large variant, the following array gives a trade-off between the maximum frequency reachable and noise limitation plus power consumption:

The weakTermination key must respect the following values:

• None

• PullDown

• PullUp (Default)

• Keeper

The slewRate key must respect the following values:

• Slow

• Medium (Default)

• Fast

The termination key specifies the output impedance of the pad in Ohms. In differential mode, the impedance is two times the value. It’s specified in Ohms, (Default is set to minimum value).

Min and max values depend on the variant and the bank voltage.

The inputDelayLine and outputDelayLine keys should be between 0 (Default) and 63. This number correspond to a number of step. Values are applied only if inputDelayOn and outputDelayOn are set to True.

The terminationReference key is used only if termination is set (Default '-'). It must respect the following criteria to be set to ‘Floating’ value otherwise it should always be defined as ‘VT’.

Unit of inputSignalSlope key is V/ns in the range [0.5;20] (Default 0).

Unit of ouputCapacity key is pF in the range [0;40] (Default 0).

When set to ‘True”, the turbo key (Default False) specifies that the input buffer of the pad is in turbo mode. As an example for NG-Large variant, the following array gives a trade-off between the maximum frequency reachable and power consumption:

The registered key (Default '') allows user to merge registers into Input/Output pads. This key can take the following values:

When a key is not in the dictionary, its value is set to default, i.e. 0 for inputDelayLine/outputDelayLine/signalSlope/outputCapacity and False for all the boolean arguments.

Example:

#LVCMOS implementation
project.addPad( 'clk', {'location': 'IO_B1D02P', 'standard': 'LVCMOS', 'drive' :'2mA'})
project.addPad(  'in_row', {'location': 'IO_B1D04P', 'standard': 'LVCMOS', 'drive' :'2mA',   
                 'weakTermination':  'PullUp', 'slewRate': 'Slow', 'termination': '50', 'inputDelayLine': 1, 
                 'outputDelayLine': 2, 'differential': False, 'turbo': True})

Example:

#LVDS implementation
project.addPad( 'spw_rxd[0]' : {'location': 'IOB19_D16P', standard: LVDS, 'differential': True, 'termination': '50','terminationReference':'VT', 'turbo': True, 'drive': 'undefined'})
project.addPad( 'spw_rxs[0]' : {'location': 'IOB19_D17P', standard: LVDS, 'differential': True, 'termination': '50','terminationReference':'VT','turbo': True, 'drive': 'undefined'})
project.addPad( 'spw_txd[0]' : {'location': 'IOB19_D14P', standard: LVDS,  'differential': True, 'slewRate': 'Fast', 'drive': 'undefined'})
project.addPad( 'spw_txs[0]' : {'location': 'IOB19_D15P', standard: LVDS,  'differential': True, 'slewRate': 'Fast', 'drive': 'undefined'})

addPads(pads)

This method is used to configure inputs/outputs of the HDL module into specific pads of the FPGA. The argument is a dictionary that associates the HDL input/output name to a dictionary, which can contain some keys (location, type, weakTermination, slewRate, termination, inputDelayLine, outputDelayLine, differential, terminationReference, turbo) as defined in addPad(name, parameters).

Arguments:

Example:

#LVCMOS implementation
pads = {'clk', {'location': 'IO_B1D02P', 'standard': 'LVCMOS', 'drive' :'2mA'},
	  'in_row', {'location': 'IO_B1D04P', 'standard': 'LVCMOS', 'drive' :'2mA', 'weakTermination':
            'PullUp', 'slewRate': 'Slow', 'termination': '50', 'inputDelayLine': 1, 'outputDelayLine': 2, 
           'differential': False, 'turbo': True}
          }
project.addPads(pads)

Example:

#LVDS implementation
pads = {'spw_rxd[0]'  : {'location': 'IOB19_D16P', standard: LVDS, 'differential': 
                                   True, 'termination': '50','terminationReference':'Floating', 'turbo': True, 'drive': 'Undefined'},
             'spw_rxs[0]'  : {'location': 'IOB19_D17P', standard: LVDS, 'differential': 
                                   True, 'termination': '50','terminationReference':'Floating','turbo': True, 'drive': 'Undefined'},
             'spw_txd[0]'  : {'location': 'IOB19_D14P', standard: LVDS,  'differential': 
                                   True, 'slewRate': 'Fast', 'drive': 'Undefined'},
             'spw_txs[0]'   : {'location': 'IOB19_D15P', standard: LVDS,  
                                   'differential': True, 'slewRate': 'Fast', 'drive': 'Undefined'}
}
project.addPads(pads)

addPin(name, location)

This method allow user to configure an input/output of the HDL module into specific pin of the embedded FPGA. This method is reserved to embedded variants of FPGA.

Arguments

Example:

project.addPin('A', 'TUI200')

addPins(pins)

This method allow user to configure inputs/outputs of the HDL module into specific pins of the embedded FPGA. This method is reserved to embedded variants of FPGA.

Arguments:

Example:

pins = {
	  'A': 'TUI200',
	 'B': 'TUI201'
          }
project.addPins(pins)

addParameter(name, value)

This method allows user to specify the value of the top design generic parameters.

Arguments:

Example:

project.addParameter('BusWidth', '16')
project.addParameter('Key_size', '2')
NB_PIPE_ROW_WG1 = 5 
NB_PIPE_ROW_WG2 = 7 
NB_PIPE_ROW_WG3 = 3 
#parameter list for VHDL design
project.addParameter('NB_PIPE_ROW_WG1', str(NB_PIPE_ROW_WG1))
project.addParameter('NB_PIPE_ROW_WG2', str(NB_PIPE_ROW_WG2))
project.addParameter('NB_PIPE_ROW_WG3', str(NB_PIPE_ROW_WG3))

addParameters(parameters)

In case of a large number of parameters, a parameter dictionary can be created consisting of the name of the parameter as a key and its respective value. Both name and value must be string.

Arguments:

Example:

parameters = {'BusWidth': '16', 'Key_size': '2', ...}
project.addParameters(parameters)

addPLLLocation(pattern, location)

This method is used to set the spot in which a PLL should be set.

Placement of PLL elements can also be done during instantiation (with location generic in source code).

Arguments:

Example:

#placing pll0, pll1, pll2, pll3 in different CKGs
project.addPLLLocation('pll0', 'CKG1.PLL1')
project.addPLLLocation('pll1', 'CKG2.PLL1')
project.addPLLLocation('pll2', 'CKG3.PLL1')
project.addPLLLocation('pll3', 'CKG4.PLL1')
#placing a PLL located in a sub-hierarchy of the design
project.addPLLLocation('FIR_MF|CLKG|PLL_20_160', 'CKG4.PLL1')

addRingLocation(name, location)

This method is used to place an instance in the I/O ring of the FPGA. addRingLocation can be used instead of addPLLLocation, addWFGLocation or addPin.

Example:

Example:

project.addRingLocation('PLL0','CKG1.PLL1')
project.addRingLocation('WFG_3','CKG4.WFG_C1')

addRingLocations(dictionary)

In case of a large number of instances to be placed in the I/O Ring, a dictionary can be created consisting in the name of the instance as a key and its association location. Both name and location must be string.

Arguments:

Example:

rings = { 'PLL0' : 'CKG1.PLL1', 
               'PLL1' : 'CKG2.PLL1',
               'WFG_0' : 'CKG1.WFG_C1',
               'WFG_1' : 'CKG2.WFG_C1' }
project.addRingLocations(rings)

addVerilogIncludeDirectory(directory)

This method is used to add an extra directory containing Verilog files to the project. This is used when the included files are external to the working directory.

Arguments:

Example:

project.addVerilogIncludeDirectory('include’)
or
project.addVerilogIncludeDirectory('../lib’)

addVerilogIncludeDirectories(directoryList)

This method is used to add several extra directories containing Verilog files to the project. This is used when the included files are external to the working directory.

Arguments:

Example:

project.addVerilogIncludeDirectories(['include’, ‘../lib’])

addVlogDefine(name,value)

This method is used to add a parameter definition for Verilog files.

Arguments:

Example:

project.addVlogDefine('G_DATA_SIZE’,'8')

addVlogDefines(dictionnary)

This method is used to add parameters definition for Verilog files.

Arguments:

Example:

project.addVlogDefines({'G_DATA_SIZE’:'8','G_ADDR_SIZE’:'16'})

addWFGLocation(name, location)

This method is used to set the spot in which a WFG should be set.

Placement of WFG elements can also be done during instantiation (with location generic in source code).

Arguments:

Valid locations depend on the variant:

Example:

project.addWFGLocation('wfg_0', 'CKG2.WFG_M3)

adjustAperture(regionName, above, left, right, below)

This method is used to move the aperture of a region or the whole design.

Arguments:

Example:

project.setAperture(6,8,14,12)
project.ajustAperture(2,3,2,2)
p.createRegion('region_0',7,8,9,10)
project.ajustAperture('region_0',2,3,2,2)

applySdcFile(filePath)

This method is used to apply a Synopsys Design Constraints (SDF) file to a project for STA or TimingDriven purpose.

Arguments:

Example:

project.applySdcFile(./sdc_directory/constraints.sdc)

clearBanks()

clearBanks() method remove all bank specification previously added in the project.

This method takes no argument.

Example:

project = createProject()
project.addBank('IOB0', {'voltage': '2.5'})
project.clearBanks()

clearFabricPrePlaceConstraints(regionName)

Clears all preplacing constraints for fabric elements. It removes the impact of the setSite constraint:

It gives the ability to clear all Fabric elements constraints and add new ones.

If no argument is set, constraints for the whole fabric are cleared.

Arguments:

Example:

project = createProject()
project.setSite('i_cpt_0|s_cpt_out_reg[0]', 'TILE[3x2]')
project.clearFabricPreplacedConstraints()
project.setSite('i_cpt_0|s_cpt_out_reg[0]', 'TILE[4x2]')

clearPLLs()

clearPLLs() method remove specification and location for PLLs previously added in the project.

This method takes no argument.

Example:

project = createProject()
project.addPLLLocation('pll_0', 'CKG2.PLL1')
project.clearPLLs()

clearPads()

clearPads() method remove all inputs/outputs of the HDL module previously configured into specific pads of the FPGA.

This method takes no argument.

Example:

project = createProject()
pads = {
	'clk', {'location': 'IO_B1D02P', 'standard': 'LVCMOS', 'drive' :'2mA'},
	'in_row', {'location': 'IO_B1D04P', 'standard': 'LVCMOS', 'drive' :'2mA', 'weakTermination': 'PullUp', 
          'slewRate': 'Slow', 'termination': '50', 'inputDelayLine': 1, 'outputDelayLine': 2, 'differential': False, 
         'turbo': True}
project.addPads(pads))
project.clearPads()

clearPins()

clearPins() method remove all inputs/outputs of the HDL module previously configured into specific pins of the embedded FPGA

This method takes no argument.

Example:

project = createProject()
pins = {
	'A': 'TUI200',
	'B': 'TUI201'
          }
project.addPins(pins)
project.clearPins()

clearWFGs()

clearWFGs() method remove specification and location for WFGs previously added in the project.

This method takes no argument.

Example:

project = createProject()
project.addWFGLocation('wfg_0', 'CKG2.WFG_M3)
project.clearWFGs()

confineModule(name, region)

This method allows to confine a module into a user defined region of the FPGA.

Arguments:

When a module is added to the current project with command, nxpython will generate a module name with automatic incremental syntax in case of listing different modules with similar names. 

Example:

project = createProject()
project.addModule('simple_mult_acc_mem_block*', 'simple_mult_acc_mem_block*', 'simple_mult_acc_mem_block-%')
project.createRegion('PO00',     4, 6,  5, 6)
project.createRegion('PO01',     7, 6,  8, 6)
project.createRegion('PO02',     9, 6,  10, 6)
project.confineModule('simple_mult_acc_mem_block-1', 'PO00')  #incremental module name
project.confineModule('simple_mult_acc_mem_block-2', 'PO01')  #incremental module name
project.confineModule('simple_mult_acc_mem_block-3', 'PO02')  #incremental module name

constrainModule(hierarchy, moduleName, type, leftCol, topRow, width, height, regionName, exclusive)

This method constrains a HDL module into a specific region. The aim of constrainModule is to provide a unique and simple function to perform the whole region driven flow described in Creating and handling regions section.

Signatures:

constrainModule(hierarchy, moduleName, leftCol, topRow, width, height, regionName)

constrainModule(hierarchy, moduleName, type, leftCol, topRow, width, height, regionName)

constrainModule(hierarchy, moduleName, leftCol, topRow, width, height, regionName, exclusive)

constrainModule(hierarchy, moduleName, type, leftCol, topRow, width, height, regionName, exclusive)

Arguments:

Example:

#hierarchy argument is extracted from hierarchy.rpt     
# hierarchy, module name, type, col, row, width, height, regionname, exclusive
project.constrainModule('|-> timer [ Inst_timer ]', 'TIMER_MOD', 'Hard', 13, 12,  19,   3,     'TIMER',    False)

constrainPath(sourceList, targetList, moduleName, type, leftCol, topRow, width, height, regionName, exclusive)

This method constrains a virtual module into a specific region. The aim of this function is to identify source and destination registers in order for all logic elements (LUT, carry) between these registers to be placed into a region created with the regionName argument.

Signatures:

constrainPath(sourceList, targetList, moduleName, leftCol, topRow, width, height, regionName)

constrainPath(sourceList, targetList, moduleName, type, leftCol, topRow, width, height, regionName)

constrainPath(sourceList, targetList, moduleName, leftCol, topRow, width, height, regionName, exclusive)

constrainPath(sourceList, targetList, moduleName, type, leftCol, topRow, width, height, regionName, exclusive)

Arguments:

Example:

 #sourceList, targetList, module name, type, col, row, width, height, region name, exclusive
project.constrainPath(['cntrl|state_reg*'], ['cntrl|state_reg*', 'cntrl|*Write_reg'], 'TEST', 6, 2, 1, 1, 'TEST', True)

createAnalyzer

If a targeted design is already routed, user can launch static timing analysis by creating a timing analyzer.

This method takes no argument.

Example:

project = createProject()
project.load('/home/user/example/vhdl/simple/routed.nym')
analyzer = project.createAnalyzer()

createClock(target, name, period, [rising, falling])

This method is used to create a clock constraint of a timing point. This constraint is used by timing driver algorithms and static timing analysis.

Arguments:

Example:

In the example above, to define a clock with 100MHz for net "Clk", the following three commands are equivalent:

project = createProject()
project.load('routed.nym')
project.createClock(getRegisterClock(reg1'), 'clk', 10000)
or
project.createClock(getPort(Clk'), 'clk', 10000)
or
project.createClock(getClockNet('Clk'), 'clk', 10000, 0, 5000)

createGeneratedClock(source, target, name, relationship)

This method is used to create an internally generated clock constraint at a timing point. This constraint is used by timing driver algorithms and static timing analysis.

Arguments:

Example:

In the example above, the master clock "Clk" was created as 100MHz and the generated clock "clk1" is divided by 2 from the master clock. But noted that the "clk_reg" is driven by falling edge of master clock, the relation between the master clock and generated clock is the following:

project = createProject()
project.load('routed.nym')
project.createClock(getPort('Clk'), 'Clk', 10000)
or
project.createGeneratedClock(getRegisterClock('clk_reg'),getRegisterClock('reg2'), 'clk1', {'DivideBy': 2})
or
project.createGeneratedClock(getClock('Clk'),getRegisterClock('reg2'), 'clk1', {'Edges': [2, 4, 6]})

The relationship generated by above command is:

createObstruction(name, column1, row1, column2, row2)

This method is used to create an obstruction object which will be removed from impulse resources for Place & Route steps.

Arguments:

Example:

project = createProject()
project.load('synthesize.nym')
project.createObstruction('obstr', 10, 2, 24, 6)

createRegion(name, column1, row1, column2, row2, exclusive)

This method is used to create a region among the FPGA resources where HDL elements will be placed during Place step.

Arguments:

Example:

project = createProject()
p.createRegion('ALU',      13, 6, 14, 6)
p.createRegion('REGISTER', 22, 6, 23, 6, True)

createSimulator()

This method is used to create a simulator object. A simulator object is used to simulate the project with a specified testbench.

This method takes no argument.

This method returns an object of class Simulator.

Example:

project = createProject()
project.load('/home/user/example/vhdl/simple/routed.nym')
analyzer = project.createSimulator()

destroyObstruction(name)

This method is used to destroy a given obstruction object.

Arguments:

Example:

project = createProject()
project.load('synthesize.nym')
project.createObstruction('obstr', 10, 2, 24, 6)
project.destroyObstruction('obstr')

destroyRegion(name)

This method is used to destroy a given region.

Arguments:

Example:

project = createProject()
project.createRegion('CNTRL',     4, 6,  5, 6)
project.destroyRegion('CNTRL')

developCKGs()

This method automatically creates a generated clock constraint on each output of the PLLs and WFGs in current project.

This constraint is used by timing driver algorithms and static timing analysis. This method takes no argument.

Ecample:

project = createProject()
project.load('routed.nym')
project.createClock(getClockNet('CLK'), 'clk', 8000, 0, 4000)
project.developCKGs()
project.createGeneratedClock(getWFGOutput('wfg_clk[1]'),getRegister('data_reg[0]'), 'clk1_div2', {'DivideBy': 2})

destroy()

This method is used to destroy the project.

This method takes no argument.

Example:

project = createProject()
project.load('/home/user/example/vhdl/simple/synthesized.nym')
project.display()
project.destroy()
print 'Display after destruction'
project.display()

Output:

Display after destruction
Traceback (most recent call last):
    File "test.py", line 22, in <module>
        project.display()
impulse.error: Invalid Request: Obsolete object

display()

This method is used to open current project in impulse graphic user interface. It can be called several times from the same Python script.

This method takes no argument.

Example:

project = createProject()
project.load('/home/user/example/vhdl/simple/native.nym')
project.synthesize()
project.display()
project.place()
project.display()
project.route()
project.display()

exportAsIPCore(file, options)

This method is used to export the synthesized design to an IPCore. An IPCOre is a HDL description (at NX components level) that can be given as part of new source design to impulse.

The export is different from the save() method as it is done during the second step of synthesis.

Arguments:

The options dictionary must contain at least the coreName key. The following keys are available:

Example:

project = createProject()
project.load('/home/user/example/vhdl/simple/native.nym')
options = { ‘coreName’: ‘IPCore’, ‘encrypt’: ‘All’ }
p.exportAsIPCore(‘IPCore.vhd’, options)
p.synthesize()

exportRegions()

This method is used to export all constrainModule constraints in the console. It can be useful if the user modified the region location or size and want to get new constraints to copy them in the script.

Example:

project.constrainModule('|-> timer [ Inst_timer ]', 'TIMER_MOD', 'Hard', 13, 12,  19,   3, 'TIMER', False)
project.modifyRegion('TIMER', 10, 8, 19, 3)
project.exportRegions()

exportSites(projectVariable,fileName)

This method is used to export all setSite constraints in a file. It can be useful in order to keep all TILE locations.

Example:

project.exportSites('p','site_constraints.py')

generateBitstream(file)

This method is used to save the bitstream configuration file to disk. The extension of the target file must be .nxb

Arguments:

Example:

project = createProject()
project.load('/home/user/example/vhdl/simple/routed.nym')
project.generateBitstream('bitstream.nxb')

generateSTANetlist(filePath,condition)

This method is used to generate routed netlist and SDF file.

Arguments:

Example:

project.route()
project.generateSTANetlist(./output_files/routed_sta_file)

setDeviceID(id)

This method is used to change the Device ID in the bitstream header before generating it.

Arguments:

Example:

project = createProject()
project.load('/home/user/example/vhdl/simple/routed.nym')
p.setDeviceID(10) #Set Device ID to 0xA
project.generateBitstream('bitstream.nxb')

getAnalyzer()

This method returns the current analyzer associated to the project to manage STA.

This method takes no argument.

Example:

project = createProject()
a = project.createAnalyzer()
project.getAnalyzer().launch()

getDirectory()

This method returns the project current directory. This directory is used as root for all relative paths passed as argument of generic functions and/or methods. The default value of the directory is the current working directory.

This method takes no argument.

Example:

project = createProject()
directory = project.getDirectory()

getHierInfo()

This method returns the detailed hierarchy into a dictionary variable.

This method takes no argument.

Example:

project = createProject()
hierarchy = project.getHierInfo()
printText(hierarchy)

getLowskewSignals(ignoreTop, showCandidates)

This method is used to get lowskew signals or potential candidates to be lowskew signals. It gives a table of impacted lobes for each lowskew signal

Arguments:

Example:

project.getLowskewSignals(No,Yes)
project.getLowskewSignals(No)
project.getLowskewSignals()

getProject()

This method returns the project object.

This method takes no argument.

Example:

createProject()
project = getproject()

getTimingUnit()

This method returns the timing unit used in STA.

Example:

printText(project.getTimingUnit())

getTopCellName()

This method returns the name of the top HDL module. If the HDL module is defined inside a library, the name is prefixed by the name of the library followed by a # character.

This method takes no argument.

Example:

project = createProject()
project.setTopCellName('myLib', 'simple')
printText(project.getTopCellName())

Output:

myLib#simple

getVariantName()

This method returns the variant of the project. The default value of the variant is 'NG-MEDIUM'.

This method takes no argument.

Example:

project = createProject()
printText(project.getVariantName())

Output:

NG-MEDIUM

initRegister(command, value)

This method is used to write in registers during the generation of bitstream.

Arguments:

Example:

project = createProject()
project.load('/home/user/example/vhdl/simple/routed.nym')
project.initRegister('SPI_CTRL', '0x01f4003f')
project.generateBitstream('bitstream.nxb')

limitLowskew(signal, lobes)

This method is used to limit a lowskew signal to be used in only specified lobes.

Arguments:

Example:

project.limitLowskew('clk_right','Rx1,Rx2,Rx3,Rx4')

listAvailableLocations(name)

This method is used to print all available pads for a bank or for all banks of a variant .

Arguments:

Example:

project.listAvailableLocations()
project.listAvailableLocations('IOB10')

load(file)

This method is used to load a previously saved project from disk. The input format (file extension) must be .nym (impulse archive).

Arguments:

Example:

project = createProject('/home/user/example/vhdl/simple')
project.load('synthesized.nym')

modifyPad(name, parameters)

This method is used to modify the configuration of an existed pad.

This method takes the same parameters as addPad method.

Parameters that only affect the configuration and not the placing can be changed at any time.

Arguments:

Example:

project.addPad('output[0]',{'location':'IOB10D09P', 'standard': 'LVCMOS', 'drive' :'2mA', 'slewRate':'Slow'})
project.modifyPad('output[0]',{'drive' :'16mA', 'slewRate':'Fast'})

modifyRegion(name, column1, row1, width, height, exclusive)

This method is used to modify the location or the size of an existed region.

Arguments:

Example:

project.constrainModule('|-> timer [ Inst_timer ]', 'TIMER_MOD', 'Hard', 13, 12,  19,   3, 'TIMER', False)
project.modifyRegion('TIMER', 10, 8, 19, 3)

place()

This method is used to run the place algorithm on a project.

This method takes no argument.

Example:

project = createProject()
project.load('/home/user/example/vhdl/simple/synthesized.nym')
project.setOption('TimingDriven', 'Yes')
project.place()

printHierInfo()

This method prints the detailed hierarchy of a project with the module matched and all instances per module.

This methods takes no argument.

Example:

project = createProject()
project.progress('Synthesize', 3)
project.printHierInfo()

progress(step, number)

This method allows to progress through project to a given flow step.

Arguments:

Example:

project = createProject()
project.load('/home/user/example/vhdl/simple/synthesized.nym')
project.progress('Place', 3)

rejectLowskew(signal)

This method avoids local lowskew signal to be converted in global lowskew signal.

Arguments:

Example:

project.rejctLowskew('sub_module0|local_reset')

removeFile(libName, filePath)

This method allows to remove a file from a project.

Arguments:

Example:

project.addFile('work','sub_modul_0.vhd')
project.addFile('work','sub_modul_1.vhd')
project.removeFile('work','sub_modul_0.vhd')
project.removeFile(sub_modul_1.vhd')

removeFiles()

This method allows to remove files from a project.

This method does not

Arguments:

Example:

project.addFiles('work', ['sub_modul_0.vhd', 'sub_modul_1.vhd'])
project.removeFiles('work', ['sub_modul_0.vhd', 'sub_modul_1.vhd'])

removeSoftModules(libName, fileList)

This method allows to remove all HDL soft modules from a project.

This method takes no argument.

Example:

project.constrainModule('|-> timer [ Inst_timer ]', 'TIMER_MOD', 'Soft', 13, 12,  19,   3, 'TIMER', False)
project.removeSoftModules()

reportDesignComplexity(html_file)

This method reports the design complexity, clock domain by clock domain, indicating the logic depth for all paths of the design and illustrates it with a chart in HTML format:

Example:

project.reportDesignComplexity('design_complexity.html')

The output HTML file looks like:

 reportHierarchyComplexity()

This method reports the design complexity module by module in the hierarchy and clock domain by clock domain, indicating the number of paths by logic depth.

Output filed are named hierarchyComplexity with .json and .rpt extension.

This method takes no argument.

Example:

project.reportHierarchyComplexity()

reportInstances()

This method reports the instances utilization of the programmed design on the current variant. Three tables are printed. The first one contains values for all types of instances. The instances are grouped by categories:

The second table gives more details about 4-LUTs utilization:

The last table gives detailed information about the use of registers:

This method takes no argument.

Example:

project = createProject()
project.load('/home/user/example/vhdl/simple/synthesized.nym')
project.reportInstances()

Output:

reportLowskewSignals(logfile)

This method reports the lowskew signals:

Example:

project.reportLowskewSignals('lowskew_report')

reportPorts()

This method reports the ports found in HDL source and the ones manually added by user in the project. The report displays the following information:

This method takes no argument.

Example:

project = createProject()
project.load('/home/user/example/vhdl/simple/placed.nym')
project.reportPorts()

reportRegions()

This method reports occupied resources by HDL elements within every region created in the FPGA.

This method takes no argument.

Example:

project = createProject()
project.addModule('mCntrl', 'cntrl', 'cntrl-%')
project.createRegion('CNTRL', 4, 6, 5, 6)
project.confineModule('cntrl-1', 'CNTRL')
project.synthesize()
project.place()
project.reportRegions()

The report displays the amount and percentage placed in the created region:

resetTimingConstraints()

This method is used to reset all timing constraints for current project.

 This includes clocks, generated clocks, derived clocks of PLLs and WFGs, input delays, output delays, clock groups, case analysis, false paths, multicycle paths, min delay paths and max delays paths.

This method takes no argument.

Example:

project = createProject()
project.load('/home/user/simple/routed.nym')
project.resetTimingConstraints()

route()

This method is used to run the route algorithm on a project.

This method takes no argument.

Example:

project = createProject()
project.load('/home/user/example/vhdl/simple/placed.nym')
project.setOption('TimingDriven', 'Yes')
project.route()

save(file,conditions)

This method is used to save the current project into a impulse archive (.nym), a design netlist (.v or .vhd) or to generate a sdf file containing delays of the design supporting bestcase, worstcase and typical scenarios.

Arguments:

Example:

project = createProject()
project.load('native.nym')
project.synthesize()
project.save('synthesized.nym')
project.save('synthesized.vhd')
project.route()
project.save(‘routed.vhd’)
project.save('sdf_file_bestcase.sdf','bestcase') #generate a sdf file defining bestcase scenario
project.save('sdf_file_worstcase.sdf','worstcase') #generate a sdf file defining worstcase scenario
project.save('sdf_file_typical.sdf','typical') #generate a sdf file defining typical scenario
project.save(‘routed.sdf’)

setAnalysisConditions(conditions)

This method is used to specify the chip conditions for static timing analysis.

This constraint is used by timing driver algorithms and static timing analysis.

Arguments:

Example:

project.setAnalysisConditions(WorstCase)

setAperture(column1, row1, column2, row2)

This method is used to define the size of aperture. The default size value is bounded to the Fabric dimensions.

Arguments:

Example:

project = createProject()
project.load('synthesize.nym')
project.setAperture(10, 2, 24, 6)

setCaseAnalysis(value, net_list)

This method is used to specify a constant logic value to the given tests.

This constraint is used by timing driver algorithms and static timing analysis.

Arguments:

setClockGroup(group1_list, group2_list, option)

This method is used to specify which clocks are not related. This constraint is used by timing driver algorithms and static timing analysis. 

Arguments:

 Example:

project = createProject()
project.load('routed.nym')
project.createClock(getClockNet(CLOCK[1]'), 'clk1', 2700)
project.createClock(getClockNet(CLOCK[2]'), 'clk2', 5000, 0, 2000)
project.setClockGroup(getClock('clk1'),getClock('clk2'), 'exclusive')

setDescription(description)

This method is used to set a description to a project.

Arguments:

Example:

project = createProject()
project.setDescription('Impulse project for training')

setDirectory(directory)

This method is used to change project directory.

Arguments:

Example:

project = createProject()
project.setDirectory('./new_dir')

setFocus(column, row)

This method is used to specify the position of the focus.

Arguments:

Example:

project = createProject()
project.load('synthesize.nym')
project.setFocus(4, 4)

setGCKCount(count)

This method is used to limit the number of GCK at the end of Placing step 2.

Arguments:

Example:

project.setGCKCount(20)

setInputDelay(clock, clock_mode, minimum_delay, maximum_delay, port_list)

This method specifies the data arrival times at the specified input ports relative to the clock. The clock must refer to a clock name in the design. This constraint is used by timing driven algorithms and static timing analysis.

Arguments:

Example:

project = createProject()
project.load('routed.nym')
project.createClock(getClockNet('CLK'), 'CLK', 8000)
project.setInputDelay(getClock('CLK'), 'rise', 1000, 1500,getPort('RST'))

setOption(name, value)

This method is used to set the value of a nxpython option. An option can be set at any time of the design flow.

Arguments:

The available options are:

“00”, “01”, “10”

“001”, “010”, “100”

Some options can affect only specific processes of the design flow. Following, a table of the specific processes per options: