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Feature

  • NG-ULTRA is now available on NX design suite tools

  • NxDC/Nxpython : The following methods are compliant with NxMap:

    • reportTiming (from registers to registers)

    • CreateClock

    • CreateGeneratedClock

    • SetClockGroup

    • SetFalsePath

    • SetMulticyclePath

    • SetMin/MaxDelay

    • SetInput/OutputDelay

    • SetCaseAnalysis

    • SetAnalysisConditions

    • DevelopCKGs

Constraint

  • Constrainpath DSP register: Source or destination register can be inside a DSP

  • Lowskew management: lowskew signals can be managed using getLowskewSignals, setGCKCount and limiLowskew methods in order to exceed +20 lowskew signals

  • Method exportSites: to export placement constraints for LUTs, DFFs, RAMs, RFs, DSPs, CYs of the design

  • Method rejectLowskew: to avoid routing signals into lowskew tree

  • Method addBlackBox: to add preplaced IP into design

Primitive

  • Header: Get NxMap release information in nxLibrary files headers

  • SERDES primitives : implement “locked” in generics

Logging

  • Module instance reporting: Indicates memories and operators used n each design module

  • Infinite loop reporting: Logs give the net + the file and line

  • Register optimization: Get information about optimized registers in registers.rpt

  • Module and Region in STA: Get the associated region and module in STA detailed path

  • DFF reporting : Get type of the DFF (DFF/DFR) in registersSummary.rpt + get number of DFF by primitive (FE/DSP/RAM/PAD)

  • Operator in LUT: Adders mapped in LUT appear in reports

Netlist

  • Header: Get NxMap release information in a header

Tool

  • Saved STA: STA can be saved in .nym projects setting 'SaveTiming' option to 'Yes'

  • Large multiplication in ULTRA: compliance with much larger multiplication using CY for adders for better STA optimization

  • ULTRA renaming: ULTRA is renamed in ULTRA1 and ULTRA2 in ULTRA

  • NXScopeV2: New Scope IP is compliant and can be used in NG-ULTRA

  • Compilation in NX library: NX is a forbidden library to compile

Bug

Constraint

  • addMappingDirective for a RAM in DFF : Tool was not able to map a RAM into DFF if infered memory is compiled in a library

Primitive

Logging

  • NX_DFF reporting : NX_DFF primitive in the design is now reported

  • addFalsePath all registers, if source or target is empty, number of found registers is *

Netlist

  • NX_HSSL_L: netlist generation is now compliant with NX_HSSL_L primitive

  • NX_PLL_L: use_pll generic is now mapped

Tool

  • Attributes: attributes were ignored in some cases + log during synthesis added

  • Differential pad with suffix : pads with suffixes like “_DQS_SWDI” were not able to be configured in differential mode

  • DSP registers with asynchronous reset : asynchronous reset DFF cannont be merged in DSP

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