Introduction
The aim of this document is to explain how to simulate a design dedicated to NanoXplore targets under Questa/Modelsim tools.
The needed minimum version is modelsim 10.6d
Design simulation
The user design may include NX primitives with files calling nx package as follow in a VHDL file:
library nx; use nx.nxpackage.all;
Consequently, the compilation script must include this package and all primitives architectures.
There is one file per variant so for instance, for NG-ULTRA target, the file to compile is stored in each release in the following path:
nxmap-<version_number>/share/modelsim/nxLibrary-<variant_name>.vhdp
For instance, for NG-MEDIUM or NG-MEDIUM-EMBEDDED target, with nxmap 22.1.0.1 release, the path is:
nxmap-dbg-22.1.0.1/share/modelsim/nxLibrary-Medium.vhdp
Only components and entities are declared in the clear part.
Architecture models are private and encrypted so.
Hereafter an example of TCL script to compile and simulate a design:
vlib nx vcom -work nx -2008 nxmap-dbg-22.1.0.1/share/modelsim/nxLibrary-Medium.vhdp vlib work vcom -work work -2008 sub_module1.vhd vcom -work work -2008 sub_module1.vhd
Netlist simulation
It can be useful to simulate a design with the output netlist generated after synthesis. Indeed, it give the ability to check NXmap synthesis tool mapped correctly the design into a flattened design containing only NX primitives even after optimizations.
The netlist must be generated using NXmap tool as follow:
p.save('<file_name>.<extension>')
Output netlist can be in VHDL or verilog code.
Generate an output netlist after at least synthesizing step 2.