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The NX_GCK_U component describes a configurable ClocK Switch circuit that allows glitch free clock generation. It can be used to enable/disable the clock to part of the user’s logic – providing that the output signal will be glitch free – and the delay from the main clock to the generated one is un-significantinsignificant.

NX_GCK_U can be configured into the following modes:

BYPASS: Input signal from lowskew network is copied on output still in lowskew network.
MUX: 2 input signals from lowskew network are MUXed with a control command from common network.
CKS: Input signal from lowskew network is copied or not, depending on control command from common network, on output still in lowskew network.
CSC: Input signal from common network is copied on output in lowskew network.

The NX_GCK_U can be used exclusively by instantiation. The current version of NXmap3 does not yet support inference for this device.

Generics

inv_in

type bit

default value ‘0’

This generic select wether to invert (inv_in = ‘1’) or not both clock inputs pins SI1 and SI2.

inv_out

type bit

default value ‘0’

This generic select wether to invert (inv_out = ‘1’) or not the clock output pin SO.

std_mode

type string

default value “BYPASS”

Select the configuration mode of the NX_GCK_U. NX_GCK_U can be configured into the following modes:

...

Ports	Direction	Type	Description	Network
SI1	input	std_logic	First Input clock	Lowskew
SI2	input	std_logic	Second Input clock	Lowskew
CMD	Input	Std_logic	Command input	Common
SO	output	std_logic	Output clock	Lowskew

Examples

This documentation only provides the instantiation of the component.

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The NX_CKS component describes a ClocK Switch circuit that allows glitch free clock generation. It can be used to enable/disable the clock to part of the user’s logic – providing that the output signal will be glitch free – and the delay from the main clock to the generated one is un-significantinsignificant. NX_CKS implements and automatically configures a NX_GCK_U primitive in CKS mode.

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Figure 2: NG-ULTRA CKG block diagram

The next figure shows a block diagram of the NX_PLL_U and the user’s settings (in yellow).

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Figure 3: Simplified NG-ULTRA PLL block diagram

Generics

location

type string

default value “”

This generic allows to define the NX_PLL_U location directly in the source code (instead of using the nxpython addPLLLocation method).

Example : location => “CKG2.PLL1”

use_pll

type bit

default value 0

Set to 1 to enable the PLL. When set to 0, the PLL is bypassed with Fvco = Frefo.

pll_odf

type bit_vector (1 downto 0)

default value others => ‘0’

Define the output division factor of the PLL (factors: 1, 2, 5 and 10).

pll_odf	Output Division factor
0	1
1	2
2	5
3	10

pll_lock

type bit_vector (1 downto 0)

default value others => ‘0’

Configure the frequency lock.

pll_lock value	PPM approx
0	20
1	40
2	60
3	80
4	100
5	200
6	400
7	600
8	800
9	1000
10	2000
11	4000
12	6000
13	8000
14	10000
15	20000

ref_intdiv

type bit_vector (4 downto 0)

default value others => ‘0’

The REFerence frequency can be divided by factors ranging from 1 to 32 before reaching the VCO input. This allows to give more flexibility of the PLL generated output frequency, and increase the PLL input frequency range.

REF input frequency range	ref_intdiv value	Vco input frequency
5 to 50 MHz	0	Fref
10 to 100 MHz	1	Fref / 2
15 to 150 MHz	2	Fref / 3
20 to 200 MHz	3	Fref / 4
…	...	…
150 MHz to 1,5 GHz	29	Fref / 30
155 MHz to 1,55 GHz	30	Fref / 31
160 MHz to 1,6 GHz	31	Fref / 32

For VCO expected at 400MHz, ref_intdiv value must be set to 8 with a REF input frequency range between 45 and 450 Mhz.

ref_osc_on

type bit

default value ‘0’

This generic configures the source of the PLL reference.

If ref_osc_on is set to ‘0’, the input reference of the pll is the REF input pin.

If set to ‘1’, the internal oscillator is used as reference of the PLL.

ext_fbk_on

type bit

default value ‘0’

When ‘0’, the internal feedback path is selected. The output of the FBK_INTDIV divider is used as feedback source. The VCO output frequency is divided by (fbk_intdiv + 1)

When ‘1’, the external feedback path is selected. This is particularly useful for “zero delay” clock generation.

fbk_intdiv

type bit_vector (6 downto 0)

default value others => ‘0’

Internal feedback divider of N+1 ratio (with division from 1 to 128).

fbk_delay_on

type bit

default value ‘0’

This generic configures whether the delay of the feedback path is active (‘1’) or not (‘0’).

fbk_delay

type bit_vector (5 downto 0)

default value others => ‘0’

The number of delay taps on the feedback path (internal or external) can be adjusted to meet the required phase on the VCO outputs. When using external feedback, it can be used to compensate the delay on the reference clock input to the REF pin of the PLL via the semi-dedicated clock input pin and associated direct routing.

The delay can be selected or not (see fbk_delay_on). When selected, it can be adjusted from 340 ps (fbk_delay = 0) to 10580 6740 ps (fbk_delay = 63) by steps of 160 100 ps.

clk_outdiv1 : applies to CLK_DIV1

type bit_vector (2 downto 0)

default value others => ‘0’

...

CLK_DIV1 = Fpll/(2*7+3) = Fpll / 17

clk_outdiv2 : applies to CLK_DIV2

type bit_vector (2 downto 0)

default value others => ‘0’

...

CLK_DIV2 = Fpll/(2*7+5) = Fpll / 19

clk_outdiv3 : applies to CLK_DIV3

type bit_vector (2 downto 0)

default value others => ‘0’

...

CLK_DIV3 = Fpll/(2*0+5) = Fpll / 7

If clk_outdiv3 = 7

CLK_DIV3 = Fpll/(2*7+5) = Fpll / 21

clk_outdiv4 : applies to CLK_DIV4

type bit_vector (2 downto 0)

default value others => ‘0’

...

CLK_DIV4 = Fpll/(2*0+5) = Fpll / 9

If clk_outdiv4 = 7

CLK_DIV4 = Fpll/(2*7+5) = Fpll / 23

clk_outdivd* : applies to CLK_DIVD*

type bit_vector (3 downto 0)

default value others => ‘0’

...

This generic allows to define the divider value of the CLK_DIVD* output. There are 16 possible values:

clk_outdivd*	ratio	Fpll_div_dyn (ex: Fpll = 800Mhz)
0	2	400
1	4	200
2	6	133.33
3	8	100
4	10	80
5	20	40
6	40	20
7	60	13.33
8	80	10
9	100	8
10	200	4
11	400	2
12	600	1.33
13	800	1
14	1000	0.8
15	2000	0.4

* clk_outdivd1/2/3/4/5 respectively apply to CLK_DIVD1/2/3/4/5

use_cal

type bit

default value ‘0’

When set to 0, the calibration module is bypassed. When set to 1, the calibration module is activated with cal_div and cal_delay generics used to define divide and delay values of the calibration engine.

clk_cal_sel

type bit_vector (1 downto 0)

default value “01”

Select the clock used for internal calibration.

cal_div

type bit_vector (3 downto 0)

default value “0111”

Set the division factor of the calibration engine.

cal_delay

type bit_vector (5 downto 0)

default value “011011”

Set the delay value of the calibration engine.

Notes about user’s adjustable delays on NG-ULTRA:

The PLL has a user’s selectable and adjustable delay line (no delay or 0 to 63 x 100 ps +/- 5% delay taps) on the feedback path. A similar delay chain is available in each WFGs. Finally, the IO banks have input, output and tri-state command 64-tap delay chains.

All the delay chain taps are calibrated with the same automatic process and hardware resources.

The procedure is transparent to the user.

The delays calibration system uses the PLL 400 MHz oscillator output as reference clock to calibrate all delays: feedback path in the PLL itself, WFG delays and calibration delay in same CKG), and IO delays in the neighboring complex IO banks:

CKG1 oscillator calibrates the delays in CKG1 (PLL + CAL+ WFGs)
- Banks 11 to 13
CKG2 oscillator calibrates the delays in CKG2 (PLL + CAL + WFGs)
- Banks 2 to 3
CKG3 oscillator calibrates the delays in CKG3 (PLL + CAL + WFGs)
CKG4 oscillator calibrates the delays in CKG4 (PLL + CAL + WFGs)
- Banks 4 to 5
CKG5 oscillator calibrates the delays in CKG5 (PLL + CAL+ WFGs)

Banks 8 to 10

CKG6 oscillator calibrates the delays in CKG6 (PLL + CAL+ WFGs)
- Banks 8 to 10
CKG7 oscillator calibrates the delays in CKG7 (PLL + CAL+ WFGs)
- Banks 11 to 13

The calibration procedure takes about 10 µs at startup. The “CAL_LOCKED” output goes high when the delay calibration process is complete. Can be used as status bit.

Ports

Ports

Direction

Type

Description

REF

In

std_logic

Reference clock input

Connectivity: semi-dedicated clock inputs, clock trees (low skew network)

FBK

In

std_logic

External FeedBack input

Connectivity: semi-dedicated clock inputs, clock trees (low skew network)

R

In

std_logic

Active high Reset input. Must be activated when REF input frequency changes to force a re-locking process of the PLL

ARST_CAL

In

std_logic

Active high asynchronous reset input of the calibration module

CAL_CLK

In

std_logic

Clock input of the calibration module.

EXT_CAL_LOCKED

In

sdt_logic

Input of the calibration module coming from the fabric. Indicates the calibration is locked

EXT_CAL1/2/3/4/5

In

sdt_logic

Input of the calibration module coming from the fabric. Indicates the calibration value send by fabric

VCO

Out

std_logic

VCO output:

- Fvco = REF * 2 * (fbk_intdiv+1) / (ref_intdiv+1) with use_pll = 1

- Fvco = Frefo when use_pll = 0

REFO

Out

std_logic

Output of the REFerence divider. The division factor is set by the generic “ref_intdiv”

LDFO

Out

std_logic

Output of the FBK_INTDIV divider. The division factor is set by the generic ‘fbk_intdiv”

CLK_DIV1

Out

std_logic

This output delivers a divided (by 2N+3) PLL frequency or REF frequency (in case PLL is bypassed). The division factor is set by the generic “clk_outdiv1”

CLK_DIV2

Out

std_logic

This output delivers a divided (by 2N+5) PLL frequency or REF frequency (in case PLL is bypassed). The division factor is set by the generic “clk_outdiv2”

CLK_DIV3

Out

std_logic

This output delivers a divided (by 2N+7) PLL frequency or REF frequency (in case PLL is bypassed). The division factor is set by the generic “clk_outdiv3”

CLK_DIV4

Out

std_logic

This output delivers a divided (by 2N+9) PLL frequency or REF frequency (in case PLL is bypassed). The division factor is set by the generic “clk_outdiv4”

CLK_DIVD1

Out

std_logic

This output delivers a dynamically divided (by N+2) PLL frequency or REF frequency (in case PLL is bypassed). The division factor is set by the generic “clk_outdivd1”

CLK_DIVD2

Out

std_logic

This output delivers a dynamically divided (by N+2) PLL frequency or REF frequency (in case PLL is bypassed). The division factor is set by the generic “clk_outdivd2”

CLK_DIVD3

Out

std_logic

This output delivers a dynamically divided (by N+2) PLL frequency or REF frequency (in case PLL is bypassed). The division factor is set by the generic “clk_outdivd3”

CLK_DIVD4

Out

std_logic

This output delivers a dynamically divided (by N+2) PLL frequency or REF frequency (in case PLL is bypassed). The division factor is set by the generic “clk_outdivd4”

CLK_DIVD5

Out

std_logic

This output delivers a dynamically divided (by N+2) PLL frequency or REF frequency (in case PLL is bypassed). The division factor is set by the generic “clk_outdivd5”

OSC

Out

std_logic

Internal 400 MHz oscillator

Connectivity: WFG inputs, delay calibration engine

PLL_LOCKED

Out

std_logic

High when PLL is locked synchronously (fine grain)

Connectivity: RDY inputs of WFGs, fabric…

PLL_LOCKEDA

Out

std_logic

High when PLL is locked asynchronously (coarse grain)

Connectivity: RDY inputs of WFGs, fabric…

CLK_CAL_DIV

Out

std_logic

Divided Clock of the calibration module sent to fabric

CAL_LOCKED

Out

std_logic

High when the automatic calibration procedure of the current FPGA quarte area is complete

Connectivity: fabric

CAL1/2/3/4/5

Out

std_logic

Calibration value sent to fabric

...

Figure 4: NX_WFG_U diagram

Generics

location

type string

default value “” (no location constraint)

This generic allows to define the NX_WFG_L location directly in the source code (with the addWFGLocation method)

Example : location => “CKG2.WFG_C2”,

delay

type integer

default value 0

...

The following is the declaration of the component NX_DSP_U_SPLIT, included in the nxLibrary-Ultra.vhdp package.

component NX_DSP_U_SPLIT

generic (

-------------------------------------------------------------------------

...

-------------------------------------------------------------------------

SIGNED_MODE : bit := '0';

INV_WE : bit := '0';

INV_WEZ : bit := '0';

INV_RST: bit := '0';

INV_RSTZ : bit := '0';

ALU_DYNAMIC_OP : bit_vector(1 downto 0) := B"00"; -- '00' for Static,

-- '-1' for Dynamic control from C

-- '10' for Dynamic control from D

SATURATION_RANK : bit_vector(5 downto 0) := B"000000"; -- Weight of useful MSB on Z and CZO result

-- (to define saturation and overflow)

ENABLE_SATURATION : bit := '0'; -- '0' for Disable, '1' for Enable

MUX_CCO : bit := '0'; -- '0' for CCO = ALU(42), '1' for CCO = ALU(56)

MUX_Z : bit := '0'; -- Select Z output. '0' for Y, '1' Saturation / ALU

MUX_CZ : bit := '0'; -- Select MUX_X input. '0' for CZI, '1' for CZO

MUX_Y : bit := '0'; -- Select ALU's Y input. '0' for MULT output, '1' for (B & A)

MUX_X : bit_vector(2 downto 0) := B"000"; -- Select MUX_X operation

...

-- "110" for MUX_X >> 17

-- "111" for MUX_X >> 18

MUX_CCI : bit := '0'; -- Select '1' input of CI mux. '0' for CCI, '1' for CO_feddback

MUX_CI : bit := '0'; -- Select input carry of ALU. '0' for CI, '1' for CCI/CO_feedback mux

MUX_P : bit := '0'; -- '0' for PRE_ADDER, '0' for B input

MUX_B : bit := '0'; -- '0' = B input, '1' = CBI input

MUX_A : bit := '0'; -- '0' = A input, '1' = CAI input

PRE_ADDER_OP : bit := '0'; -- '0' = Add, '1' = Sub

-------------------------------------------------------------------------

...

-------------------------------------------------------------------------

PR_WE_MUX : bit := '0'; -- '0' for No pipe reg, '1' for 1 pipe reg

PR_WEZ_MUX : bit := '0'; -- '0' for No pipe reg, '1' for 1 pipe reg

PR_RST_MUX : bit := '0'; -- '0' for No pipe reg, '1' for 1 pipe reg

PR_RSTZ_MUX : bit := '0'; -- '0' for No pipe reg, '1' for 1 pipe reg

PR_OV_MUX : bit := '0'; -- '0' for No pipe reg, '1' for 1 pipe reg

PR_CO_MUX : bit := '0'; -- Registered carry out (CO42 & CO56)

PR_CCO_MUX : bit := '0'; -- Registered cascade carry out

PR_Z_MUX : bit := '0'; -- Registered output

PR_CZ_MUX : bit := '0'; -- Registered Cascade output

PR_Y_MUX : bit := '0'; -- '0' for No pipe reg, '1' for 1 pipe reg

PR_X_MUX : bit := '0'; -- '0' for No pipe reg, '1' for 1 pipe reg

PR_CI_MUX : bit := '0'; -- '0' for No pipe reg, '1' for 1 pipe reg

PR_MULT_MUX : bit := '0'; -- No pipe reg -- Register inside MULT

PR_P_MUX : bit := '0'; -- '0' for No pipe reg, '1' for 1 pipe reg (Pre-adder)

PR_D_MUX : bit := '0'; -- '0' for No pipe reg, '1' for 1 pipe reg

PR_C_MUX : bit := '0'; -- '0' for No pipe reg, '1' for 1 pipe reg

PR_B_CASCADE_MUX : bit_vector(1 downto 0) := "00"; -- Number of pipe reg levels for CAO output. "-0" for 0 level, "01" for 1 level, "11" for 2 levels

PR_B_MUX : bit_vector(1 downto 0) := "00"; -- Number of pipe reg levels on B input. "-0" for 0 level, "01" for 1 level, "11" for 2 levels

PR_A_CASCADE_MUX : bit_vector(1 downto 0) := "00"; -- Number of pipe reg levels for CAO output. "-0" for 0 level, "01" for 1 level, "11" for 2 levels

PR_A_MUX : bit_vector(1 downto 0) := "00"; -- Number of pipe reg levels on A input. "-0" for 0 level, "01" for 1 level, "11" for 2 levels

...

-------------------------------------------------------------------------

ENABLE_PR_OV_RST : bit := '1'; -- '0' for Disable, '1' for Enable

ENABLE_PR_CO_RST : bit := '1'; -- '0' for Disable, '1' for Enable

ENABLE_PR_CCO_RST : bit := '1'; -- '0' for Disable, '1' for Enable

ENABLE_PR_Z_RST : bit := '1'; -- '0' for Disable, '1' for Enable

ENABLE_PR_CZ_RST : bit := '1'; -- '0' for Disable, '1' for Enable

ENABLE_PR_Y_RST : bit := '1'; -- '0' for Disable, '1' for Enable

ENABLE_PR_X_RST : bit := '1'; -- '0' for Disable, '1' for Enable

ENABLE_PR_CI_RST : bit := '1'; -- '0' for Disable, '1' for Enable

ENABLE_PR_MULT_RST : bit := '1'; -- '0' for Disable, '1' for Enable

ENABLE_PR_P_RST : bit := '1'; -- '0' for Disable, '1' for Enable

ENABLE_PR_D_RST : bit := '1'; -- '0' for Disable, '1' for Enable

ENABLE_PR_C_RST : bit := '1'; -- '0' for Disable, '1' for Enable

ENABLE_PR_B_RST : bit := '1'; -- '0' for Disable, '1' for Enable

ENABLE_PR_A_RST : bit := '1'; -- '0' for Disable, '1' for Enable

-- PR_CZ_INIT : bit_vector(5 downto 0) := B"000000"; -- Value of CZ's pipe register on reset

...

-------------------------------------------------------------------------

ALU_OP : bit_vector(2 downto 0) := B"000"; -- ALU operation

-- x+y+c = "000"

...

-- -x+y-c = "110"

-- -x-y+c-2 = "111"

);

port(

CK : IN std_logic;

R : IN std_logic;

RZ : IN std_logic;

WE : IN std_logic;

WEZ : IN std_logic;

CI : IN std_logic;

A : IN std_logic_vector(23 downto 0);

B : IN std_logic_vector(17 downto 0);

C : IN std_logic_vector(35 downto 0);

D : IN std_logic_vector(17 downto 0);

CAI : IN std_logic_vector(23 downto 0);

CBI : IN std_logic_vector(17 downto 0);

CZI : IN std_logic_vector(55 downto 0);

CCI : IN std_logic;

Z : out std_logic_vector(55 downto 0);

CO42 : OUT std_logic;

CO56 : OUT std_logic;

OVF : OUT std_logic;

CAO : OUT std_logic_vector(23 downto 0);

CBO : OUT std_logic_vector(17 downto 0);

CZO : OUT std_logic_vector(55 downto 0);

CCO : OUT std_logic

);

end component

NX_DSP_U_WRAP

Description

The NX_DSP_U_WRAP component provides a wrapper around NX_DSPU IP for user convenience, concatening bits into vector interfaces. The generics are the same as NX_DSP_U, check the associated section for detail explanations.

...

type string (value in ohms – range 30 to 80depends on variant and bank voltage)