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This document aims to list all the the nxpython methods available to apply timing constraints on a design

...

.

Table of Contents

minLevel	1
maxLevel	7

createClock( )

/ ! \ DEPRECATED / ! \ Please use setFalsePath instead, with the same key argumentsThis method is used to specify the false path for the timing paths. This constraint is used createClock(target = ‘target', name = ‘name’, period = ]0, ], rising = [0,period[, falling = ]rising, rising+period]) instead. This method is described immediately below.

This method is used to create a clock constraint at a timing point. This constraint is used by timing driven algorithms and static timing analysis. Depending on the unit defined in the project, timings are in ns or ps.

Signatures:

createClock(target, name, period)

createClock(target, name, period, rising)

createClock(target, name, period, rising, falling)

Arguments:

...

Name

Type

Description

from_list

target

string

the command which specifies

Specifies how to get a

timing path starting points

clock related point. A valid

timing starting point is an input port or a register. A valid command

argument can be: getPort(port_name),

getPorts

getRegisterClock(register_name

_expression

)

,

or getRegister(register_name),

getRegisters

getClockNet(

name_expression), getRegistersByClock(clock

clock_net_name).

to_list

name

string

the command which specifies how to get a timing path ending points. A valid timing ending point is an output port or a register. A valid command can be: getPort(port_name), getPorts(name_expression), getRegister(register_name), getRegisters(name_expression), getRegistersByClock(clock_name)

Example:

...

User clock name of the created clock.
period	float	The period value.
rising	float	Specifies the rising edge for clock waveform. Range [0, period[ (the default value is 0)
falling	float	Specifies the falling edge for clock waveform. Range ]rising, rising + period] (default value is period/2)

Note
The name of the clock net is case sensitive

Examples:

...

In the example above, to define a 100MHz clock for net “Clk”, the following three commands are equivalent :

Code Block

language	py

project = createProject()
project.load('routed.nym')
project.addFalsePathcreateClock('getRegister('UUT1|Gen_seq[3].seq_i|temp_reg[1]'getRegisterClock(reg1)', 'getRegister('UUT2|dout_reg[61]')')clk', 10)
or 
project.addFalsePathcreateClock('getRegistersByClockgetPort(clk1Clk)', 'getRegistersByClock(clk2)')clk', 10)
or 
project.addFalsePathcreateClock('getRegister(cpt_in_p_reg[0]getClockNet(Clk)', 'clk')
project.addFalsePath('getPort(cpt_in[0])','getRegisters("cpt_in_p_reg[`[0-3]`]")')
project.addFalsePath('getPorts("cpt_in[`[0-3]`]")', 'getRegistersByClock(clk2)')
project.addFalsePath('getRegistersByClock(clk1)', 'getWFGOutput(i_WFG_0)')

In order to match with all registers, it is possible to specify empty string ('') for parameters from_list or to_list.

addMaxDelayPath(from_list, to_list, delay)

/ ! \ DEPRECATED / ! \ Please use setMaxDelay instead, with the same key arguments

This method is used to specify the maximum delay path for the timing paths. It is used by timing driven algorithms and static timing analysis.

Arguments:

...

Name

...

Type

...

Description

...

from_list

...

string

...

the command which specifies how to get a timing path starting points. A valid timing starting point can be either an input port or a register. A valid command can be: getPort(port_name), getPorts(name_expression),
getRegister(register_name), getRegisters(name_expression), getRegistersByClock(clock_name)

...

to_list

...

string

...

the command which specifies how to get a timing path ending points. A valid timing ending point can be either an output port or a register. A valid command can be: getPort(port_name), getPorts(name_expression),
getRegister(register_name), getRegisters(name_expression), getRegistersByClock(clock_name)

...

delay

...

float

...

the required maximum delay value in ns for specified paths.

Example:

Code Block

language	py

project = createProject()
project.load('routed.nym')
project.addMaxDelayPath('getRegister('UUT1|Gen_seq[3].seq_i|temp_reg[1]')', 'getRegister('UUT2|dout_reg[61]')', 3.9)
project.addMaxDelayPath('getPort(cpt_in[0])', 'getRegister(i_cpt_1|s_cpt_out_reg[1])', 8.0)         
project.addMaxDelayPath('getRegister(i_cpt_0|s_cpt_out_reg[0])','getRegister(i_cpt_1|s_cpt_out_reg[1])', 4.0) 
project.addMaxDelayPath('getPorts("cpt_in[`[1-3]`]")','getRegister(i_cpt_1|s_cpt_out_reg[1])', 8.0)  
project.addMaxDelayPath('getRegisters("i_cpt_0\|s_cpt_out_reg[`[1-3]`]")', 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', 8.0)

addMinDelayPath(from_list, to_list, delay)

/ ! \ DEPRECATED / ! \ Please use setMinDelay instead, with the same key arguments.

This method is used to specify the minimum delay path for the timing paths. It is used by timing driven algorithms and static timing analysis.

Arguments:

...

Name

...

Type

...

Description

...

from_list

...

string

...

the command which specifies how to get a timing path starting points. A valid timing starting point can be either an input port or a register. A valid command can be: getPort(port_name), getPorts(name_expression),
getRegister(register_name), getRegisters(name_expression), getRegistersByClock(clock_name)

...

to_list

...

string

...

the command which specifies how to get a timing path ending points. A valid timing ending point can be either an output port or a register. A valid command can be: getPort(port_name), getPorts(name_expression),
getRegister(register_name), getRegisters(name_expression), getRegistersByClock(clock_name)

...

delay

...

float

...

the required minimum delay value in ns for specified paths.

Example:

Code Block

language	py

project = createProject()
project.load('routed.nym')
project.addMinDelayPath(getRegister('UUT1|Gen_seq[3].seq_i|temp_reg[23]'), getRegister('UUT1|Gen_seq[3].seq_i|temp_reg[22]'), 1.2)
project.addMinDelayPath(getPort(cpt_in[0]), getRegister(i_cpt_1|s_cpt_out_reg[1]), 8.0)
project.addMinDelayPath(getRegister(i_cpt_0|s_cpt_out_reg[0]), getRegister(i_cpt_1|s_cpt_out_reg[1]), 8.0)
project.addMinDelayPath(getPorts("cpt_in[`[1-3]`]"), getRegister(i_cpt_1|s_cpt_out_reg[1]), 8.0)
project.addMinDelayPath(getRegisters("i_cpt_0\|s_cpt_out_reg[`[1-3]`]"), getRegister(i_cpt_1\|s_cpt_out_reg[1]), 8.0)

addMulticyclePath(from_list, to_list, cycle_count)

/ ! \ DEPRECATED / ! \ Please use setMulticyclePath instead, with the same key arguments.

This method is used to specify the multicycle path for the timing paths. It is used by timing driven algorithms and static timing analysis.

Arguments:

...

Name

...

Type

...

Description

...

from_list

...

string

...

the command which specifies how to get a timing path starting points. A valid timing starting point can be either an input port or a register. A valid command can be: getPort(port_name), getPorts(name_expression),
getRegister(register_name), getRegisters(name_expression), getRegistersByClock(clock_name).
Valid ports mush be constrained by 'setInputDelay'.

...

to_list

...

string

...

the command which specifies how to get a timing path ending points. A valid timing ending point can be either an output port or a register. A valid command can be: getPort(port_name), getPorts(name_expression),
getRegister(register_name), getRegisters(name_expression), getRegistersByClock(clock_name).
Valid ports must be constrained by 'setOutputDelay'.

...

cycle_count

...

unsigned

...

An unsigned value that represents a number of cycles the data path must have for setup check.

Example:

Code Block

language	py

project = createProject()
project.load('routed.nym')
project.addMulticyclePath('getRegister('UUT1|Gen_seq[3].seq_i|temp_reg[1]')', 'getRegister('UUT2|dout_reg[61]')', 2)
project.addMulticyclePath('getRegisters("i_cpt_0\|s_cpt_out_reg[`[1-3]`]")', 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', 2)

createClock( )

This method is used to create a clock constraint at a timing point. This constraint is used by timing driven algorithms and static timing analysis. Depending on the unit defined in the project, timings are in ns or ps.

Signatures:

createClock(target, name, period)

createClock(target, name, period, rising)

createClock(target, name, period, rising, falling)

Arguments:

...

Name

...

Type

...

Description

...

target

...

string

...

the query which specifies how to get a clock related point. A valid query can be: getPort(port_name), getRegisterClock(register_name) or getRegister(register_name), getClockNet(clock_net_name).

...

name

...

string

...

user clock name of the created clock.

...

period

...

float

...

the period value.

...

rising

...

float

...

specific rising edge for clock waveform. Range [0, period[ (the default value is 0)

...

falling

...

float

...

specific falling edge for clock waveform. Range ]rising, rising + period] (default value is period/2)

Note
The name of the clock net is case sensitive

Example:

...

In the example above, to define a 100MHz clock for net “Clk”, the following three commands are equivalent :

Code Block

language	py

project = createProject()
project.load('routed.nym')
project.createClock('getRegisterClock(reg1)', 'clk', 10)
or 
project.createClock('getPort(Clk)', 'clk', 10)
or 
project.createClock('getClockNet(Clk)', 'clk', 10, 0, 5)

createClock( target = ‘target', name = ‘name’, period = ]0, ], rising = [0,period[, falling = ]rising, rising+period] )

...

, 10, 0, 5)

createClock( target = ‘target', name = ‘name’, period = ]0, ], rising = [0,period[, falling = ]rising, rising+period] )

This method is used to create a clock constraint at a timing point. This constraint is used by timing driven algorithms and static timing analysis. Depending on the unit defined in the project, timings are in ns or ps.

Arguments:

Name	Type	Description
target	string	Mandatory. The argument that specifies how to get a clock related point. A valid argument can be: `getPort(port_name)`, `getRegisterClock(register_name)` or `getRegister(register_name)`, `getClockNet(clock_net_name)`.
name	string	Optional. User clock name of the created clock, default name is target_str
period	float	Mandatory. Period for the clock waveform. Must be positive, default value is period/2
rising	float	Mandatory if falling is defined. Otherwise, it is optional. Rising edge for the clock waveform. The range is defined as [0, period[ The default value is 0.
falling	float	Optional. Falling edge for the clock waveform. The range is defined as ]rising, rising + period]. The default value is period/2.

Examples:

...

In the example above, to define a 100MHz clock for net “Clk”, the following three commands are equivalent :

Code Block

language	py

project = createProject()
project.load('routed.nym')
project.createClock(target = 'getRegisterClock(reg1)', name = 'Clk', period = 10)
or 
project.createClock(target = 'getPort(Clk)', name = 'Clk', period = 10)
or 
project.createClock(target = 'getClockNet(Clk)', name = 'Clk', period = 10, rising = 0, falling = 5)

createGeneratedClock(source, target, name, relationship)

/ ! \ DEPRECATED / ! \ Please use createGeneratedClock(source = ‘source', target = ‘target’, name = 'name', key = value) instead. This method is described immediately below.

This method is used to create an internal generated clock constraint at a timing point. This constraint is used by timing driven algorithms and static timing analysis.

Arguments:

Name	Type	Description
source	string	Specifies how to get a source clock related point. A valid argument can be: `getClock(clock_name)`, `getPort(port_name)`, `getRegisterClock(register_name)`, `getRegister(register_name)`, `getClockNet(clock_net_name)`, `getWFGOutput(wfg_name)`
target	string	Specifies how to get a clock related point. A valid argument can be: `getRegisterClock(register_name)`, `getRegister(register_name)`, `getClockNet(clock_net_name)`
name	string	User clock name of the generated clock
relationship	dictionary	The relationship for computing clock wave of the generated clock from the master clock. A valid parameter can be: MultiplyBy : unsigned DivideBy : unsigned DutyCycle : unsigned (1 to 99) Phase : unsigned (0 to 359) Offset : integer (delay in ns) Edges : list [unsigned, unsigned, unsigned] (in non-decreasing order) EdgeShift : list [integer, integer, integer] (delay in ns)

Note
Frequency-based and edge-based relationships are mutually exclusive.

Examples:

...

In the example above, the master clock "Clk" was created as 100MHz and the generated clock "clk1" is divided by 2 from the master clock. However note that the "clk_reg" is driven by the falling edge of master clock, the relation between the master clock and the generated clock is shown in the diagram below:

...

Code Block

language	py

project = createProject()
project.load('routed.nym')
project.createClock(getPort('Clk'), 'Clk', 10)
project.createGeneratedClock('getRegisterClock(clk_reg)', 'getRegisterClock(reg2)', 'clk1', {'DivideBy': 2})
or
project.createGeneratedClock('getClock(Clk)', 'getRegisterClock(reg2)', 'clk1', {'Edges': [2, 4, 6]})

Note

The following script is incorrect in this case:

########### INCORRECT SCRIPT ##########

project.createGeneratedClock(getClock('Clk'),getRegisterClock('reg2'), 'clk1', {'DivideBy': 2})

The diagram of the above command would be:

...

createGeneratedClock(source = ‘source', target = ‘target’, name = 'name', key = value)

This method is used to create an internal generated clock constraint at a timing point. This constraint is used by timing driven algorithms and static timing analysis.

Arguments:

Name	Type	Description
source	string	Mandatory. Specifies how to get source clock related point. A valid argument can be: `getClock(clock_name)`, `getPort(port_name)`, `getRegisterClock(register_name)`, `getRegister(register_name)`, `getClockNet(clock_net_name)`, `getWFGOutput(wfg_name)`
target	string	Mandatory. Specifies how to get a clock related point. A valid argument can be: `getRegisterClock(register_name)`, `getRegister(register_name)`, `getClockNet(clock_net_name)`
name	string	User clock name of the generated clock

Parameters for computing clock wave of generated clock from master clock are described below:

Key	Type	Description and value
multiplyBy	int	Period multiplication factor. The value must be greater or equal to 1. Default value is 1
divideBy	int	Period division factor. The value must be greater or equal to 1. Default value is 1
dutyCycle	int	Duty cycle of clock period. The range must be from 1 to 99. Default value is 50.0
phase	unsigned	The range must be from 0 to 359
invert	boolean	Invert the clock signal (~ phase = 180)
offset	float	Offset for rising edge
edges	int list	Specifies the edges of the master clock to use in defining transitions on the generated clock. List in non-decreasing order. Mutually exclusive with 'multiplyBy' or 'divideBy'
edgeShift	float list	Shifts the edges of the generated clock by the specified values relative to the master clock. Mutually exclusive with 'multiplyBy' or 'divideBy'

Note
Frequency-based and edge-based relationships are mutually exclusive.

Examples:

...

In the example above, the master clock "Clk" was created as 100MHz and the generated clock "clk1" is divided by 2 from the master clock. However note that the "clk_reg" is driven by the falling edge of master clock, the relation between the master clock and the generated clock is shown in the diagram below:

...

Code Block

language	py

project = createProject()
project.load('routed.nym')
project.createClock(source = 'getPort(Clk)', name = 'Clk', period = 10)
project.createGeneratedClock(source = 'getRegisterClock(clk_reg)', target = 'getRegisterClock(reg2)', name = 'clk1', divideBy = 2)
or 
project.createGeneratedClock(source = 'getClock(Clk)', target = getRegisterClock(reg2)', name = 'clk1', edges = [2, 4, 6])

Note

The following script is incorrect in this case:

########### INCORRECT SCRIPT ##########

project.createGeneratedClock(source = 'getClock(Clk)', target ='getRegisterClock(reg2)', name ='clk1', divideBy = 2)

The diagram of the above command would be:

...

setClockGroup(group1_list, group2_list, option)

/ ! \ DEPRECATED / ! \ Please use setClockGroup(group1 = ‘group1’, group2 = ‘group2', option = 'option’) instead. This method is described immediately below.

This method is used to specify which clocks are not related. This constraint is used by timing driven algorithms and static timing analysis.

A clock cannot be in a different group from itself.

Arguments:

Name	Type	Description
group1_list	string	Specifies how to get a group of clocks. A valid clock should be a clock created by command createClock. A valid argument can be: `getClock(clock_name)` and `getClocks(name_expression)`.
group2_list	string	Same as the argument "group1_list"
option	string	A valid option can be 'asynchronous' or 'exclusive': Asynchronous clocks are those that are completely unrelated. Exclusive clocks are not actively used in the design at the same time.

Examples:

Code Block

language	py

project = createProject()
project.load('routed.nym')
project.createClock('getRegister(UUT1\|Gen_seq[2].seq_i\|temp_reg[13])', 'clk1', 2.7)
project.createClock('getClockNet(CLOCK[2])', 'clk2', 5, 0, 2)    
project.setClockGroup('getClock(clk1)', 'getClock(clk2)', 'exclusive')

setClockGroup(group1 = ‘group1', group2= ‘group2’, option = 'option’)

This method is used to specify which clocks are not related. This constraint is used by timing driven algorithms and static timing analysis.

A clock cannot be in a different group from itself.

Arguments:

Name	Type	Description
group1	string	Mandatory. Specifies how to get a group of clocks. A valid clock should be a clock created by command createClock. A valid argument can be: `getClock(clock_name)` and `getClocks(name_expression)`.
group2	string	Mandatory. Same as the argument "group1"
option	string	Mandatory. A valid option can be 'asynchronous' or 'exclusive': Asynchronous clocks are those that are completely unrelated. Exclusive clocks are not actively used in the design at the same time

Examples:

Code Block

language	py

project = createProject()
project.load('routed.nym')
project.createClock(name ='clk1', period = 2.7, target= 'getRegister(UUT1\|Gen_seq[2].seq_i\|temp_reg[13])')
project.createClock(name = 'clk2', period = 5, rising = 0, falling = 2, target= 'getClockNet(CLOCK[2])')    
project.setClockGroup(group1 = 'getClock(clk1)', group2 = 'getClock(clk2)', option = 'exclusive')

addMaxDelayPath(from_list, to_list, delay)

/ ! \ DEPRECATED / ! \ Please use setMaxDelay instead, with the same key arguments. This method is described immediately below.

This method is used to specify the maximum delay path for the timing paths. It is used by timing driven algorithms and static timing analysis.

Arguments:

Name	Type	Description
from_list	string	Specifies how to get a timing path starting points. A valid timing starting point can be either an input port or a register. A valid argument can be: `getPort(port_name)`, `getPorts(name_expression)`, `getRegister(register_name)`, `getRegisters(name_expression)`, `getRegistersByClock(clock_name)`
to_list	string	Specifies how to get a timing path ending points. A valid timing ending point can be either an output port or a register. A valid argument can be: `getPort(port_name)`, `getPorts(name_expression)`, `getRegister(register_name)`, `getRegisters(name_expression)`, `getRegistersByClock(clock_name)`
delay	float	The required maximum delay value in ns for specified paths.

Examples:

Code Block

language	py

project = createProject()
project.load('routed.nym')
project.addMaxDelayPath('getRegister('UUT1\|Gen_seq[3].seq_i\|temp_reg[1]')', 'getRegister('UUT2\|dout_reg[61]')', 3.9)
project.addMaxDelayPath('getPort(cpt_in[0])', 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', 8.0)         
project.addMaxDelayPath('getRegister(i_cpt_0\|s_cpt_out_reg[0])','getRegister(i_cpt_1\|s_cpt_out_reg[1])', 4.0) 
project.addMaxDelayPath('getPorts("cpt_in[`[1-3]`]")','getRegister(i_cpt_1\|s_cpt_out_reg[1])', 8.0)  
project.addMaxDelayPath('getRegisters("i_cpt_0\|s_cpt_out_reg[`[1-3]`]")', 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', 8.0)

setMaxDelay(source = ‘source', target = ‘target’, delay = 'delay’)

This method is used to specify the maximum delay path for the timing paths. It is used by timing driven algorithms and static timing analysis.

Arguments:

Name	Type	Description
source	string	Specifies how to get a timing path starting points. A valid timing starting point can be either an input port or a register. A valid argument can be: `getPort(port_name)`, `getPorts(name_expression)`, `getRegister(register_name)`, `getRegisters(name_expression)`, `getRegistersByClock(clock_name)`
target	string	Specifies how to get a timing path ending points. A valid timing ending point can be either an output port or a register. A valid argument can be: `getPort(port_name)`, `getPorts(name_expression)`, `getRegister(register_name)`, `getRegisters(name_expression)`, `getRegistersByClock(clock_name)`
delay	float	The required maximum delay value in ns for specified paths.

Examples:

Code Block

language	py

project = createProject()
project.load('routed.nym')
project.setMaxDelay(source = 'getRegister('UUT1\|Gen_seq[3].seq_i\|temp_reg[1]')', target = 'getRegister('UUT2\|dout_reg[61]')', delay = 3.9)
project.setMaxDelay(source = 'getPort(cpt_in[0])', target = 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', delay = 8.0)         
project.setMaxDelay(source = 'getRegister(i_cpt_0\|s_cpt_out_reg[0])', target = 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', delay = 4.0) 
project.setMaxDelay(source = 'getPorts("cpt_in[`[1-3]`]")', target = 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', delay = 8.0)  
project.setMaxDelay(source = 'getRegisters("i_cpt_0\|s_cpt_out_reg[`[1-3]`]")', target = 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', delay = 8.0)

addMinDelayPath(from_list, to_list, delay)

/ ! \ DEPRECATED / ! \ Please use setMinDelay instead, with the same key arguments. This method is described immediately below.

This method is used to specify the minimum delay path for the timing paths. It is used by timing driven algorithms and static timing analysis.

Arguments:

Name	Type	Description
from_list	string	Specifies how to get a timing path starting points. A valid timing starting point can be either an input port or a register. A valid argument can be: `getPort(port_name)`, `getPorts(name_expression)`, `getRegister(register_name)`, `getRegisters(name_expression)`, `getRegistersByClock(clock_name)`
to_list	string	Specifies how to get a timing path ending points. A valid timing ending point can be either an output port or a register. A valid argument can be: `getPort(port_name)`, `getPorts(name_expression)`, `getRegister(register_name)`, `getRegisters(name_expression)`, `getRegistersByClock(clock_name)`
delay	float	The required minimum delay value in ns for specified paths.

Examples:

Code Block

language	py

project = createProject()
project.load('routed.nym')
project.addMinDelayPath('getRegister('UUT1\|Gen_seq[3].seq_i\|temp_reg[23]')', 'getRegister('UUT1\|Gen_seq[3].seq_i\|temp_reg[22]')', 1.2)
project.addMinDelayPath('getPort(cpt_in[0])', 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', 8.0)
project.addMinDelayPath('getRegister(i_cpt_0\|s_cpt_out_reg[0])', 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', 8.0)
project.addMinDelayPath('getPorts("cpt_in[`[1-3]`]")', 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', 8.0)
project.addMinDelayPath('getRegisters("i_cpt_0\|s_cpt_out_reg[`[1-3]`]")', 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', 8.0)

setMinDelay(source = ‘source', target = ‘target’, delay = 'delay’)

This method is used to specify the minimum delay path for the timing paths. It is used by timing driven algorithms and static timing analysis.

Arguments:

Name	Type	Description
source	string	Specifies how to get a timing path starting points. A valid timing starting point can be either an input port or a register. A valid argument can be: `getPort(port_name)`, `getPorts(name_expression)`, `getRegister(register_name)`, `getRegisters(name_expression)`, `getRegistersByClock(clock_name)`
target	string	Specifies how to get a timing path ending points. A valid timing ending point can be either an output port or a register. A valid argument can be: `getPort(port_name)`, `getPorts(name_expression)`, `getRegister(register_name)`, `getRegisters(name_expression)`, `getRegistersByClock(clock_name)`
delay	float	The required minimum delay value in ns for specified paths.

Examples:

Code Block

language	py

project = createProject()
project.load('routed.nym')
project.setMinDelay(source = 'getRegister('UUT1\|Gen_seq[3].seq_i\|temp_reg[23]')', target = 'getRegister('UUT1\|Gen_seq[3].seq_i\|temp_reg[22]')', delay = 1.2)
project.setMinDelay(source = 'getPort(cpt_in[0])', target = 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', delay = 8.0)
project.setMinDelay(source = 'getRegister(i_cpt_0\|s_cpt_out_reg[0])', target = 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', delay = 8.0)
project.setMinDelay(source = 'getPorts("cpt_in[`[1-3]`]")', target = 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', delay = 8.0)
project.setMinDelay(source = 'getRegisters("i_cpt_0\|s_cpt_out_reg[`[1-3]`]")', target = 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', delay = 8.0)

addMulticyclePath(from_list, to_list, cycle_count)

/ ! \ DEPRECATED / ! \ Please use setMulticyclePath instead, with the same key arguments. This method is described immediately below.

This method is used to specify the multicycle path for the timing paths. It is used by timing driven algorithms and static timing analysis.

Arguments:

Name	Type	Description
from_list	string	Specifies how to get a timing path starting points. A valid timing starting point is a register. A valid argument can be: `getRegister(register_name)`, `getRegisters(name_expression)`, `getRegistersByClock(clock_name)`.
to_list	string	Specifies how to get a timing path ending points. A valid timing ending point is a register. A valid argument can be: `getRegister(register_name)`, `getRegisters(name_expression)`, `getRegistersByClock(clock_name)`.
cycle_count	unsigned	An unsigned value that represents a number of cycles the data path must have for setup check.

Examples:

Code Block

language	py

project = createProject()
project.load('routed.nym')
project.addMulticyclePath('getRegister('UUT1\|Gen_seq[3].seq_i\|temp_reg[1]')', 'getRegister('UUT2\|dout_reg[61]')', 2)
project.addMulticyclePath('getRegisters("i_cpt_0\|s_cpt_out_reg[`[1-3]`]")', 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', 2)

Note
This method is only available for path(s) whose source and target registers are clocked by the same clock!

setMulticyclePath(source = 'source', target = 'target', pathMultiplier = 'pathMultiplier')

This method is used to specify the multicycle path for the timing paths. It is used by timing driven algorithms and static timing analysis.

Arguments:

Name	Type	Description
source	string	Mandatory. Specifies how to get a timing path starting points. A valid timing starting point is a register. A valid argument can be: `getRegister(register_name)`, `getRegisters(name_expression)`, `getRegistersByClock(clock_name)`.
target	string	Mandatory. Specifies how to get a timing path ending points. A valid timing ending point is a register. A valid argument can be: `getRegister(register_name)`, `getRegisters(name_expression)`, `getRegistersByClock(clock_name)`.
pathMultiplier	integer	Mandatory. A value that represents a number of cycles. Must be greater than 1.

Examples:

Code Block

language	py

project = createProject()
project.load('routed.nym')
project.setMulticyclePath(source = 'getRegister('UUT1\|Gen_seq[3].seq_i\|temp_reg[1]')', target = 'getRegister('UUT2\|dout_reg[61]')', pathMultiplier = 2)
project.setMulticyclePath(source = 'getRegisters("i_cpt_0\|s_cpt_out_reg[`[1-3]`]")', target = 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', pathMultiplier = 2)

Note
This method is only available for path(s) whose source and target registers are clocked by the same clock!

addFalsePath(from_list, to_list)

/ ! \ DEPRECATED / ! \ Please use setFalsePath instead, with the same key arguments. This method is described immediately below.

This method is used to specify the false path for the timing paths. This constraint is used by timing driven algorithms and static timing analysis.

Arguments:

Name	Type	Description
from_list	string	Specifies how to get a timing path starting points. A valid timing starting point is an input port or a register. A valid argument can be: `getPort(port_name)`, `getPorts(name_expression)`, `getRegister(register_name)`, `getRegisters(name_expression)`, `getRegistersByClock(clock_name)`
to_list	string	Specifies how to get a timing path ending points. A valid timing ending point is an output port or a register. A valid argument can be: `getPort(port_name)`, `getPorts(name_expression)`, `getRegister(register_name)`, `getRegisters(name_expression)`, `getRegistersByClock(clock_name)`

Examples:

Code Block

breakoutMode	wide
language	py

project = createProject()
project.load('routed.nym')
project.addFalsePath('getRegister('UUT1\|Gen_seq[3].seq_i|temp_reg[1]')','getRegister('UUT2\|dout_reg[61]')')
project.addFalsePath('getRegistersByClock(clk1)','getRegistersByClock(clk2)')
project.addFalsePath('getRegister(cpt_in_p_reg[0])','')
project.addFalsePath('getPort(cpt_in[0])','getRegisters("cpt_in_p_reg[`[0-3]`]")')
project.addFalsePath('getPorts("cpt_in[`[0-3]`]")', 'getRegistersByClock(clk2)')
project.addFalsePath('getRegistersByClock(clk1)', 'getWFGOutput(i_WFG_0)')

In order to match with all registers, source or target SHOULD be set to empty.

setFalsePath(source = ‘source', target = 'target’)

This method is used to specify the false path for the timing paths. This constraint is used by timing driven algorithms and static timing analysis.

Name	Type	Description
source	string	Mandatory. Specifies how to get a timing path starting points. A valid timing starting point is an input port or a register. A valid argument can be: `getPort(port_name)`, `getPorts(name_expression)`, `getRegister(register_name)`, `getRegisters(name_expression)`, `getRegistersByClock(clock_name)`
target	string	Mandatory. Specifies how to get a timing path ending points. A valid timing ending point is an output port or a register. A valid argument can be: `getPort(port_name)`, `getPorts(name_expression)`, `getRegister(register_name)`, `getRegisters(name_expression)`, `getRegistersByClock(clock_name)`

Examples:

Code Block

breakoutMode	wide
language	py

project = createProject()
project.load('routed.nym')
project.setFalsePath(source = 'getRegister('UUT1\|Gen_seq[3].seq_i\|temp_reg[1]')', target = 'getRegister('UUT2\|dout_reg[61]')')
project.setFalsePath(source = 'getRegistersByClock(clk1)', target = 'getRegistersByClock(clk2)')
project.setFalsePath(source = 'getRegister(cpt_in_p_reg[0])')
project.setFalsePath(source = 'getPort(cpt_in[0])', target = 'getRegisters("cpt_in_p_reg[`[0-3]`]")')
project.setFalsePath(source = 'getPorts("cpt_in[`[0-3]`]")', target = 'getRegistersByClock(clk2)')
project.setFalsePath(source = 'getRegistersByClock(clk1)', target = 'getWFGOutput(i_WFG_0)')

In order to match with all registers, source or target SHOULD be set to empty.

setInputDelay(clock, clock_mode, minimum_delay, maximum_delay, port_list)

/ ! \ DEPRECATED / ! \ Please use setInputDelay(clock = ‘clock', clockMode = ‘clockMode’, min = ‘min’, max = ‘max’, ports = 'ports’) instead. This method is described immediately below.

This method specifies the data arrival times at the specified input ports relative to the clock. The clock must refer to a clock name in the design. This constraint is used by timing driven algorithms and static timing analysis. Depending on the unit define in the project, timings are in ns or ps.

Arguments:

Name	Type	Description
clock	string	Specifies how to get a clock specified. A valid clock should be a clock created by command createClock. The valid argument is `getClock(clock_name)`.
clock_mode	string	Specifies that input delay is relative to the falling or rising edge of the clock. It must be "rise"' or "fall".
minimum_delay	float	Applies value as minimum data arrival time.
maximum_delay	float	Applies value as maximum data arrival time.
port_list	string	Specifies how to get a list of input pads. A valid argument can be: `getPort(port_name)`, `getPorts(name_expression)`.

Examples:

Code Block
project = createProject() project.load('routed.nym') project.createClock(getClockNet('CLK'),'CLK',8) project.setInputDelay(getClock('CLK'),'rise', 1, 1.5, getPort('RST'))

setInputDelay(clock = ‘clock', clockMode = ‘clockMode’, min = ‘min’, max = ‘max’, ports = 'ports’)

This method specifies the data arrival times at the specified input ports relative to the clock. The clock must refer to a clock name in the design. This constraint is used by timing driven algorithms and static timing analysis. Depending on the unit define in the project, timings are in ns or ps.

Arguments:

Name	Type	Description
clock	string	Mandatory. Specifies how to get a clock specified. A valid clock should be a clock created by command createClock. The valid argument is `getClock(clock_name)`.
clockMode	string	Optional. Specifies that input delay is relative to the falling or rising edge of the clock. It must be "rise"' or "fall". Default value is rise.
min	float	Optional. Applies value as minimum data delay, it refers to the longest path. The default value is max if the max is defined, otherwise it is set to 0.
max	float	Optional. Applies value as maximum data delay, it refers to the shortest path. The default value is min if the min is defined, otherwise it is set to 0.
ports	string	Mandatory. Specifies how to get a list of input pads. A valid argument can be: `getPort(port_name)`, `getPorts(name_expression)`.

Examples:

Code Block

project = createProject()
project.load('routed.nym')
project.createClock(target = 'getClockNet(CLK)', name = 'clock',period = 8)
project.setInputDelay(clock = 'getClock(clock)', clockMode = 'rise', min = 1, max = 1.5, ports = 'getPort(RST)')

setOutputDelay(clock, clock_mode, minimum_delay, maximum_delay, port_list)

/ ! \ DEPRECATED / ! \ Please use setOutputDelay(clock = ‘clock', clockMode = ‘clockMode’, min = ‘min’, max = ‘max’, ports = 'ports’) instead. This method is described immediately below.

This method specifies the data arrival times at the specified output ports relative to the clock. The clock must refer to a clock name in the design. This constraint is used by timing driven algorithms and static timing analysis.

Arguments:

Name	Type	Description
clock	string	Specifies how to get a clock specified. A valid clock should be a clock created by command createClock. A valid argument can be: `getClock(clock_name)`.
clock_mode	string	Specifies that output delay is relative to the falling or rising edge of the clock. It must be "rise"' or "fall".
minimum_delay	integer	Applies value as minimum data arrival time.
maximum_delay	integer	Applies value as maximum data arrival time.
port_list	string	Specifies how to get a list of output pads. A valid argument can be: `getPort(port_name)`, `getPorts(name_expression)`.

Examples:

Code Block

breakoutMode	wide

project = createProject()
project.load('routed.nym')
project.createClock(getClockNet('CLK'),'CLK',8)
project.setOutputDelay(getClock('CLK'),'rise', 1.0, 1.5, getPorts('dataout[`[0−5]`]'))

setOutputDelay(clock = ‘clock', clockMode = ‘clockMode’, min = ‘min’, max = ‘max’, ports = 'ports’)

This command specifies the data required times at the specified output ports relative to the clock. The clock must refer to a clock defined in the design. This constraint is used by timing driven algorithms and static timing analysis. Depending on the unit defined in the project, timings could be in ns or ps.

Arguments:

Name	Type	Description
clock	string	Mandatory. Specifies how to get a clock specified. A valid clock should be a clock created by command createClock. A valid argument can be: `getClock(clock_name)`.
clockMode	string	Optional. Specifies that output delay is relative to the falling or rising edge of the clock. It must be "rise"' or "fall". The default value is “rise”.
min	float	Optional. Applies value as minimum data delay, it refers to the longest path. The default value is max if the max is defined, otherwise it is set to 0.
max	float	Optional. Applies value as maximum data delay, it refers to the shortest path. The default value is min if the min is defined, otherwise it is set to 0.
ports	string	Mandatory. Specifies how to get a list of input pads. A valid argument can be:`getPort(port_name)`, `getPorts(name_expression)`.

Examples:

Code Block

language	py

project = createProject()
project.load('routed.nym')
project.createClock(target = 'getClockNet('CLK')', name = 'CLK', period = 8)
project.setOutputDelay(clock = 'getClock(clock)', clockMode = 'rise', min = 1, max = 1.5, ports = 'getPort(RST)')

developCKGs()

This method automatically creates a generated clock constraint on each output of the PLLs and WFGs in current project. This constraint is used by timing driven algorithms and static timing analysis.

This method takes no argument.

developCKGs() allows the user to create generated clocks for CKGs output pins. For example, before activating a generated clock which is based on a clock driven by a WFG, user needs to launch this method for generating the base clock. Without this method, nxmap automatically derives a clock on each output of the CKGs after activating all of the given timing constraints.

Examples:

Code Block

breakoutMode	wide
language	py

project = createProject()
project.load('routed.nym')
project.createClock(target = 'getClockNet(CLK)', name ='clk', period = 8, rising = 0, falling = 4)
project.developCKGs()
project.createGeneratedClock(source = 'getWFGOutput(wfg_clk[1])', target= 'getRegister(data_reg[0])', name='clk1_div2', divideBy = 2)

setAnalysisConditions(conditions)

/ ! \ DEPRECATED / ! \ Please use setAnalysisConditions(conditions = 'conditions') instead.

This method is used to specify the chip conditions for static timing analysis. This constraint is used by timing driven algorithms and static timing analysis.

Arguments:

Name	Type	Description
conditions	string	Specifies the conditions for static timing analysis.

Example:

Code Block
project.setAnalysisConditions(WorstCase)

setAnalysisConditions(conditions = 'conditions')

This method is used to specify the chip conditions for the static timing analysis. This constraint is used by timing driven algorithms and static timing analysis.

Arguments:

Name	Type	Description
conditions	string	Specifies the conditions for static timing analysis.

Example:

Code Block

language	py

project.setAnalysisConditions(conditions = 'worstcase')

setCaseAnalysis(value, net_list)

/ ! \ DEPRECATED / ! \ Please use setCaseAnalysis(value = ‘value', netList = 'netList’) instead. This method is described immediately below.

This method is used to specify a constant logic value to the given tests. This constraint is used by timing driven algorithms and static timing analysis.

Arguments:

Name	Type	Description
value	unsigned	The valid constant. Values can be 0 or 1
net_list	string	Specifies how to get one or several nets. A valid argument can be `getNet(net_name)`, `getNets(net_name_expression)`, `getPort(port_name)`, `getPorts(port_name_expression)`

Setting a case value on a net results in disabling timing analysis through the emitter pin and all the receiver pins of the net. It means that timing paths through those pins are not considered. The constant value is propagated through the network as long as a controlling value for the traversed logic is at the constant value.

Example:

...

In the example above, two clocks (clk[0] and clk[1]) are connected to the inputs of the multiplexer. However, only clk[1] is propagated through the output after setting the constant value on the selection signal (sel).

Code Block

language	py

 project = createProject()
 project.load('routed.nym')
 project.setCaseAnalysis(1, 'getNet(sel)')

setCaseAnalysis(value = ‘value', netList = 'netList’)

This method is used to specify a constant logic value to the given tests. This constraint is used by timing driven algorithms and static timing analysis. Depending on the unit defined in the project, timings are in ns or ps.

Arguments:

Name	Type	Description

target

value	unsigned	The valid constant. Values can be 0 or 1
netList	string

Mandatory. The query which specifies

Specifies how to get

a clock related point

one or several nets. A valid

query

argument can be:

getPort

getNet(

port

net_name),

getRegisterClock

getNets(

register

net_name_expression)

or getRegister

, getPort(

register

port_name),

getClockNet(clock_net_name).

name

string

Optional. User clock name of the created clock, default name is target_str

period

float

Mandatory. Period for the clock waveform. Must be positive, default value is period/2

rising

float

Mandatory if falling is defined. Otherwise, it is optional. Rising edge for the clock waveform. The range is defined as [0, period[ The default value is 0.

falling

float

Optional. Falling edge for the clock waveform. The range is defined as ]rising, rising + period]. The default value is period/2.

Example:

...

In the example above, to define a 100MHz clock for net “Clk”, the following three commands are equivalent :

Code Block

language	py

project = createProject()
project.load('routed.nym')
project.createClock(target = 'getRegisterClock(reg1)', name = 'Clk', period = 10)
or 
project.createClock(target = 'getPort(Clk)', name = 'Clk', period = 10)
or 
project.createClock(target = 'getClockNet(Clk)', name = 'Clk', period = 10, rising = 0, falling = 5)

createGeneratedClock(source, target, name, relationship)

...

getPorts(port_name_expression)

Setting a case value on a net results in disabling timing analysis through the emitter pin and all the receiver pins of the net. It means that timing paths through those pins are not considered. The constant value is propagated through the network as long as a controlling value for the traversed logic is at the constant value.

Example:

...

In the example above, two clocks (clk[0] and clk[1]) are connected to the inputs of the multiplexer, but only clk[1] is propagated through the output after setting the constant value on the selection signal (sel).

Code Block

language	py

project = createProject()
project.load('routed.nym')
project.setCaseAnalysis(value = '1', netList = 'getNet(sel)')

addReportTimingPath(source = ‘source_reg', target = 'target_reg’)

This method gives the shortest and the longest delays of a path. This constraint is used by timing driven algorithms and static timing analysis.

Timing log files will only contain paths found between sources and targets from these queries.

Arguments:

Name	Type	Description
source_reg	string	Specifies the starting points of the timing paths to be analyzed. A valid argument can only be a register : `getRegister(register_name)`, `getRegisters(name_expression)`
target_reg	string	Specifies the ending points or destination objects of timing paths to be analyzed. A valid argument can be: `getRegister(register_name)`, `getRegisters(name_expression)`

Example:

This method should be launched after creating an Analyzer, as follow :

Code Block
Timing_analysis = p.createAnalyzer() Timing_analysis.addReportTimingPath(source = 'getRegister(i_cpt_0\|s_cpt_out_reg[1])', target ='getRegister(i_cpt_1\|s_cpt_out_reg[2])') Timing_analysis.launch()

removeDesignConstraint(id= ‘id')

This method is used to remove a design constraint from the current project.
Remove constraint can be clocks, generated clocks, derived clocks of PLLs and WFGs, input delays, output delays, clock groups, analysis case, false paths, multicycle paths, min delay paths, and max delays paths.

Arguments:

Name	Type	Description

source

id

string

unsigned

The

command which specifies how to get a source clock related point. A valid command can be: getClock(), getPort(port_name), getRegisterClock(register_name), getRegister(register_name), getClockNet(clock_net_name), getWFGOutput(wfg_name)

target

string

The command which specifies how to get a clock related point. A valid command can be: getRegisterClock(register_name), getRegister(register_name)), getClockNet(clock_net_name)

name

string

User clock name of the generated clock

relationship

dictionary

The relationship for computing clock wave of the generated clock from the master clock. All valid parameter can be:

MultiplyBy : unsigned

DivideBy : unsigned

DutyCycle : unsigned (1 to 99)

Phase : unsigned (0 to 359)

Offset : integer (delay in ns)

Edges : list [unsigned, unsigned, unsigned] (in non-decreasing order)

EdgeShift : list [integer, integer, integer] (delay in ns)

Note
Frequency-based and edge-based relationships are mutually exclusive.

Example:

...

In the example above, the master clock "Clk" was created as 100MHz and the generated clock "clk1" is divided by 2 from the master clock. But note that the "clk_reg" is driven by the falling edge of master clock, the relation between the master clock and the generated clock is shown in the diagram below:

...

Code Block

language	py

project = createProject()
project.load('routed.nym')
project.createClock(getPort('Clk'), 'Clk', 10)
project.createGeneratedClock('getRegisterClock(clk_reg)', 'getRegisterClock(reg2)', 'clk1', {'DivideBy': 2})
or
project.createGeneratedClock('getClock(Clk)', 'getRegisterClock(reg2)', 'clk1', {'Edges': [2, 4, 6]})

Note

The following script is incorrect in this case:

########### INCORRECT SCRIPT ##########

project.createGeneratedClock(getClock('Clk'),getRegisterClock('reg2'), 'clk1', {'DivideBy': 2})

The diagram of the above command would be:

...

id of the design constraint to remove

Example:

This method is used before launching a Static Timing Analysis or using TimingDriven:

Code Block

p.createClock(target=getClockNet('clk1'),name='clk1',period=20.000,rising=0,falling=10.000) #Clk1 is created with 50 MHz frequency
p.removeDesignConstraint(1)
p.createClock(target=getClockNet('clk1'),name='clk1',period=40.000,rising=0,falling=20.000) #Clk1 is now with 25 MHz frequency

resetTimingConstraints()

This method is used to reset all design constraints from the current project.
Reseted constraints can be clocks, generated clocks, derived clocks of PLLs and WFGs, input delays, output delays, clock groups, analysis case, false paths, multicycle paths, min delay paths, and max delays paths.

This method takes no argument.

Example:

This method is used before launching a Static Timing Analysis or using TimingDriven:

Code Block
p.createClock(target=getClockNet('clk1'),name='clk1',period=20.000,rising=0,falling=10.000) #Clk1 is created with 50 MHz frequency p.resetTimingConstraints()

addReportPath(source = ‘source_reg', target = 'target_reg’)

This method gives the shortest and the longest delays of a path. This constraint is used by timing driven algorithms and static timing analysis.

Timing log files will still contain all paths. In addition, A file is create with shortest and longest paths found between sources and targets from each query.

Arguments:

Name	Type	Description
source_reg	string	Specifies the starting points of the timing paths to be analyzed. A valid argument can only be a register : `getRegister(register_name)`, `getRegisters(name_expression)`
target_reg	string	Specifies the ending points or destination objects of timing paths to be analyzed. A valid argument can be: `getRegister(register_name)`, `getRegisters(name_expression)`

Example:

This method should be launched after creating an Analyzer, as follow :

Code Block
Timing_analysis = p.createAnalyzer() Timing_analysis.addReportPath(source = 'getRegister(i_cpt_0\|s_cpt_out_reg[1])', target ='getRegister(i_cpt_1\|s_cpt_out_reg[2])') Timing_analysis.launch()

Versions Compared

Old Version 5

New Version Current

Key

createClock( )

addMaxDelayPath(from_list, to_list, delay)

addMinDelayPath(from_list, to_list, delay)

addMulticyclePath(from_list, to_list, cycle_count)

createClock( )

createClock( target = ‘target', name = ‘name’, period = ]0, ], rising = [0,period[, falling = ]rising, rising+period] )

createClock( target = ‘target', name = ‘name’, period = ]0, ], rising = [0,period[, falling = ]rising, rising+period] )

createGeneratedClock(source, target, name, relationship)

createGeneratedClock(source = ‘source', target = ‘target’, name = 'name', key = value)

setClockGroup(group1_list, group2_list, option)

setClockGroup(group1 = ‘group1', group2= ‘group2’, option = 'option’)

addMaxDelayPath(from_list, to_list, delay)

setMaxDelay(source = ‘source', target = ‘target’, delay = 'delay’)

addMinDelayPath(from_list, to_list, delay)

setMinDelay(source = ‘source', target = ‘target’, delay = 'delay’)

addMulticyclePath(from_list, to_list, cycle_count)

setMulticyclePath(source = 'source', target = 'target', pathMultiplier = 'pathMultiplier')

addFalsePath(from_list, to_list)

setFalsePath(source = ‘source', target = 'target’)

setInputDelay(clock, clock_mode, minimum_delay, maximum_delay, port_list)

setInputDelay(clock = ‘clock', clockMode = ‘clockMode’, min = ‘min’, max = ‘max’, ports = 'ports’)

setOutputDelay(clock, clock_mode, minimum_delay, maximum_delay, port_list)

setOutputDelay(clock = ‘clock', clockMode = ‘clockMode’, min = ‘min’, max = ‘max’, ports = 'ports’)

developCKGs()

setAnalysisConditions(conditions)

setAnalysisConditions(conditions = 'conditions')

setCaseAnalysis(value, net_list)

setCaseAnalysis(value = ‘value', netList = 'netList’)

createGeneratedClock(source, target, name, relationship)

addReportTimingPath(source = ‘source_reg', target = 'target_reg’)

removeDesignConstraint(id= ‘id')

resetTimingConstraints()

addReportPath(source = ‘source_reg', target = 'target_reg’)