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In order to match with all registers, it is possible to specify empty string ('') for parameters from_list or to_listsource or target SHOULD be set to empty.

setFalsePath(source = ‘source', target = 'target’)

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In order to match with all registers, source or target can SHOULD be set to empty.

setInputDelay(clock, clock_mode, minimum_delay, maximum_delay, port_list)

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This method gives the shortest and the longest delays of a path. This constraint is used by timing driven algorithms and static timing analysis.

Timing log files will only contain paths found between sources and targets from these queries.

Arguments:

Name

Type

Description

source_reg

string

Specifies the starting points of the timing paths to be analyzed. A valid argument can only be a register : getRegister(register_name), getRegisters(name_expression)

target_reg

string

Specifies the ending points or destination objects of timing paths to be analyzed. A valid argument can be: getRegister(register_name), getRegisters(name_expression)

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This method is used before launching a Static Timing Analysis or using TimingDriven:

Code Block
p.createClock(target=getClockNet('clk1'),name='clk1',period=20.000,rising=0,falling=10.000) #Clk1 is created with 50 MHz frequency
p.removeDesignConstraint(1)
p.createClock(target=getClockNet('clk1'),name='clk1',period=40.000,rising=0,falling=20.000) #Clk1 is now with 25 MHz frequency

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This method is used before launching a Static Timing Analysis or using TimingDriven:

Code Block
p.createClock(target=getClockNet('clk1'),name='clk1',period=20.000,rising=0,falling=10.000) #Clk1 is created with 50 MHz frequency
p.resetTimingConstraints()

addReportPath(source = ‘source_reg', target = 'target_reg’)

This method gives the shortest and the longest delays of a path. This constraint is used by timing driven algorithms and static timing analysis.

Timing log files will still contain all paths. In addition, A file is create with shortest and longest paths found between sources and targets from each query.

Arguments:

Name

Type

Description

source_reg

string

Specifies the starting points of the timing paths to be analyzed. A valid argument can only be a register : getRegister(register_name), getRegisters(name_expression)

target_reg

string

Specifies the ending points or destination objects of timing paths to be analyzed. A valid argument can be: getRegister(register_name), getRegisters(name_expression)

Example:

This method should be launched after creating an Analyzer, as follow :

Code Block
Timing_analysis = p.createAnalyzer()
Timing_analysis.addReportPath(source = 'getRegister(i_cpt_0|s_cpt_out_reg[1])', target ='getRegister(i_cpt_1|s_cpt_out_reg[2])')
Timing_analysis.launch()