This document aims to list all the the nxpython methods available to apply timing constraints on a design.
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createClock( )
/ ! \ DEPRECATED / ! \
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Please use createClock(target = ‘target', name = ‘name’, period = ]0, ], rising = [0,period[, falling = ]rising, rising+period]) instead. This method is described immediately below.
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In order to match with all registers, it is possible to specify empty string ('') for parameters from_list or to_listsource or target SHOULD be set to empty.
setFalsePath(source = ‘source', target = 'target’)
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In order to match with all registers, source or target can SHOULD be set to empty.
setInputDelay(clock, clock_mode, minimum_delay, maximum_delay, port_list)
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This method gives the shortest and the longest delays of a path. This constraint is used by timing driven algorithms and static timing analysis.
Timing log files will only contain paths found between sources and targets from these queries.
Arguments:
Name | Type | Description |
|---|---|---|
source_reg | string | Specifies the starting points of the timing paths to be analyzed. A valid argument can only be a register : |
target_reg | string | Specifies the ending points or destination objects of timing paths to be analyzed. A valid argument can be: |
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Timing_analysis = p.createAnalyzer()
Timing_analysis.addReportTimingPath(source = 'getRegister(i_cpt_0|s_cpt_out_reg[1])', target ='getRegister(i_cpt_1|s_cpt_out_reg[2])')
Timing_analysis.launch() |
removeDesignConstraint(id= ‘id')
This method is used to remove a design constraint from the current project.
Remove constraint can be clocks, generated clocks, derived clocks of PLLs and WFGs, input delays, output delays, clock groups, analysis case, false paths, multicycle paths, min delay paths, and max delays paths.
Arguments:
Name | Type | Description |
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id | unsigned | The id of the design constraint to remove |
Example:
This method is used before launching a Static Timing Analysis or using TimingDriven:
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p.createClock(target=getClockNet('clk1'),name='clk1',period=20.000,rising=0,falling=10.000) #Clk1 is created with 50 MHz frequency
p.removeDesignConstraint(1)
p.createClock(target=getClockNet('clk1'),name='clk1',period=40.000,rising=0,falling=20.000) #Clk1 is now with 25 MHz frequency |
resetTimingConstraints()
This method is used to reset all design constraints from the current project.
Reseted constraints can be clocks, generated clocks, derived clocks of PLLs and WFGs, input delays, output delays, clock groups, analysis case, false paths, multicycle paths, min delay paths, and max delays paths.
This method takes no argument.
Example:
This method is used before launching a Static Timing Analysis or using TimingDriven:
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p.createClock(target=getClockNet('clk1'),name='clk1',period=20.000,rising=0,falling=10.000) #Clk1 is created with 50 MHz frequency
p.resetTimingConstraints() |
addReportPath(source = ‘source_reg', target = 'target_reg’)
This method gives the shortest and the longest delays of a path. This constraint is used by timing driven algorithms and static timing analysis.
Timing log files will still contain all paths. In addition, A file is create with shortest and longest paths found between sources and targets from each query.
Arguments:
Name | Type | Description |
|---|---|---|
source_reg | string | Specifies the starting points of the timing paths to be analyzed. A valid argument can only be a register : |
target_reg | string | Specifies the ending points or destination objects of timing paths to be analyzed. A valid argument can be: |
Example:
This method should be launched after creating an Analyzer, as follow :
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Timing_analysis = p.createAnalyzer()
Timing_analysis.addReportPath(source = 'getRegister(i_cpt_0|s_cpt_out_reg[1])', target ='getRegister(i_cpt_1|s_cpt_out_reg[2])')
Timing_analysis.launch() |
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