This document aims to list all the the nxpython methods available to apply timing constraints on a design.
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createClock( )
/ ! \ DEPRECATED / ! \
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Please use createClock(target = ‘target', name = ‘name’, period = ]0, ], rising = [0,period[, falling = ]rising, rising+period]) instead. This method is described immediately below.
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project = createProject()
project.load('routed.nym')
project.createClock('getRegisterClock(reg1)', 'clk', 10)
or
project.createClock('getPort(Clk)', 'clk', 10)
or
project.createClock('getClockNet(Clk)', 'clk', 10, 0, 5) |
createClock( target = ‘target', name = ‘name’, period = ]0, ], rising = [0,period[, falling = ]rising, rising+period] )
This method is used to create a clock constraint at a timing point. This constraint is used by timing driven algorithms and static timing analysis. Depending on the unit defined in the project, timings are in ns or ps.
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project = createProject()
project.load('routed.nym')
project.createClock(target = 'getRegisterClock(reg1)', name = 'Clk', period = 10)
or
project.createClock(target = 'getPort(Clk)', name = 'Clk', period = 10)
or
project.createClock(target = 'getClockNet(Clk)', name = 'Clk', period = 10, rising = 0, falling = 5) |
createGeneratedClock(source, target, name, relationship)
/ ! \ DEPRECATED / ! \ Please use createGeneratedClock(source = ‘source', target = ‘target’, name = 'name', key = value) instead. This method is described immediately below.
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The diagram of the above command would be:
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createGeneratedClock(source = ‘source', target = ‘target’, name = 'name', key = value)
This method is used to create an internal generated clock constraint at a timing point. This constraint is used by timing driven algorithms and static timing analysis.
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The diagram of the above command would be:
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setClockGroup(group1_list, group2_list, option)
/ ! \ DEPRECATED / ! \ Please use setClockGroup(group1 = ‘group1’, group2 = ‘group2', option = 'option’) instead. This method is described immediately below.
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project = createProject()
project.load('routed.nym')
project.createClock('getRegister(UUT1\|Gen_seq[2].seq_i\|temp_reg[13])', 'clk1', 2.7)
project.createClock('getClockNet(CLOCK[2])', 'clk2', 5, 0, 2)
project.setClockGroup('getClock(clk1)', 'getClock(clk2)', 'exclusive') |
setClockGroup(group1 = ‘group1', group2= ‘group2’, option = 'option’)
This method is used to specify which clocks are not related. This constraint is used by timing driven algorithms and static timing analysis.
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Name | Type | Description |
group1 | string | Mandatory. Specifies how to get a group of clocks. A valid clock should be a clock created by command createClock. A valid argument can be: |
group2_list | string | Mandatory. Same as the argument "group1_list" |
option | string | Mandatory. A valid option can be 'asynchronous' or 'exclusive': Asynchronous clocks are those that are completely unrelated. Exclusive clocks are not actively used in the design at the same time |
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project = createProject()
project.load('routed.nym')
project.createClock(name ='clk1', period = 2.7, target= 'getRegister(UUT1\|Gen_seq[2].seq_i\|temp_reg[13])')
project.createClock(name = 'clk2', period = 5, rising = 0, falling = 2, target= 'getClockNet(CLOCK[2])')
project.setClockGroup(group1 = 'getClock(clk1)', group2 = 'getClock(clk2)', option = 'exclusive') |
addMaxDelayPath(from_list, to_list, delay)
/ ! \ DEPRECATED / ! \ Please use setMaxDelay instead, with the same key arguments. This method is described immediately below.
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project = createProject()
project.load('routed.nym')
project.addMaxDelayPath('getRegister('UUT1\|Gen_seq[3].seq_i\|temp_reg[1]')', 'getRegister('UUT2\|dout_reg[61]')', 3.9)
project.addMaxDelayPath('getPort(cpt_in[0])', 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', 8.0)
project.addMaxDelayPath('getRegister(i_cpt_0\|s_cpt_out_reg[0])','getRegister(i_cpt_1\|s_cpt_out_reg[1])', 4.0)
project.addMaxDelayPath('getPorts("cpt_in[`[1-3]`]")','getRegister(i_cpt_1\|s_cpt_out_reg[1])', 8.0)
project.addMaxDelayPath('getRegisters("i_cpt_0\|s_cpt_out_reg[`[1-3]`]")', 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', 8.0) |
setMaxDelay(source = ‘source', target = ‘target’, delay = 'delay’)
This method is used to specify the maximum delay path for the timing paths. It is used by timing driven algorithms and static timing analysis.
Arguments:
Name | Type | Description |
from_listsource | string | Specifies how to get a timing path starting points. A valid timing starting point can be either an input port or a register. A valid argument can be: |
target | string | Specifies how to get a timing path ending points. A valid timing ending point can be either an output port or a register. A valid argument can be: |
delay | float | The required maximum delay value in ns for specified paths. |
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project = createProject()
project.load('routed.nym')
project.setMaxDelay(source = 'getRegister('UUT1\|Gen_seq[3].seq_i\|temp_reg[1]')', target = 'getRegister('UUT2\|dout_reg[61]')', delay = 3.9)
project.setMaxDelay(source = 'getPort(cpt_in[0])', target = 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', delay = 8.0)
project.setMaxDelay(source = 'getRegister(i_cpt_0\|s_cpt_out_reg[0])', target = 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', delay = 4.0)
project.setMaxDelay(source = 'getPorts("cpt_in[`[1-3]`]")', target = 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', delay = 8.0)
project.setMaxDelay(source = 'getRegisters("i_cpt_0\|s_cpt_out_reg[`[1-3]`]")', target = 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', delay = 8.0) |
addMinDelayPath(from_list, to_list, delay)
/ ! \ DEPRECATED / ! \ Please use setMinDelay instead, with the same key arguments. This method is described immediately below.
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project = createProject()
project.load('routed.nym')
project.addMinDelayPath('getRegister('UUT1\|Gen_seq[3].seq_i\|temp_reg[23]')', 'getRegister('UUT1\|Gen_seq[3].seq_i\|temp_reg[22]')', 1.2)
project.addMinDelayPath('getPort(cpt_in[0])', 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', 8.0)
project.addMinDelayPath('getRegister(i_cpt_0\|s_cpt_out_reg[0])', 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', 8.0)
project.addMinDelayPath('getPorts("cpt_in[`[1-3]`]")', 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', 8.0)
project.addMinDelayPath('getRegisters("i_cpt_0\|s_cpt_out_reg[`[1-3]`]")', 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', 8.0) |
setMinDelay(source = ‘source', target = ‘target’, delay = 'delay’)
This method is used to specify the minimum delay path for the timing paths. It is used by timing driven algorithms and static timing analysis.
Arguments:
Name | Type | Description |
from_listsource | string | Specifies how to get a timing path starting points. A valid timing starting point can be either an input port or a register. A valid argument can be: |
target | string | Specifies how to get a timing path ending points. A valid timing ending point can be either an output port or a register. A valid argument can be: |
delay | float | The required minimum delay value in ns for specified paths. |
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project = createProject()
project.load('routed.nym')
project.setMinDelay(source = 'getRegister('UUT1\|Gen_seq[3].seq_i\|temp_reg[23]')', target = 'getRegister('UUT1\|Gen_seq[3].seq_i\|temp_reg[22]')', delay = 1.2)
project.setMinDelay(source = 'getPort(cpt_in[0])', target = 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', delay = 8.0)
project.setMinDelay(source = 'getRegister(i_cpt_0\|s_cpt_out_reg[0])', target = 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', delay = 8.0)
project.setMinDelay(source = 'getPorts("cpt_in[`[1-3]`]")', target = 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', delay = 8.0)
project.setMinDelay(source = 'getRegisters("i_cpt_0\|s_cpt_out_reg[`[1-3]`]")', target = 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', delay = 8.0) |
addMulticyclePath(from_list, to_list, cycle_count)
/ ! \ DEPRECATED / ! \ Please use setMulticyclePath instead, with the same key arguments. This method is described immediately below.
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This method is only available for path(s) whose source and target registers are clocked by the same clock! |
setMulticyclePath(source = 'source', target = 'target', pathMultiplier = 'pathMultiplier')
This method is used to specify the multicycle path for the timing paths. It is used by timing driven algorithms and static timing analysis.
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This method is only available for path(s) whose source and target registers are clocked by the same clock! |
addFalsePath(from_list, to_list)
/ ! \ DEPRECATED / ! \ Please use setFalsePath instead, with the same key arguments. This method is described immediately below.
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In order to match with all registers, it is possible to specify empty string ('') for parameters from_list or to_list.
-from and -to options apply the constraint to both the rising and falling edges
source or target SHOULD be set to empty.
setFalsePath(source = ‘source', target = 'target’)
This method is used to specify the false path for the timing paths. This constraint is used by timing driven algorithms and static timing analysis.
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In order to match with all registers, source or target can SHOULD be set to empty.-from and -to options apply the constraint to both the rising and falling edges
setInputDelay(clock, clock_mode, minimum_delay, maximum_delay, port_list)
/ ! \ DEPRECATED / ! \ Please use setInputDelay(clock = ‘clock', clockMode = ‘clockMode’, min = ‘min’, max = ‘max’, ports = 'ports’) instead. This method is described immediately below.
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project = createProject()
project.load('routed.nym')
project.createClock(getClockNet('CLK'),'CLK',8)
project.setInputDelay(getClock('CLK'),'rise', 1, 1.5, getPort('RST')) |
setInputDelay(clock = ‘clock', clockMode = ‘clockMode’, min = ‘min’, max = ‘max’, ports = 'ports’)
This method specifies the data arrival times at the specified input ports relative to the clock. The clock must refer to a clock name in the design. This constraint is used by timing driven algorithms and static timing analysis. Depending on the unit define in the project, timings are in ns or ps.
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project = createProject()
project.load('routed.nym')
project.createClock(target = 'getClockNet(CLK)', name = 'clock',period = 8)
project.setInputDelay(clock = 'getClock(clock)', clockMode = 'rise', min = 1, max = 1.5, ports = 'getPort(RST)') |
setOutputDelay(clock, clock_mode, minimum_delay, maximum_delay, port_list)
/ ! \ DEPRECATED / ! \ Please use setOutputDelay(clock = ‘clock', clockMode = ‘clockMode’, min = ‘min’, max = ‘max’, ports = 'ports’) instead. This method is described immediately below.
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project = createProject()
project.load('routed.nym')
project.createClock(getClockNet('CLK'),'CLK',8)
project.setOutputDelay(getClock('CLK'),'rise', 1.0, 1.5, getPorts('dataout[`[0−5]`]')) |
setOutputDelay(clock = ‘clock', clockMode = ‘clockMode’, min = ‘min’, max = ‘max’, ports = 'ports’)
This command specifies the data required times at the specified output ports relative to the clock. The clock must refer to a clock defined in the design. This constraint is used by timing driven algorithms and static timing analysis. Depending on the unit defined in the project, timings could be in ns or ps.
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project = createProject()
project.load('routed.nym')
project.createClock(target = 'getClockNet('CLK')', name = 'CLK', period = 8)
project.setOutputDelay(clock = 'getClock(clock)', clockMode = 'rise', min = 1, max = 1.5, ports = 'getPort(RST)') |
developCKGs()
This method automatically creates a generated clock constraint on each output of the PLLs and WFGs in current project. This constraint is used by timing driven algorithms and static timing analysis.
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project = createProject()
project.load('routed.nym')
project.createClock(target = 'getClockNet(CLK)', name ='clk', period = 8, rising = 0, falling = 4)
project.developCKGs()
project.createGeneratedClock(source = 'getWFGOutput(wfg_clk[1])', target= 'getRegister(data_reg[0])', name='clk1_div2', divideBy = 2) |
setAnalysisConditions(conditions)
/ ! \ DEPRECATED / ! \ Please use setAnalysisConditions(conditions = 'conditions') instead.
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project.setAnalysisConditions(WorstCase) |
setAnalysisConditions(conditions = 'conditions')
This method is used to specify the chip conditions for the static timing analysis. This constraint is used by timing driven algorithms and static timing analysis.
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project.setAnalysisConditions(conditions = 'worstcase') |
setCaseAnalysis(value, net_list)
/ ! \ DEPRECATED / ! \ Please use setCaseAnalysis(value = ‘value', netList = 'netList’) instead. This method is described immediately below.
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project = createProject()
project.load('routed.nym')
project.setCaseAnalysis(1, 'getNet(sel)') |
setCaseAnalysis(value = ‘value', netList = 'netList’)
This method is used to specify a constant logic value to the given tests. This constraint is used by timing driven algorithms and static timing analysis.
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project = createProject()
project.load('routed.nym')
project.setCaseAnalysis(value = '1', netList = 'getNet(sel)') |
addReportTimingPath(source = ‘source_reg', target = 'target_reg’)
This method gives the shortest and the longest delays of a path. This constraint is used by timing driven algorithms and static timing analysis.
Timing log files will only contain paths found between sources and targets from these queries.
Arguments:
Name | Type | Description |
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source_reg | string | Specifies the starting points of the timing paths to be analyzed. A valid argument can only be a register : |
target_reg | string | Specifies the ending points or destination objects of timing paths to be analyzed. A valid argument can be: |
Example:
This method should be launched after creating an Analyzer, as follow :
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Timing_analysis = p.createAnalyzer()
Timing_analysis.addReportTimingPath(source = 'getRegister(i_cpt_0|s_cpt_out_reg[1])', target ='getRegister(i_cpt_1|s_cpt_out_reg[2])')
Timing_analysis.launch() |
removeDesignConstraint(id= ‘id')
This method is used to remove a design constraint from the current project.
Remove constraint can be clocks, generated clocks, derived clocks of PLLs and WFGs, input delays, output delays, clock groups, analysis case, false paths, multicycle paths, min delay paths, and max delays paths.
Arguments:
Name | Type | Description |
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id | unsigned | The id of the design constraint to remove |
Example:
This method is used before launching a Static Timing Analysis or using TimingDriven:
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p.createClock(target=getClockNet('clk1'),name='clk1',period=20.000,rising=0,falling=10.000) #Clk1 is created with 50 MHz frequency
p.removeDesignConstraint(1)
p.createClock(target=getClockNet('clk1'),name='clk1',period=40.000,rising=0,falling=20.000) #Clk1 is now with 25 MHz frequency |
resetTimingConstraints()
This method is used to reset all design constraints from the current project.
Reseted constraints can be clocks, generated clocks, derived clocks of PLLs and WFGs, input delays, output delays, clock groups, analysis case, false paths, multicycle paths, min delay paths, and max delays paths.
This method takes no argument.
Example:
This method is used before launching a Static Timing Analysis or using TimingDriven:
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p.createClock(target=getClockNet('clk1'),name='clk1',period=20.000,rising=0,falling=10.000) #Clk1 is created with 50 MHz frequency
p.resetTimingConstraints() |
addReportPath(source = ‘source_reg', target = 'target_reg’)
This method gives the shortest and the longest delays of a path. This constraint is used by timing driven algorithms and static timing analysis.
Timing log files will still contain all paths. In addition, A file is create with shortest and longest paths found between sources and targets from each query.
Arguments:
Name | Type | Description |
|---|---|---|
source_reg | string | Specifies the starting points of the timing paths to be analyzed. A valid argument can only be a register : |
target_reg | string | Specifies the ending points or destination objects of timing paths to be analyzed. A valid argument can be: |
Example:
This method should be launched after creating an Analyzer, as follow :
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Timing_analysis = p.createAnalyzer()
Timing_analysis.addReportPath(source = 'getRegister(i_cpt_0|s_cpt_out_reg[1])', target ='getRegister(i_cpt_1|s_cpt_out_reg[2])')
Timing_analysis.launch() |