Link V1.0 /Nxmap22tool_22.1.0.1-v0: https://files.nanoxplore.com/f/3709351814f24326a310603188918fce48dfb748/?dl=1

Table of Contents

minLevel	1
maxLevel	7

Introduction

NanoXplore provides a tool in order to compute:

NX_PLL parameters : Generate parameters to set when instantiate NX_PLL in VHDL code
NX_WFG parameters
constrainModule constraints

Examples

: Generate parameters to set when instantiate NX_PLL

...

in VHDL code
confineModule constraints: Generate constraints to set to create and confine modules

Examples

NX_PLL

User needed PLL

Code Block

$ make pll_calculator_interface
pll_calculator_interface
Please set the variant ?
 1 - NG-MEDIUM 
 2 - NG-LARGE 
 3 - NG-ULTRA 
3
How the reference clock is generated ?
 1 - External 
 2 - Internal (internal oscillator)
1
What is the reference clock frequency in MHz ?
50
Do you want to set a VCO frequency or let the tool research automatically ?
 1 - Set VCO frequency 
 2 - Automatical research with 1st output clk
2
How many output clocks do you want to generate in the range [0;9] ?
2
What is the frequency of the output clock 0 in MHz ?
400
What is the frequency of the output clock 1 in MHz ?
200

//////////PLL setting//////////
|Signal |Frequency (MHz)|
|------ |-------------- |
|Ref    |50.0           |
|Ref_int|50.0           |
|VCO    |800.0          |
|------ |-------------- |
|DIVD5  |400.0          |
|DIVD4  |200.0          |

//////////PLL parameters//////////
ref_osc_on       => '0'                                             ,
ref_intdiv       => 0                                               ,
fbk_int_div      => 7                                               ,
clk_outdiv1      => to_bitvector(conv_std_logic_vector(0,3))        ,
clk_outdiv2      => to_bitvector(conv_std_logic_vector(0,3))        ,
clk_outdiv3      => to_bitvector(conv_std_logic_vector(0,3))        ,
clk_outdiv4      => to_bitvector(conv_std_logic_vector(0,3))        ,
clk_outdivd1     => to_bitvector(conv_std_logic_vector(0,4))        ,
clk_outdivd2     => to_bitvector(conv_std_logic_vector(0,4))        ,
clk_outdivd3     => to_bitvector(conv_std_logic_vector(0,4))        ,
clk_outdivd4     => to_bitvector(conv_std_logic_vector(1,4))        ,
clk_outdivd5     => to_bitvector(conv_std_logic_vector(0,4))

...

All available PLL

Code Block

breakoutMode	wide

$ make wfgpll_all_calculatorvalues_interface
wfgpll_all_calculatorvalues_interface
WhatPlease isset the inputvariant clock?
frequency in1 MHz ?
100
What is the output clock frequency in MHz. It has to be input clock frequency divided by power of 2 in the range [6.25;100.0]?
25
For how many input clock cycles do you want to shift output clock in the range [0;2] ?
1
On which edge of input clock do you want to generate output clock ?
 1 - Rising edge 
 2 - Falling edge
1

//////////WFG parameters//////////
mode             => '1'                                             ,
wfg_edge         => '1'                                             ,
pattern          => "0110011001100110"                              ,
pattern_end      => 15

constrainModules

Code Block

breakoutMode	wide

$ make constrain_modules HIERARCHY_FILE=~/fae/tool/tool/hierarchy.rpt HIERARCHY_LEVEL_MAX=2 EXCLUSIVE=False
constrain_modules HIERARCHY_FILE=/home/users/kchopier/fae/tool/tool/hierarchy.rpt HIERARCHY_LEVEL_MAX=2 EXCLUSIVE=False

#New sub-module
p.addModule('RAM(X6AAF88E9)','g_loop_depth4[0].i_RAM_example','RAM(X6AAF88E9)_MOD0-%')
#New sub-module
p.addModule('RAM(X6AAF88E9)','g_loop_depth4[1].i_RAM_example','RAM(X6AAF88E9)_MOD1-%')
#New sub-module
p.addModule('RAM(X5A5D25DC)','g_loop_depth8[0].i_RAM_example','RAM(X5A5D25DC)_MOD0-%')
#New sub-module
p.addModule('RAM(X5A5D25DC)','g_loop_depth8[1].i_RAM_example','RAM(X5A5D25DC)_MOD1-%')

p.createRegion('RAM(X6AAF88E9)_REG0',,,,,False)
p.createRegion('RAM(X6AAF88E9)_REG1',,,,,False)
p.createRegion('RAM(X5A5D25DC)_REG0',,,,,False)
p.createRegion('RAM(X5A5D25DC)_REG1',,,,,False)

p.confineModule('RAM(X6AAF88E9)_MOD0-0','RAM(X6AAF88E9)_REG0')
p.confineModule('RAM(X6AAF88E9)_MOD1-0','RAM(X6AAF88E9)_REG1')
p.confineModule('RAM(X5A5D25DC)_MOD0-0','RAM(X5A5D25DC)_REG0')
p.confineModule('RAM(X5A5D25DC)_MOD1-0','RAM(X5A5D25DC)_REG1')

statModules

Code Block

$ make stat_modules HIERARCHY_FILE=~/fae/tool/tool/hierarchy.rpt
stat_modules HIERARCHY_FILE=/home/users/kchopier/fae/tool/tool/hierarchy.rpt- NG-MEDIUM 
 2 - NG-LARGE 
 3 - NG-ULTRA 
2
How the reference clock is generated ?
 1 - External 
 2 - Internal (internal oscillator)
1
What is the reference clock frequency in MHz ?
50

//////////PLL Output Values//////////

CLK (MHz),VCO (MHz),CLK name,ref_osc_on,ref_intdiv,fbk_int_div,clk_outdivp1,clk_outdivp2,clk_outdivp3o2,clk_outdivo1
0.390625,200.0,DIVP3,'0',0,0,0,0,7,0
0.390625,200.0,DIVP3,'0',1,2,0,0,7,0
0.48828125,250.0,DIVP3,'0',1,3,0,0,7,0
0.5859375,300.0,DIVP3,'0',0,1,0,0,7,0
0.5859375,300.0,DIVP3,'0',1,4,0,0,7,0
0.68359375,350.0,DIVP3,'0',1,5,0,0,7,0
0.78125,400.0,DIVP3,'0',0,2,0,0,7,0
0.78125,400.0,DIVP3,'0',1,6,0,0,7,0
0.78125,200.0,DIVP3,'0',0,0,0,0,6,0
0.78125,200.0,DIVP2,'0',0,0,0,7,0,0
0.78125,200.0,DIVP3,'0',1,2,0,0,6,0
0.78125,200.0,DIVP2,'0',1,2,0,7,0,0

WFG

Code Block

breakoutMode	wide

$ make wfg_calculator_interface
wfg_calculator_interface
What is the input clock frequency in MHz ?
100
What is the output clock frequency in MHz. It has to be input clock frequency divided by power of 2 in the range [6.25;100.0]?
25
For how many input clock cycles do you want to shift output clock in the range [0;2] ?
1
On which edge of input clock do you want to generate output clock ?
 1 - Rising edge 
 2 - Falling edge
1

//////////WFG parameters//////////
mode             => '1'                                             ,
wfg_edge         => '1'                                             ,
pattern          => "0110011001100110"                              ,
pattern_end      => 15

constrainModules

Code Block

breakoutMode	wide

$ make constrain_modules HIERARCHY_FILE=~/fae/tool/tool/hierarchy.rpt HIERARCHY_LEVEL_MAX=2 EXCLUSIVE=False
constrain_modules HIERARCHY_FILE=/home/users/kchopier/fae/tool/tool/hierarchy.rpt HIERARCHY_LEVEL_MAX=2 EXCLUSIVE=False

#New sub-module
p.addModule('RAM(X6AAF88E9)','g_loop_depth4[0].i_RAM_example','RAM(X6AAF88E9)_MOD0-%')
#New sub-module
p.addModule('RAM(X6AAF88E9)','g_loop_depth4[1].i_RAM_example','RAM(X6AAF88E9)_MOD1-%')
#New sub-module
p.addModule('RAM(X5A5D25DC)','g_loop_depth8[0].i_RAM_example','RAM(X5A5D25DC)_MOD0-%')
#New sub-module
p.addModule('RAM(X5A5D25DC)','g_loop_depth8[1].i_RAM_example','RAM(X5A5D25DC)_MOD1-%')

p.createRegion('RAM(X6AAF88E9)_REG0',,,,,False)
p.createRegion('RAM(X6AAF88E9)_REG1',,,,,False)
p.createRegion('RAM(X5A5D25DC)_REG0',,,,,False)
p.createRegion('RAM(X5A5D25DC)_REG1',,,,,False)

p.confineModule('RAM(X6AAF88E9)_MOD0-0','RAM(X6AAF88E9)_REG0')
p.confineModule('RAM(X6AAF88E9)_MOD1-0','RAM(X6AAF88E9)_REG1')
p.confineModule('RAM(X5A5D25DC)_MOD0-0','RAM(X5A5D25DC)_REG0')
p.confineModule('RAM(X5A5D25DC)_MOD1-0','RAM(X5A5D25DC)_REG1')

statModules

Code Block

$ make stat_modules HIERARCHY_FILE=~/fae/tool/tool/hierarchy.rpt
stat_modules HIERARCHY_FILE=/home/users/kchopier/fae/tool/tool/hierarchy.rpt

////////// GEN_HIER0_COL-0 //////////
// TILE //
{'LUT': 0.0, 'DFF': 0.01, 'XLUT': 0.0, 'CY': 0.0, 'RFB': 0.0}
// CGB //
{'DSP': 0.0, 'RAM': 0.0}

////////// GEN_HIER0_ROW-0 //////////
// TILE //
{'LUT': 0.0, 'DFF': 0.01, 'XLUT': 0.0, 'CY': 0.0, 'RFB': 0.0}
// CGB //
{'DSP': 0.0, 'RAM': 0.0}

////////// GEN_HIER1_COL_0 //////////
// TILE //
{'LUT': 0.0, 'DFF': 0.01, 'XLUT': 0.0, 'CY': 0.0, 'RFB': 0.0}
// CGB //
{'DSP': 0.0, 'RAM': 0.0}

////////// GEN_HIER1_ROW_0 //////////
// TILE //
{'LUT': 0.0, 'DFF': 0.01, 'XLUT': 0.0, 'CY': 0.0, 'RFB': 0.0}
// CGB //
{'DSP': 0.0, 'RAM': 0.0}

////////// GEN_HIER1_ROW_1 //////////
// TILE //
{'LUT': 0.0, 'DFF': 0.01, 'XLUT': 0.0, 'CY': 0.0, 'RFB': 0.0}
// CGB //
{'DSP': 0.0, 'RAM': 0.0}

////////// GEN_HIER2_COUNTER0-0 //////////
// TILE //
{'LUT': 0.01, 'DFF': 0.01, 'XLUT': 0.0, 'CY': 0.0, 'RFB': 0.0}
// CGB //
{'DSP': 0.0, 'RAM': 0.0}

////////// GEN_HIER0HIER2_COLCOUNTER1-0 //////////
// TILE //
{'LUT': 0.0, 'DFF': 0.0111, 'XLUT': 0.0, 'CY': 0.0, 'RFB': 0.0}
// CGB //
{'DSP': 0.0, 'RAM': 0.0}


////////// GEN_HIER0_ROW-0 SUMMARY ///////////
// TILE //
{'LUT': 0.0, 'DFF': 0.01, 'XLUT': 0.0, 'CY': 0.0, 'RFB': 0.0}
// CGB //
{'DSP': 0.0, 'RAM': 0.0}

////////// GEN_HIER1_COL_0 //////////
// TILE //
{'LUT': 0.0, 'DFF': 0.01, 'XLUT': 0.0, 'CY': 0.0, 'RFB': 0.0}
// CGB //
{'DSP': 0.0, 'RAM': 0.0}

////////// GEN_HIER1_ROW_0 //////////
// TILE //
{'LUT': 0.0, 'DFF': 0.01, 'XLUT': 0.0, 'CY': 0.0, 'RFB': 0.0}
// CGB //
{'DSP': 0.0, 'RAM': 0.0}

////////// GEN_HIER1_ROW_1 //////////
// TILE //
{'LUT': 0.0, 'DFF': 0.01, 'XLUT': 0.0, 'CY': 0.0, 'RFB': 0.0}
// CGB //
{'DSP': 0.0, 'RAM': 0.0}

////////// GEN_HIER2_COUNTER0-0 //////////
// TILE //
{'LUT': 0.01, 'DFF': 0.01, 'XLUT': 0.0, 'CY': 0.0, 'RFB': 0.0}
// CGB //
{'DSP': 0.0, 'RAM': 0.0}

////////// GEN_HIER2_COUNTER1-0 //////////
// TILE //
{'LUT': 0.0, 'DFF': 0.11, 'XLUT': 0.0, 'CY': 0.0, 'RFB': 0.0}
// CGB //
{'DSP': 0.0, 'RAM': 0.0}


////////// SUMMARY //////////
|Module                  
|Module                          |TILE    |CGB     |
|--------------------------------|--------|--------|
|GEN_HIER0_COL-0                 |1       |0       |
|GEN_HIER0_ROW-0                 |1       |0       |
|GEN_HIER1_COL_0                 |1       |0       |
|GEN_HIER1_ROW_0                 |1       |0       |
|GEN_HIER1_ROW_1                 |1       |0       |
|GEN_HIER2_COUNTER0-0        |TILE    |CGB1      |
|--------------------------------|--------|-------- |0       |
|GEN_HIER0HIER2_COLCOUNTER1-0            |1       |10       |

compareProjects

compareInstances

Code Block

$ make compare_instances PROJECT_PATH=/home/users/kchopier/fae/tool/tool/top
compare_instances  |0       |
|GEN_HIER0_ROW-0                 |1       |0       |
|GEN_HIER1_COL_0                 |1       |0       |
|GEN_HIER1_ROW_0                 |1       |0       |
|GEN_HIER1_ROW_1                 |1       |0       |
|GEN_HIER2_COUNTER0-0            |1       |0       |
|GEN_HIER2_COUNTER1-0            |1       |0       |PROJECT_PATH=/home/users/kchopier/fae/tool/tool/top
Instance,4-LUT,DFF,XLUT,1-bit CY,RFB,CDC,CB,CS,DSP,RAM,WFG,PLL
/home/users/kchopier/fae/tool/tool/top_logic_NG-MEDIUM,13,0,0,0,0,0,0,0,0,0,0,0
/home/users/kchopier/fae/tool/tool/top_RAM_NG-MEDIUM,20,0,0,8,1,0,0,0,0,1,0,0

compareSta

Code Block

breakoutMode	wide

$ make compare_sta PROJECT_PATH=/home/users/kchopier/fae/tool/tool/test_2 STEP=Routed CONDITION=worstcase
compare_sta PROJECT_PATH=/home/users/kchopier/fae/tool/tool/test_2 STEP=Routed CONDITION=worstcase
Source,i_core_0|clk_core_1M (Rising),CLK_140M (Rising),rg~CLK_p (Rising),rg~i_core_0|clk_core_70M (Rising)
Target,i_core_0|clk_core_1M (Rising),CLK_140M (Rising),rg~CLK_p (Rising),rg~i_core_0|clk_core_70M (Rising)
Required,2.187 MHz,139.978 MHz,34.994 MHz,69.989 MHz
/home/users/kchopier/fae/tool/tool/test_22,29.657 MHz,130.924 MHz,28.395 MHz,74.789 MHz
/home/users/kchopier/fae/tool/tool/test_21,31.386 MHz,130.702 MHz,28.913 MHz,73.025 MHz
/home/users/kchopier/fae/tool/tool/test_20,33.485 MHz,130.924 MHz,31.586 MHz,72.312 MHz

Versions Compared

Old Version 2

New Version Current

Key

Introduction

Examples

Examples

NX_PLL

User needed PLL

All available PLL

constrainModules

statModules

WFG

constrainModules

constrainModules

statModules

compareProjects

compareInstances

compareSta

Page Comparison

Versions Compared

Old Version 2

New Version Current

Key

Introduction

Examples

Examples

NX_PLL

User needed PLL

All available PLL

constrainModules

statModules

WFG

constrainModules

constrainModules

statModules

compareProjects

compareInstances

compareSta