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Table of Content

Table of Contents

List of figures

CKS chronograms

Simplified PLL block diagram

...

NX_DES primitive

NX_SER primitive

Introduction

This document aims at giving guidelines on how to use the provided NX components in VHDL source code for NXmap3. Its purpose is to explain how to correctly instantiate the different supported NX components provided by NanoXplore for NXmap3 synthesis and implementation tools.

...

For each NX component, the reader will find a quick introduction and a description of both the generics and ports. He will also find a diagram of the component with an instantiation example in VHDL.

Clocks distribution and management

NX_BD

Description

The NX_BD component describes a Buffer Driver circuit that allows the user to direct the routing of a signal to the general routing or low-skew network.

Generics

mode

type string

default value “local_lowskew”

...

If mode is set to “global_lowskew”, the output signal is routed to global low skew network of fabric.

Ports

Ports	Direction	Type	Description
I	input	std_logic	Input signal
O	output	std_logic	Output signal

Example

This documentation only provides the instantiation of the component.

Code Block

language	vhdl

BD_0 : NX_BD

port map (

      I => CK_GEN

    , O => CK_LS

);

NX_CKS

Description

The NX_CKS component describes a ClocK Switch circuit that allows glitch free clock generation. It can be used to enable/disable the clock to part of the user’s logic – providing that the output signal will be glitch free – and the delay from the main clock to the generated one is un-significant.

...

The blue internal signals are CMD signal sampled on rising edge (SPL1) and then sampled on falling edge (SPL0). SPL0 is the final enable.

Ports

Ports	Direction	Type	Description
CKI	input	std_logic	Input clock
CMD	input	std_logic	Command
CKO	output	std_logic	Output clock

Example

This documentation only provides the instantiation of the component.

Code Block

language	vhdl

CKS_0 : NX_CKS

port map (

      CKI => CK

    , CMD => ENABLE

    , CKO => CKG

);

NX_PLL (NG-MEDIUM)

Description

The NX_PLL component describes a Phase Locked Loop circuit available in NG-MEDIUM. The PLL just as the WaveForm Generators (WFG) is part of the ClocK Generator block (also called CKG). There are 4 CKG blocks, on in each corner of the FPGA die.

...

Internal 200 MHz oscillator (precision and stability over PVT around 10%)
- Can be used as auxiliary clock
- In addition, this oscillator is used by NXmap to calibrate the programmable delays available in :
  - PLL feedback path
  - WFG (to delay the clocks)
  - IOs input, output and tri-state command paths (complex IO banks only)

Generics

location

type string

default value “” (no location constraint)

...

The calibration procedure takes about 10 µs at startup. No status is available on NG-MEDIUM.

Ports

Ports

Direction

Type

Description

REF

In

std_logic

Reference clock input

Connectivity: semi-dedicated clock inputs, clock trees (low skew network)

Note: If REF pin is connected to a PAD, please declare the pad with Turbo mode enabled.

FBK

In

std_logic

External FeedBack input

Connectivity: semi-dedicated clock inputs, clock trees (low skew network)

VCO

Out

std_logic

VCO output : Fvco = fbk_intdiv * 2**(fbk_div_on - ref_div_on + 1) * clk_ref_freq

Connectivity: WFG inputs

D1…D3

Out

std_logic

Divided clocks. Fvco frequency divided by 1, 2, 4, 8, 16, 32, 64 or 128

Important note: D1, D2 and D3 outputs are reset while PLL RDY is not asserted.

Connectivity: WFG inputs

OSC

Out

std_logic

Internal 200 MHz oscilator

Connectivity :WFG inputs, delay calibration system

RDY

Out

std_logic

High when PLL is locked

Connectivity: RDY inputs of WFGs, fabric…

Instantiation Example

This documentation only provides the instantiation of the component.

Code Block

language	vhdl

-- targetFreq = (refFreq * (2 * fbk_intdiv)) / (2^clk_outdiv1)) 

-- 12.5 MHz = (25 MHz * (2 * 4) / (2^4)) 

-- 50 MHz = (25 MHz * (2 * 4) / (2^2)) 

-- 

-- Please note that (refFreq * (2 * fbk_intdiv)) must be above 200 MHz and below 1200 MHz 

PLL_0 : NX_PLL 

   generic map ( 

        location    => “CKG1.PLL1”

      ,  fbk_intdiv  => 4 

      , clk_outdiv1 => 4  -- Divide by 2**4 = 16

      , clk_outdiv2 => 2  -- Divide by 2**2 = 4

   ) 

port map ( 

      REF => ck25MHz 

    , FBK => OPEN 

    , VCO => OPEN,

    , D1  => ck12_5MHz

    , D2  => ck50MHz

    , D3  => OPEN 

    , OSC => OPEN 

    , RDY => OPEN 

  );

Simulation

The NX_PLL VHDL simulation model is included in the NxLibrary (NxPackage.vhd). It allows to simulate any one of the possible NX_PLL configurations.

NX_PLL_L (NG-LARGE)

Description

The NX_PLL_L component describes a Phase Locked Loop circuit available in NG-LARGE The PLL just as the WaveForm Generators (WFG) is part of the ClocK Generator block (also called CKG). There are 4 CKG blocks, on in each corner of the FPGA die.

...

PLL_LOCKED: status pin. Goes high when the PLL is locked
CAL_LOCKED : this output goes high when the automatic process of delay calibration has completed (PLL and internal delays as well as neighboring IO banks delay)

Generics

location

type string

default value “”

...

The calibration procedure takes about 10 µs at startup. The “CAL_LOCKED” output goes high when the delay calibration process is complete. Can be used as status bit.

Ports

Ports

Direction

Type

Description

REF

In

std_logic

Reference clock input

Connectivity: semi-dedicated clock inputs, clock trees (low skew network)

Note: If REF pin is connected to a PAD, please declare the pad with Turbo mode enabled.

FBK

In

std_logic

External FeedBack input

Connectivity: semi-dedicated clock inputs, clock trees (low skew network)

R

In

std_logic

Active high Reset input. Must be activated when REF input frequency changes to force a re-locking process of the PLL

VCO

Out

std_logic

VCO output:

- Internal feedback: Fvco = 2 * (fbk_intdiv + 2) * clk_ref_freq / (ref_intdiv + 1)

- External feedback: Fvco = (pattern_end + 1) / n_sim_pat * clk_ref_freq / (ref_intdiv + 1)

Where n_sim_pat is the number of similar patterns sequence found in pattern_end+1 MSB bits of pattern.

REFO

Out

std_logic

Output of the REFerence divider. The division factor is set by the generic “ref_intdiv”

LDFO

Out

std_logic

Output of the FBK_INTDIV divider. The division factor is set by the generic ‘fbk_intdiv”

DIVP1

Out

std_logic

This output delivers a divided VCO frequency (by a power of 2). The division factor is set by the generic “clk_divoutp1”

DIVP2

Out

std_logic

This output delivers a divided VCO frequency (by a power of 2). The division factor is set by the generic “clk_divoutp2”

DIVP3

Out

std_logic

This output delivers a divided VCO frequency (by a power of 2). The division factor is set by the generic “clk_divoutp3o2”

DIVO1

Out

std_logic

This output delivers a divided VCO frequency (by an odd factor). The division factor is set by the generic “clk_divouto1”

DIVO2

Out

std_logic

This output delivers a divided VCO frequency (by an odd factor). The division factor is set by the generic “clk_divoutp3o2”

OSC

Out

std_logic

200 MHz coming from 400MHz internal oscilator

Connectivity :WFG inputs, delay calibration engine

PLL_LOCKED

Out

std_logic

High when PLL is locked

Connectivity: RDY inputs of WFGs, fabric…

CAL_LOCKED

Out

std_logic

High when the automatic calibration procedure of the current FPGA quarte area is complete

Connectivity: fabric

Instantiation Example

This documentation only provides the instantiation of the component.

Code Block

language	vhdl

-- In this example :

-- Fref = 25 MHz (and “ref_intdiv” = 0 for division factor of 1 

-- Fldfo = 25 MHz (used as feedback) 

-- Fvco = 400 MHz (25 MHz x (“fbk_intdiv” + 2) * 2 = 25 MHz * 16

-- Please note that Fvco must be in the range 200 to 800 MHz 

-- Fdivp1 = 400 MHz / (2 ** “clk_outdivp1”) = 400 MHz / 8 = 50 MHz

-- Fdivp2 = 400 MHz / (2 ** (“clk_outdivp2” + 1)) = 400 MHz / 32 = 12.5 MHz

-- Fdivp3o2 = 400 MHz / (2 ** (“clk_outdivp3o2” + 2)) = 400 MHz / 64 = 6.25 MHz

-- Fdivo2 = 400 MHz / ((2 * “clk_outdivp3o2”) + 5) = 400 MHz / 13 = 30.77 MHz

-- Fdivo1 = 400 MHz / ((2 * “clk_outdivo1”) + 3)) = 400 MHz / 9 = 44.44 MHz

PLLUT : NX_PLL_L 

generic map (

    location       => “CKG2.PLL1”, 

    cfg_use_pll    => '1', 
    
    ref_intdiv     => 0,      -- 0 to 31  ((N+1 : (%1 to %32)  -- 0 for div by 1 

    ref_osc_on     => '0',    -- 0: disabled - 1: enabled

    ext_fbk_on     => '0',    -- 0: disabled - 1: enabled

    fbk_intdiv     => 6,      -- 0 to 31  ((N+2)*2 : %4 to %66 by step 2)  -- Div by 16

    fbk_delay_on   => '0',    -- 0: no delay - 1: delay

    fbk_delay      => 0,      -- 0 to 63

    clk_outdivp1   => 3,      -- 0 to 7  P1 (2^n    : %1 to %128)  -- Div by 8

    clk_outdivp2   => 4,      -- 0 to 7  P2 (2^(n+1): %2 to %256)  -- Div by 32

    clk_outdivo1   => 3,      -- 0 to 7  O1 ((2n)+3 : %3 to  %17)  -- Div by 7

    clk_outdivp3o2 => 4       -- 0 to 7  P3 (2^(n+2): %4 to %512)  -- P3 : Div by 64 

                              --         O2 ((2n)+5 : %5 to  %19)  -- O2 : Div by 13

   )

port map (

    REF   => REFIN,

    FBK   => FBK,

    R     => RST,

    VCO   => VCO,              -- VCO = 400 MHz

    LDFO  => LDFO,             -- LDFO = 50 MHz

    REFO  => REFO,

    

    DIVO1 => DIVO1,            -- DIVO1 = 57.14 MHz

    DIVO2 => DIVO2,            -- DIVO2 = 30.77 MHz

    

    DIVP1 => DIVP1,            -- DIVP1 = 50 Mhz

    DIVP2 => DIVP2,            -- DIVP2 = 12.5 MHz

    DIVP3 => DIVP3,            -- DIVP3 = 6.25 MHz

    OSC   => OSC,

    PLL_LOCKED => PLL_LOCKED,

    CAL_LOCKED => CAL_LOCKED

);

Simulation

The NX_PLL VHDL simulation model is included in the NxLibrary (NxPackage.vhd). It allows to simulate any one of the possible NX_PLL configurations.

NX_WFG (NG-MEDIUM)

Description

The NX_WFG component is used to access the low skew lines and clock trees. Among the main WFG features:

User’s selectable clock inversion
Programmable delay line (0 to 64 taps)
Waveform generation by using a 2 to 16-tap user’s defined pattern
Includes synchronization with other WFG using pattern, in the same ClocK Generator

Anchor

	_Figure6
	_Figure6

...

Generics

delay

type integer

default value 0

...

This generic configures whether the input clock is inverted (‘1’) or not (‘0’). When sampling the input clock, this generic configures whether the sampling is done on rising edge (‘0’) or falling edge (‘1’).

Ports

Ports	Direction	Type	Description
SI	input	std_logic	Synchronization input (connected to the synchronization output of the master WFG)
ZI	input	std_logic	Input clock (connected to PLL VCO or D1, D2 or D3 output)
RDY	input	std_logic	Usually connected to the PLL RDY pin. Must be left unconnected for the WFG that generates the clock feedback for the PLL using external feedback. RDY input is an active low reset. When low, it disables the WFG behavior. When high or open, the WFG works as specified.
SO	output	std_logic	Synchronization output (Master WFG SO output is connected to all slave WFGs SI inputs)
ZO	output	std_logic	Generated clock (connected to clock tree)

Synchronizing WFG together can be useful if output clocks must be synchronous. It is made by getting the same source clock for Master and Slave WFG and connecting SO from Master WFG to Si of Slave WFG.

Note

When sampling the input clock, the synchronization input must be connected either to another WFG (using pattern) synchronization output or to the synchronization output of the WFG itself.

If synchronization comes from another WFG, both WFG must get the same pattern_end value.

Example

This documentation only provides the instantiation of the component.

Code Block

language	vhdl

-- CK50MHz at 50 MHz

--   NOTCK   = ~CK50MHz

--   CK25MHz = CK50MHz / 2

WFG_0 : NX_WFG

generic map (

      wfg_edge => ‘1’

)

port map (

      SI => OPEN, SO => OPEN, RDY => OPEN

    , ZI => CK50MHz, ZO => NOTCK

);

WFG_1 : NX_WFG

Generic map (

      mode    => ‘1’

    , pattern_end  => 1

    , pattern => b"1000000000000000"

)

port map (

      SI => SYNC, SO => SYNC, RDY => OPEN

    , ZI => CK50MHz, ZO => CK25MHz

);

Simulation

The NX_WFG VHDL simulation model is included in the NxLibrary (NxPackage.vhd). It allows to simulate any one of the possible NX_WFG configurations.

NX_WFG_L (NG-LARGE)

Description

The NX_WFG_L component is used to access the low skew lines and clock trees on NG-LARGE. The NX_WFG_L is very similar to the NX_WFG of NG-MEDIUM. The difference is that the NX_WFG_L have an additional active high Reset input.

...

User’s selectable clock inversion
Programmable delay line (0 to 64 taps)
Waveform generation by using a 2 to 16-tap user’s defined pattern
Includes synchronization with other WFG using pattern, in the same ClocK Generator

Anchor

	_Figure8
	_Figure8

...

Generics

location

type string

default value “” (no location constraint)

...

This generic configures whether the input clock is inverted (‘1’) or not (‘0’). When sampling the input clock, this generic configures whether the sampling is done on rising edge (‘0’) or falling edge (‘1’).

Ports

Ports	Direction	Type	Description
SI	input	std_logic	Synchronization input (connected to the synchronization output of the master WFG)
ZI	input	std_logic	Input clock (connected to PLL VCO or D1, D2 or D3 output)
RDY	input	std_logic	Usually connected to the PLL RDY pin. Must be left unconnected for the WFG that generates the clock feedback for the PLL using external feedback. RDY input is an active low reset. When low, it disables the WFG behavior. When high or open, the WFG works as specified.
R	Input	std_logic	Active high Reset. Can be fed by the LOCKED output of the NX_PLL_L.
SO	output	std_logic	Synchronization output (Master WFG SO output is connected to all slave WFGs SI inputs)
ZO	output	std_logic	Generated clock (connected to clock tree)

Synchronizing WFG together can be useful if output clocks must be synchronous. It is made by getting the same source clock for Master and Slave WFG and connecting SO from Master WFG to Si of Slave WFG.

Note

When sampling the input clock, the synchronization input must be connected either to another WFG (using pattern) synchronization output or to the synchronization output of the WFG itself.

If synchronization comes from another WFG, both WFG must get the same pattern_end value.

Example

This documentation only provides the instantiation of the component.

Code Block

language	vhdl

-- CK50MHz at 50 MHz

--   NOTCK   = ~CK50MHz

--   CK25MHz = CK50MHz / 2

WFG_0 : NX_WFG_L

generic map (

      location => “CKG1.WFG_C2”,

      wfg_edge => ‘1’

)

port map (

      SI => OPEN, SO => OPEN, RDY => OPEN

    , ZI => CK50MHz, ZO => NOTCK

);

WFG_1 : NX_WFG

Generic map (

      location => “CKG1.WFG_C2”,

      mode    => ‘1’,

      pattern_end  => 1,

      pattern => b"1000000000000000"

)

port map (

      SI => SYNC, SO => SYNC, RDY => OPEN

    , ZI => CK50MHz, ZO => CK25MHz

);

imulation

The NX_WFG_L VHDL simulation model is included in the NxLibrary (NxPackage.vhd). It allows to simulate any one of the possible NX_WFG_L configurations.

Core logic

NX_CY (!)

Note
on nxmap3, the NX_CY primitive includes only the dedicated arithmetic logic, excluding the Functional Element LUTs and FFs – unlike on nxmap2, where the NX_CY primitive included the FE logic shown in dashed lines.

Description

The NX_ADD component describes a 4-bit adder and carry look ahead circuit. It’s available on the FEs having arithmetic logic capabilities.

The NX_ADD is composed of 4 stages numbered from 1 to 4 where 1 represents the LSB.

Anchor

	_Figure10
	_Figure10

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Generics

add_carry

type integer range 0 to 2

...

This generic represents the way the CI (carry in) port is connected: 0 is for low, 1 for high and 2 for propagate which means it is connected to the previous NX_CY CO (carry out) port.

Ports

Ports	Direction	Type	Description
A[1:4]	input	std_logic	A input of each stage
BI[1:4]	input	std_logic	B input of each stage
CI	input	std_logic	Carry input
CO	output	std_logic	Carry output
S[1:4]	output	std_logic	Output of each stage

Example

This documentation only provides the instantiation of the component..

Code Block

language	vhdl

-- SUM[3:0] <= A[3:0] + ”10”&B[1:0]

ADD_0 : NX_CY

generic map (

      add_carry   => 0                     -- low

)

port map (

      A1 => A(0), B1 => B(0)

    , A2 => A(1), B2 => B(1)

    , A3 => A(2), B3 => ‘0’

    , A4 => A(3), B4 => ‘1’

    , CI => OPEN, CO => OPEN

    , S1 => SUM(0), S2 => SUM(1), S3 => SUM(2), S4 => SUM(3)

);

NX_LUT

Description

The NX_LUT component describes a 4-input LUT as part of a functional element (FE) as shown in the following diagram:

Anchor

	_Figure11
	_Figure11

...

Generics

lut_table

type bit_vector(15 downto 0)

...

I4 and I3 and I2 and I1 => lut_table = b“1000000000000000” (or x”8000”)
I4 or I3 or I2 or I1 => lut_table = b“1111111111111110” (or x”FFFE”)
(I4 and I3) xor (I2 and I1) => lut_table = x”0111 1000 1000 1000” (or x”7888”)

Ports

Ports	Direction	Type	Description
I[1:4]	input	std_logic	LUT inputs
O	output	std_logic	Output

Example

This documentation only provides the instantiation of the component.

Code Block

language	vhdl

LUT_0 : NX_LUT

generic map (

      lut_table => b“1000000000000000” -– O <= A and B and C and D

)

port map (

      I1 => A

    , I2 => B

    , I3 => C

    , I4 => D

    , O  => OUT

);

NX_DFF

Description

The NX_DFF component describes a DFF of the functional elements as shown in the following diagram:

Anchor

	_Figure12
	_Figure12

...

Generics

dff_ctxt

type std_logic

default value ‘U’

...

Note
Only dff_type = 0 is allowed for NG-MEDIUM and NG-LARGE.

Ports

Ports	Direction	Type	Description
I	input	std_logic	Input
CK	input	std_logic	Clock
L	input	std_logic	Load
R	input	std_logic	Reset
O	output	std_logic	Output

Example

This documentation only provides the instantiation of the component.

Code Block

language	vhdl

DFF_0 : NX_DFF

generic map (

      dff_edge  => ‘0’                 -- rising edge

    , dff_load  => ‘0’                 -- always load

    , dff_init  => ‘1’                 -- use connected reset net

    , dff_sync  => ‘1’                 -- synchronous reset

    , dff_ctxt  => ‘0’                 -- initial value is 0

)

port map (

      I  => IN

    , O  => OUT

    , CK => CLK

    , R  => RST

    , L  => OPEN

);

NX_RFB

Description

The NX_RFB component describes a Register File Block circuit that is a Simple Dual Port memory of 64 words of 16-bit (one is port dedicated to write, the second port is dedicated to read). The circuit includes Error Code Correction (EDAC).

...

NXmap support:

The current version of NXmap supports the implementation of simple decoders on the Write_Enable and Read_Enable commands paths (the Register_File must be instantiated).

LUTs are used as transparent for data inputs as well as read and write addresses (both inference and instantiation).

Future versions of NXmap will support higher flexibility such as multiplexers and other simple combinatorial function on the data and address input paths.

Generics

mem_ctxt (1)

type string

default value “”

...

This generic represents the front polarity of the WCK clock. ‘0’ is for rising edge and ‘1’ for falling edge.

Ports

Ports	Direction	Type	Description
RCK	input	std_logic	Read clock
WCK	input	std_logic	Write clock
I[1:16]	input	std_logic	Data input
COR	output	std_logic	Correction output flag
ERR	output	std_logic	Error output
O1 to O16	output	std_logic	Data output
RA1 to RA6	input	std_logic	Read address
RE1 to RE4	input	std_logic	Read enable
WA1 to WA6	input	std_logic	Write address
WE1 to WE4	input	std_logic	Write enable

Instantiation Example

This documentation only provides the instantiation of the component.

Code Block

language	vhdl

-- RFB 64 words of 16 bits

RFB_0 : NX_RFB 

generic map (

      ren_table => b"1111111111111111" – O <= ‘1’

    , wen_table => b"1010101010101010" – O <= I1

    , mem_ctxt  => "1111111111111111,0011001100110011," &

                      "1100110011001100,1111111111111111," &

                      "..."

                      -- other 64 words must be also initialized

)

port map (

      RCK => CLK, WCK => CLK

    , I1  => DI(0), ... , I16 => DI(15)

    , COR => COR, ERR => ERR

    , O1  => DO(0), ... , O16 => DO(15)

    , RA1 => RA(0), ... , RA6 => RA(5)

    , WA1 => WA(0), ... , WA6 => WA(5)

    , RE1 => OPEN,  ... , RE4 => OPEN

    , WE1 => WE

    , WE2 => OPEN,  ... , WE4 => OPEN

   );

NX_DSP (NG-MEDIUM)

Description

The NX_DSP component describes a Digital Signal Processor circuit that allows implementation of arithmetic computations such as multiply, add/subtract.

Anchor

	_Figure14
	_Figure14

...

Generics

std_mode

type string

default value “”

...

Operation	Opcode	Equation
Arithmetic operation
ADD	b”000000”	Z = Y + X
ADDC	b”000001”	Z = Y + X + CI
SUB	b”001010”	Z = Y – X
SUBC	b”001011”	Z = Y – X – CI
INCY	b”000101”	Z = Y + CI
DECY	b”000111”	Z = Y – CI
Logic operation
Y	b”100000”	Z = Y
notY	b”110000”	Z = ~Y
AND	b”100001”	Z = Y & X
ANDnotX	b”101001”	Z = Y & ~X
NAND	b”110001”	Z = ~(Y & X)
OR	b”100010”	Z = Y \| X
ORnotX	b”101010”	Z = Y \| ~X
NOR	b”110010”	Z = ~(Y \| X)
XOR	b”100011”	Z = Y ^ X
XNOR	b”110011”	Z = ~(Y ^ X)
INVALID OP	48 other possible values	Z = XXXXXXXXXXXXXX

Ports

Ports	Direction	Type	Description
A1 to A24	input	std_logic	24-bit A input
B1 to B18	input	std_logic	18-bit B input
C1 to C36	input	std_logic	36-bit C input
CAI1 to CAI18	input	std_logic	18-bit Cascaded A input
CAO1 to CAO18	output	std_logic	18-bit Cascaded A output
CBI1to CBI18	input	std_logic	18-bit Cascaded B input
CBO1 to CBO18	output	std_logic	18-bit Cascaded B output
CCI	input	std_logic	Cascaded Carry input
CCO	output	std_logic	Cascaded Carry output
CI	input	std_logic	Carry input
CK	input	std_logic	Clock (works on rising edges)
CO	output	std_logic	Carry output
CO37	output	std_logic	Carry output bit 37
CO49	output	std_logic	Carry output bit 49
CZI1 to CZI56	input	std_logic	56-bit Cascaded Z input
CZO1 to CZO56	output	std_logic	56-bit Cascaded Z output
D1 to D18	input	std_logic	18-bit D input
OVF	output	std_logic	Overflow output flag
R	input	std_logic	Reset for pipeline registers except Z output register (active high)
RZ	input	std_logic	Reset for Z output register only(active high)
WE	input	std_logic	Write enable: ‘0’: all DSP internal registers are frozen, ‘1’: normal operation
Z1 to Z56	output	std_logic	56-bit Z output

Instantiation Example

This documentation only provides the instantiation of the component.

Code Block

language	vhdl

-- MUL(47:0) <= A(23:0) * B(23:0)    unsigned

signal link : std_logic_vector(35 downto 0)

DSP_0 : NX_DSP

generic map (

      std_mode => “UMUL_18”

)

port map (

      A1    => A(0)   , ... , A24   => A(23)

    , B1    => B(12)  , ... , B12   => B(23)

    , B13   => OPEN   , ... , B18   => OPEN

    , C1    => OPEN   , ... , C36   => OPEN

    , D1    => OPEN   , ... , D18   => OPEN

    , Z1    => OPEN   , ... , Z56   => OPEN

    , CAI1  => OPEN   , ... , CAI18 => OPEN

    , CAO1  => OPEN   , ... , CAO18 => OPEN

    , CBI1  => OPEN   , ... , CBI18 => OPEN

    , CBO1  => OPEN   , ... , CBO18 => OPEN

    , CZI1  => OPEN   , ... , CZO56 => OPEN

    , CZO1  => link(0), ... , CZO36 => link(35)

    , CZO37 => OPEN   , ... , CZO56 => OPEN    

    , CCI   => OPEN   , CCO => OPEN, CK   => OPEN

    , CI    => OPEN   , CO  => OPEN, CO37 => OPEN, CO49 => OPEN

    , OVF   => OPEN   , R   => OPEN, RZ   => OPEN, WE   => OPEN

);

DSP_1 : NX_DSP

generic map (

      std_mode => “UMUL_EXT”

)

port map (

      A1    => A(0)   , ... , A24   => A(23)

    , B1    => B(0)   , ... , B12   => B(11)

    , B13   => OPEN   , ... , B18   => OPEN

    , C1    => OPEN   , ... , C36   => OPEN

    , D1    => OPEN   , ... , D18   => OPEN

    , Z1    => MUL(0) , ... , Z48   => MUL(47)

    , Z49   => OPEN   , ... , Z56   => OPEN

    , CAI1  => OPEN   , ... , CAI18 => OPEN

    , CAO1  => OPEN   , ... , CAO18 => OPEN

    , CBI1  => OPEN   , ... , CBI18 => OPEN

    , CBO1  => OPEN   , ... , CBO18 => OPEN

    , CZI1  => link(0), ... , CZO36 => link(35)

    , CZI36 => OPEN   , ... , CZI56 => OPEN

    , CZO1  => OPEN   , ... , CZO56 => OPEN    

    , CCI   => OPEN   , CCO => OPEN, CK   => OPEN

    , CI    => OPEN   , CO  => OPEN, CO37 => OPEN, CO49 => OPEN

    , OVF   => OPEN   , R   => OPEN, RZ   => OPEN, WE   => OPEN

);

Simulation

The NX_DSP VHDL simulation model is included in the NxLibrary (NxPackage). It allows to simulate any one of the possible NX_DSP configurations.

NX_DSP_SPLIT

The NX_DSP_SPLIT is an alternate primitive for using DSP blocks. It can be instantiated as many times as required in your design.

...

Code Block

language	vhdl

component DSP_SPLIT 

generic (

-------------------------------------------------------------------------

-- Generic declaration to define the "raw_config0" (cfg_mode). Defines :

------------------------------------------------------------------------- 

   SIGNED_MODE : bit              := '1';

   PRE_ADDER_OP : bit             := '0';  -- '0' = Additon, '1' = Subraction

   MUX_A : bit                    := '0';  -- '0' = A input, '1' = CAI input

   MUX_B : bit                    := '0';  -- '0' = B input, '1' = CBI input

   MUX_P : bit                    := '0';  -- '0' for PRE_ADDER, '0' for B input

   MUX_X : bit_vector(1 downto 0) := "01"; -- Select X operand "00" = C, 

                                                                  -- "01" = CZI, 

                                                                  -- "10" Select Z feedback 

                                                                  -- "11" = SHFT(CZI) & C(11:0),

   MUX_Y : bit                    := '0';  -- '0' Select MULT output, '1' for (B & A)

   MUX_CI : bit                   := '0';  -- Select fabric input (not cascade)

   MUX_Z : bit                    := '0';  -- Select ALU output (not ALU input operand coming from PR_Y

   

   Z_FEEDBACK_SHL12 : bit         := '0';  -- '0' for No shift, '1' for 12-bit left shift

   ENABLE_SATURATION : bit        := '0';  -- '0' for Disable, '1' for Enable

   SATURATION_RANK : bit_vector(5 downto 0) := "110110"; -- Weight of useful MSB on Z and CZO result 

                                                               -- (to define saturation and overflow) 

   

   ALU_DYNAMIC_OP : bit           := '0';  -- '0' for Static, '1' for Dynamic 

                                                 -- D(5:0) are used for dynamic operation

   CO_SEL : bit                   := '0';  -- '0' for CO = ALU(36), '1' for CO = ALU(48)   

-------------------------------------------------------------------------

-- Generic declaration to define the "raw_config1" (cfg_pipe_mux)

-------------------------------------------------------------------------

   PR_A_MUX : bit_vector(1 downto 0) := "01";         -- Number of pipe reg levels on A input

   PR_A_CASCADE_MUX : bit_vector(1 downto 0) := "10"; -- Number of pipe reg levels for CAO output

   PR_B_MUX : bit_vector(1 downto 0) := "01";         -- Number of pipe reg levels on B input

   PR_B_CASCADE_MUX : bit_vector(1 downto 0) := "10"; -- Number of pipe reg levels for CAO output

   

   PR_C_MUX : bit    := '0';       -- '0' for No pipe reg, '1' for 1 pipe reg

   PR_D_MUX : bit    := '1';       -- '0' for No pipe reg, '1' for 1 pipe reg

   PR_CI_MUX : bit   := '1';       -- '0' for No pipe reg, '1' for 1 pipe reg

   PR_P_MUX : bit    := '1';       -- '0' for No pipe reg, '1' for 1 pipe reg (Pre-adder)

   PR_X_MUX : bit    := '0';       -- '0' for No pipe reg, '1' for 1 pipe reg

   PR_Y_MUX : bit    := '1';       -- '0' for No pipe reg, '1' for 1 pipe reg

   PR_MULT_MUX : bit := '1';       -- No pipe reg  -- Register inside MULT

   PR_ALU_MUX : bit  := '0';       -- No pipe reg  -- Register inside ALU

   PR_Z_MUX : bit    := '1';       -- Registered output

   PR_CO_MUX : bit   := '0';       -- '0' for No pipe reg, '1' for 1 pipe reg

   PR_OV_MUX : bit   := '0';       -- '0' for No pipe reg, '1' for 1 pipe reg

-------------------------------------------------------------------------

-- Generic declaration to define the "raw_config2" (cfg_pipe_rst)

-------------------------------------------------------------------------

   ENABLE_PR_A_RST : bit    := '1';   -- '0' for Disable, '1' for Enable 

   ENABLE_PR_B_RST : bit    := '1';   -- '0' for Disable, '1' for Enable 

   ENABLE_PR_C_RST : bit    := '1';   -- '0' for Disable, '1' for Enable 

   ENABLE_PR_D_RST : bit    := '1';   -- '0' for Disable, '1' for Enable 

   ENABLE_PR_CI_RST : bit   := '1';   -- '0' for Disable, '1' for Enable 

   ENABLE_PR_P_RST : bit    := '1';   -- '0' for Disable, '1' for Enable 

   ENABLE_PR_X_RST : bit    := '1';   -- '0' for Disable, '1' for Enable 

   ENABLE_PR_Y_RST : bit    := '1';   -- '0' for Disable, '1' for Enable 

   ENABLE_PR_MULT_RST : bit := '1';   -- '0' for Disable, '1' for Enable 

   ENABLE_PR_ALU_RST : bit  := '1';   -- '0' for Disable, '1' for Enable 

   ENABLE_PR_Z_RST : bit    := '1';   -- '0' for Disable, '1' for Enable 

   ENABLE_PR_CO_RST : bit   := '1';   -- '0' for Disable, '1' for Enable 

   ENABLE_PR_OV_RST : bit   := '1';   -- '0' for Disable, '1' for Enable 

-------------------------------------------------------------------------

-- Constants declaration to define the "cfg_pipe_rst" -- raw_config3(6 downto 0)

-------------------------------------------------------------------------

   ALU_OP : bit_vector(5 downto 0) := "000000";  -- Addition = "000000", Subtract = "001010"

   ALU_MUX : bit                   := '0'  -- '0' for Don't swap ALU operands, '1' for ALU Swap operands

    );

port(

   CK : IN  std_logic;

   R : IN  std_logic;

   RZ : IN  std_logic;

   WE : IN  std_logic;

   

   CI : IN  std_logic;  

   A : IN  std_logic_vector(23 downto 0);

   B : IN  std_logic_vector(17 downto 0);

   C : IN  std_logic_vector(35 downto 0);

   D : IN  std_logic_vector(17 downto 0);

   CAI : IN  std_logic_vector(17 downto 0);

   CBI : IN  std_logic_vector(17 downto 0);

   CZI : IN  std_logic_vector(55 downto 0);

   CCI : IN  std_logic;  

   Z : out  std_logic_vector(55 downto 0);

   CO : OUT  std_logic; 

   CO36 : OUT  std_logic;  

   CO48 : OUT  std_logic;  

   OVF : OUT  std_logic;

   CAO : OUT  std_logic_vector(17 downto 0);

   CBO : OUT  std_logic_vector(17 downto 0);

   CZO : OUT  std_logic_vector(55 downto 0);

   CCO : OUT  std_logic  

  );

end component;

NX_DSP_L (NG-LARGE)

Description

The NX_DSP component describes a Digital Signal Processor circuit that allows implementation of arithmetic computations such as multiply, add/subtract.

...

CAO/CAI chain is 24-bit wide instead of 18-bit on NG-MEDIUM
CO57 output instead of CO49 on NG-MEDIUM

Anchor

	_Figure15
	_Figure15

...

Generics

std_mode

type string

default value “”

...

Operation	Opcode	Equation
Arithmetic operation
ADD	b”000000”	Z = Y+ X
ADDC	b”000001”	Z = Y + X + CI
SUB	b”001010”	Z = Y – X
SUBC	b”001011”	Z = Y – X – CI
INCY	b”000101”	Z = Y + CI
DECY	b”000111”	Z = Y – CI
Logic operation
Y	b”100000”	Z = Y
NotY	b”110000”	Z = ~Y
AND	b”100001”	Z = Y & X
ANDnotX	b”101001”	Z = Y & ~X
NAND	b”110001”	Z = ~(Y & X)
OR	b”100010”	Z = Y \| X
ORnotX	b”101010”	Z = Y \| ~X
NOR	b”110010”	Z = ~(Y \| X)
XOR	b”100011”	Z = Y ^ X
XNOR	b”110011”	Z = ~(Y ^ X)
INVALID OP	48 other possible values	Z = XXXXXXXXXXXXXX

Ports

Ports	Direction	Type	Description
A1 to A24	input	std_logic	24-bit A input
B1 to B18	input	std_logic	18-bit B input
C1 to C36	input	std_logic	36-bit C input
CAI1 to CAI23	input	std_logic	24-bit Cascaded A input
CAO1 to CAO24	output	std_logic	24-bit Cascaded A output
CBI1to CBI18	input	std_logic	18-bit Cascaded B input
CBO1 to CBO18	output	std_logic	18-bit Cascaded B output
CCI	input	std_logic	Cascaded Carry input
CCO	output	std_logic	Cascaded Carry output
CI	input	std_logic	Carry input
CK	input	std_logic	Clock (works on rising edges)
CO	output	std_logic	Carry output
CO37	output	std_logic	Carry output bit 37
CO57	output	std_logic	Carry output bit 57
CZI1 to CZI56	input	std_logic	56-bit Cascaded Z input
CZO1 to CZO56	output	std_logic	56-bit Cascaded Z output
D1 to D18	input	std_logic	18-bit D input
OVF	output	std_logic	Overflow output flag
R	input	std_logic	Reset for pipeline registers except Z output register (active high)
RZ	input	std_logic	Reset for Z output register only(active high)
WE	input	std_logic	Write enable: ‘0’: all DSP internal registers are frozen, ‘1’: normal operation
Z1 to Z56	output	std_logic	56-bit Z output

Instantiation Example

This documentation only provides the instantiation of the component.

Code Block

language	vhdl

-- MUL(47:0) <= A(23:0) * B(23:0)    unsigned

signal link : std_logic_vector(35 downto 0)

DSP_0 : NX_DSP_L

generic map (

      std_mode => “UMUL_18”

)

port map (

      A1    => A(0)   , ... , A24   => A(23)

    , B1    => B(12)  , ... , B12   => B(23)

    , B13   => OPEN   , ... , B18   => OPEN

    , C1    => OPEN   , ... , C36   => OPEN

    , D1    => OPEN   , ... , D18   => OPEN

    , Z1    => OPEN   , ... , Z56   => OPEN

    , CAI1  => OPEN   , ... , CAI24 => OPEN

    , CAO1  => OPEN   , ... , CAO24 => OPEN

    , CBI1  => OPEN   , ... , CBI18 => OPEN

    , CBO1  => OPEN   , ... , CBO18 => OPEN

    , CZI1  => OPEN   , ... , CZO56 => OPEN

    , CZO1  => link(0), ... , CZO36 => link(35)

    , CZO37 => OPEN   , ... , CZO56 => OPEN    

    , CCI   => OPEN   , CCO => OPEN, CK   => OPEN

    , CI    => OPEN   , CO  => OPEN, CO37 => OPEN, CO49 => OPEN

    , OVF   => OPEN   , R   => OPEN, RZ   => OPEN, WE   => OPEN

);

DSP_1 : NX_DSP_L

generic map (

      std_mode => “UMUL_EXT”

)

port map (

      A1    => A(0)   , ... , A24   => A(23)

    , B1    => B(0)   , ... , B12   => B(11)

    , B13   => OPEN   , ... , B18   => OPEN

    , C1    => OPEN   , ... , C36   => OPEN

    , D1    => OPEN   , ... , D18   => OPEN

    , Z1    => MUL(0) , ... , Z48   => MUL(47)

    , Z49   => OPEN   , ... , Z56   => OPEN

    , CAI1  => OPEN   , ... , CAI24 => OPEN

    , CAO1  => OPEN   , ... , CAO24 => OPEN

    , CBI1  => OPEN   , ... , CBI18 => OPEN

    , CBO1  => OPEN   , ... , CBO18 => OPEN

    , CZI1  => link(0), ... , CZO36 => link(35)

    , CZI36 => OPEN   , ... , CZI56 => OPEN

    , CZO1  => OPEN   , ... , CZO56 => OPEN    

    , CCI   => OPEN   , CCO => OPEN, CK   => OPEN

    , CI    => OPEN   , CO  => OPEN, CO37 => OPEN, CO49 => OPEN

    , OVF   => OPEN   , R   => OPEN, RZ   => OPEN, WE   => OPEN

);

Simulation

The NX_DSP_L VHDL simulation model is included in the NxLibrary (NxPackage). It allows to simulate any one of the possible NX_DSP_L configurations.

NX_DSP_L_SPLIT

The NX_DSP_L_SPLIT is an alternate primitive for using DSP blocks. It can be instantiated as many times as required in your design.

...

Code Block

language	vhdl

component NX_DSP_L_SPLIT 

generic (

-------------------------------------------------------------------------

-- Generic declaration to define the "raw_config0" (cfg_mode). Defines :

------------------------------------------------------------------------- 

   SIGNED_MODE : bit              := '1';

   PRE_ADDER_OP : bit             := '0';  -- '0' = Additon, '1' = Subraction

   MUX_A : bit                    := '0';  -- '0' = A input, '1' = CAI input

   MUX_B : bit                    := '0';  -- '0' = B input, '1' = CBI input

   MUX_P : bit                    := '0';  -- '0' for PRE_ADDER, '0' for B input

   MUX_X : bit_vector(1 downto 0) := "01"; -- Select X operand "00" = C, 

                                                                  -- "01" = CZI, 

                                                                  -- "10" Select Z feedback 

                                                                  -- "11" = SHFT(CZI) & C(11:0),

   MUX_Y : bit                    := '0';  -- '0' Select MULT output, '1' for (B & A)

   MUX_CI : bit                   := '0';  -- Select fabric input (not cascade)

   MUX_Z : bit                    := '0';  -- Select ALU output (not ALU input operand coming from PR_Y

   

   Z_FEEDBACK_SHL12 : bit         := '0';  -- '0' for No shift, '1' for 12-bit left shift

   ENABLE_SATURATION : bit        := '0';  -- '0' for Disable, '1' for Enable

   SATURATION_RANK : bit_vector(5 downto 0) := "110110"; -- Weight of useful MSB on Z and CZO result 

                                                               -- (to define saturation and overflow) 

   

   ALU_DYNAMIC_OP : bit           := '0';  -- '0' for Static, '1' for Dynamic 

                                                 -- D(5:0) are used for dynamic operation

   CO_SEL : bit                   := '0';  -- '0' for CO = ALU(36), '1' for CO = ALU(48)   

-------------------------------------------------------------------------

-- Generic declaration to define the "raw_config1" (cfg_pipe_mux)

-------------------------------------------------------------------------

   PR_A_MUX : bit_vector(1 downto 0) := "01";         -- Number of pipe reg levels on A input

   PR_A_CASCADE_MUX : bit_vector(1 downto 0) := "10"; -- Number of pipe reg levels for CAO output

   PR_B_MUX : bit_vector(1 downto 0) := "01";         -- Number of pipe reg levels on B input

   PR_B_CASCADE_MUX : bit_vector(1 downto 0) := "10"; -- Number of pipe reg levels for CAO output

   

   PR_C_MUX : bit    := '0';       -- '0' for No pipe reg, '1' for 1 pipe reg

   PR_D_MUX : bit    := '1';       -- '0' for No pipe reg, '1' for 1 pipe reg

   PR_CI_MUX : bit   := '1';       -- '0' for No pipe reg, '1' for 1 pipe reg

   PR_P_MUX : bit    := '1';       -- '0' for No pipe reg, '1' for 1 pipe reg (Pre-adder)

   PR_X_MUX : bit    := '0';       -- '0' for No pipe reg, '1' for 1 pipe reg

   PR_Y_MUX : bit    := '1';       -- '0' for No pipe reg, '1' for 1 pipe reg

   PR_MULT_MUX : bit := '1';       -- No pipe reg  -- Register inside MULT

   PR_ALU_MUX : bit  := '0';       -- No pipe reg  -- Register inside ALU

   PR_Z_MUX : bit    := '1';       -- Registered output

   PR_CO_MUX : bit   := '0';       -- '0' for No pipe reg, '1' for 1 pipe reg

   PR_OV_MUX : bit   := '0';       -- '0' for No pipe reg, '1' for 1 pipe reg

-------------------------------------------------------------------------

-- Generic declaration to define the "raw_config2" (cfg_pipe_rst)

-------------------------------------------------------------------------

   ENABLE_PR_A_RST : bit    := '1';   -- '0' for Disable, '1' for Enable 

   ENABLE_PR_B_RST : bit    := '1';   -- '0' for Disable, '1' for Enable 

   ENABLE_PR_C_RST : bit    := '1';   -- '0' for Disable, '1' for Enable 

   ENABLE_PR_D_RST : bit    := '1';   -- '0' for Disable, '1' for Enable 

   ENABLE_PR_CI_RST : bit   := '1';   -- '0' for Disable, '1' for Enable 

   ENABLE_PR_P_RST : bit    := '1';   -- '0' for Disable, '1' for Enable 

   ENABLE_PR_X_RST : bit    := '1';   -- '0' for Disable, '1' for Enable 

   ENABLE_PR_Y_RST : bit    := '1';   -- '0' for Disable, '1' for Enable 

   ENABLE_PR_MULT_RST : bit := '1';   -- '0' for Disable, '1' for Enable 

   ENABLE_PR_ALU_RST : bit  := '1';   -- '0' for Disable, '1' for Enable 

   ENABLE_PR_Z_RST : bit    := '1';   -- '0' for Disable, '1' for Enable 

   ENABLE_PR_CO_RST : bit   := '1';   -- '0' for Disable, '1' for Enable 

   ENABLE_PR_OV_RST : bit   := '1';   -- '0' for Disable, '1' for Enable 

-------------------------------------------------------------------------

-- Constants declaration to define the "cfg_pipe_rst" -- raw_config3(6 downto 0)

-------------------------------------------------------------------------

   ALU_OP : bit_vector(5 downto 0) := "000000";  -- Addition = "000000", Subtract = "001010"

   ALU_MUX : bit                   := '0'  -- '0' for Don't swap ALU operands, '1' for ALU Swap operands

    );

port(

   CK : IN  std_logic;

   R : IN  std_logic;

   RZ : IN  std_logic;

   WE : IN  std_logic;

   

   CI : IN  std_logic;  

   A : IN  std_logic_vector(23 downto 0);

   B : IN  std_logic_vector(17 downto 0);

   C : IN  std_logic_vector(35 downto 0);

   D : IN  std_logic_vector(17 downto 0);

   CAI : IN  std_logic_vector(23 downto 0);

   CBI : IN  std_logic_vector(17 downto 0);

   CZI : IN  std_logic_vector(55 downto 0);

   CCI : IN  std_logic;  

   Z : out  std_logic_vector(55 downto 0);

   CO : OUT  std_logic; 

   CO36 : OUT  std_logic;  

   CO56 : OUT  std_logic;  

   OVF : OUT  std_logic;

   CAO : OUT  std_logic_vector(23 downto 0);

   CBO : OUT  std_logic_vector(17 downto 0);

   CZO : OUT  std_logic_vector(55 downto 0);

   CCO : OUT  std_logic  

  );

end component;

NX_ECC

Description

The NX_ECC component describes an Error Code Correction circuit that can be used with memory declaration to add error correction support.

The NX_ECC can be instantiated with inferred memory blocks. The user must connect the LSB of the NX_RAM output data to the CHK input, and then use the COR and ERR flags.

Ports

Ports	Direction	Type	Description
CKD	input	std_logic	Input clock
CHK	input	std_logic	Check link This pin must be connected to the LSB of the output memory block – for each port requiring the ECC function.
COR	output	std_logic	One error found and corrected
ERR	output	std_logic	Errors found and not corrected

Instantiation Example

This documentation only provides the instantiation of the component.

Code Block

language	vhdl

entity hdpecc_4Kx32 is

port(

    ckw : in std_logic;

    ckr : in std_logic;

    ckq : in std_logic;

    we  : in std_logic;

    adw : in std_logic_vector (11 downto 0);

    adr : in std_logic_vector (11 downto 0);

    di  : in std_logic_vector (31 downto 0);

    do  : out std_logic_vector (31 downto 0);

    cor : out std_logic;

    err : out std_logic

);

end entity;

architecture rtl of hdpecc_4Kx32 is 

    type mem_reg is array (4095 downto 0) of std_logic_vector(31 downto 0);

    signal mem : mem_reg;

begin

    hdpram_ecc: NX_ECC

    port map (

          CKD => ckq

        , CHK => do(0)

        , COR => cor

        , ERR => err

    );

NX_RAM (NG-MEDIUM & NG-LARGE)

Description

The NX_RAM component describes a synchronous True Dual Port Random Access Memory circuit of 48 Kbits available in NG-MEDIUM. The circuit supports Error Code Correction (ECC, also called EDAC – Error Detection and Correction).

...

However, simultaneous write access on both ports at the same physical address, or write access simultaneous with a read access at the same physical address are not allowed.

Anchor

	_Figure16
	_Figure16

...

Memory ports configurations

Optional input and output behavior and pipeline registers:

By default, the RAM block do not use pipeline registers. The output delivers a valid data T_{access_time}after the clock edge that samples the read address (ACS = ‘1’ and AWE = ‘0’) or BCS = ‘1’ and BWE = ‘0’).

...

In addition, the polarity of the block RAM clock as well as the one of the register clocks can be modified by the user (see NX_RAM raw_config0).

No ECC modes

The NO_ECC configuration mode is set by generics (raw_config1(15:12) = “0000”.

...

In 16K x 3 configuration, the 3-bit data input must be replicated 8 times
In 8K x 6 configuration, the 3-bit data input must be replicated 4 times

ECC modes (NG-MEDIUM & NG-LARGE)

When used with ECC, the user array size is restricted to 2K x 18. The 6 remaining bits of each internal address of 24-bit words are used to store the ECC signature of each 18-bit data.

...

The physical connections of address and input/output data lines is shown in the next figure.

Anchor

	_Figure20
	_Figure20

...

ECC data correction in FAST mode

If a single bit error is found, it will be automatically detected and corrected at the RAM output port. The flags ACOR or BCOR are set during the read cycle to signal the error detection and correction. However, the internal memory array remains corrupt.
If a double bit error is detected, it can’t be corrected, and the flags AERR or BERR are asserted.

ECC data correction in SLOW mode

This mode is also called Read Repair Mode (RRM).
If a single bit error is found, it will be automatically detected and corrected at the RAM output port, and the memory content is automatically updated with the corrected value. The flags ACOR or BCOR are set during the user’s read cycle to signal the error detection and correction.
If a double bit error is detected, it can’t be corrected, but the flags AERR or BERR are asserted.
In order to correct a possible error during a read access, the read cycle becomes a read modify write, where the write half cycle is transparent to the user. For this, the NG-MEDIUM RAM blocks use a doubled internal frequency. This internal clock is generated by using an exclusive OR, between the main clock (CKA or CKB) and the 90° shifted clock (ACKD or BCKD) required to support the ECC SLOW mode.
Using ACKD and/or BCKD in ECC SLOW mode is mandatory. It must be a 90° phase shifted version of the main clock input (ACK and/or BCK). ACKD and BCKD can each be generated with ACK and BCK by using PLL and WFGs.
In this mode, the internal RAM block works a frequency that is double of the user’s clock. The maximum user’s clock frequency is then reduced by a factor of 2, approximately.

Generics

mcka_edge

type bit

default value ‘0’

...

This generic is reserved for future versions.

Ports

Ports	Direction	Type	Description
ACK	input	std_logic	A port memory main clock
ACKC	input	std_logic	A port memory clock clone. Must be connected to the same clock source as ACK
ACKD	input	std_logic	A port memory 90° shifted clock. ACKD must be used when Read Repair Mode is selected on this port. It allows to internally generate a double frequency for the memory matrix, to allow read modify write during a single user’s clock cycle.
ACKR	input	std_logic	A port register clock. ACKR must be fed by a valid clock (typically ACK), if the optional input or output pipeline registers are used.
BCK	input	std_logic	B port memory main clock.
BCKC	input	std_logic	B port memory clock clone. Same comments as for ACKC
BCKD	input	std_logic	B port memory 90° shifted clock. Just as ACKD, BCKD is used when Read Repair Mode is selected on B port.
BCKR	input	std_logic	B port register clock. BCKR must be fed by a valid clock (typically BCK), if the optional input or output pipeline registers are used.
AI1 to AI24	input	std_logic	A port input data. See notes on data input width for proper operation.
BI1 to BI24	input	std_logic	B port input data. See notes on data input width for proper operation.
ACOR	output	std_logic	Goes high for one clock cycle when an error has been detected and corrected on port A
AERR	output	std_logic	Goes high for one clock cycle when an uncorrectable error has been found on port A
BCOR	output	std_logic	Goes high for one clock cycle when an error has been detected and corrected on port A
BERR	output	std_logic	Goes high for one clock cycle when an uncorrectable error has been found on port A
AO1 to AO24	output	std_logic	A port output data. See notes on data output width for proper operation
BO1 to BO24	output	std_logic	B port output data. See notes on data output width for proper operation
AA1 to AA16	input	std_logic	A port address. See notes on physical and logical addresses for proper operation
ACS	input	std_logic	A port chip select (active high)
AWE	input	std_logic	A port write enable (active high)
AR	input	std_logic	A port registers reset (active high)
BA1 to BA16	input	std_logic	B port address. See notes on physical and logical addresses for proper operation
BCS	input	std_logic	B port chip select (active high)
BWE	input	std_logic	B port write enable (active high)
BR	input	std_logic	B port registers reset (active high)

...

The BCKC and BCKD ports must be connected as described for ACKC and ACKD. BR is the synchronous reset of the optional input and output registers on port B.

Instantiation Example

Code Block

-- RAM with Fast ECC: 1024 words of 18 bits and 1 read/write port

RAM_0 : NX_RAM 

generic map (

   std_mode => "FAST_2kx18",

   mem_ctxt => (

                  "000000111111111111111111,000000001100110011001100,

                   000000110011001100110011,000000111111111111111111," &

                  "000000111111111111111111,000000001100110011001100,

                   000000110011001100110011,000000111111111111111111," &

			    “...”

                  "000000111111000000111001,000000001100110011001100,

                   000000110011001100110011,000000111000111111000110," &

                  "000000111111111111111111,000000001100110011001100,

                   000000110011001100110011,000000111010110011111001" 

		   -- other 2048 words must be also initialized

   )

port map (

      ACK  => CLK,  ACKC => CLK,  ACKD => OPEN, ACKR => OPEN

    , AI1  => DI(0), ... , AI18 => DI(17)

    , AI19 => OPEN,  ... , AI24 => OPEN

    , ACOR => COR,  AERR => ERR

    , AO1  => DO(0), ... , AO18 => DO(17)

    , AO19 => OPEN,  ... , AO24 => OPEN

    , AA1  => AD(0), ... , AA10 => AD(9)

    , AA11 => OPEN,  ... , AA16 => OPEN

    , ACS  => ‘1’, AWE => WE,   AR => OPEN

    , BCK  => OPEN, BCKC => OPEN, BCKD => OPEN, BCKR => OPEN

    , BI1  => OPEN,  ... , BI24 => OPEN

    , BCOR => OPEN, BERR => OPEN

    , BO1  => OPEN,  ... , BO24 => OPEN

    , BA1  => OPEN,  ... , BA16 => OPEN

    , BCS  => OPEN, BWE => OPEN, BR => OPEN

);

Simulation

The NX_RAM VHDL simulation model is included in the NxLibrary (NxPackage.vhd). It allows to simulate any one of the possible configurations, including with ECC in FAST or SLOW modes.

NX_RAM_WRAP (NG-MEDIUM & NG-LARGE)

Description

The NX_RAM_WRAP provides an alternate way to instantiate NX_RAM. It uses the same generics as NX_RAM, and the ports are grouped as busses whenever possible.

Generics

std_mode : string := "";

mcka_edge : bit := '0';

...

Please, refer to the NX_RAM chapter for more detailed information.

Ports

Ports	Direction	Type	Description
ACK	input	std_logic	A port memory main clock
ACKD	input	std_logic	A port memory 90° shifted clock. ACKD must be used when Read Repair Mode is selected on this port. It allows to internally generate a double frequency for the memory matrix, to allow read modify write during a single user’s clock cycle.
ACKR	input	std_logic	A port register clock. ACKR must be fed by a valid clock (typically ACK), if the optional input or output pipeline registers are used.
BCK	input	std_logic	B port memory main clock.
BCKD	input	std_logic	B port memory 90° shifted clock. Just as ACKD, BCKD is used when Read Repair Mode is selected on B port.
BCKR	input	std_logic	B port register clock. BCKR must be fed by a valid clock (typically BCK), if the optional input or output pipeline registers are used.
AI(23:0)	input	std_logic_vector	A port input data. See notes on data input width for proper operation.
BI(23:0)	input	std_logic_vector	B port input data. See notes on data input width for proper operation.
ACOR	output	std_logic	Goes high for one clock cycle when an error has been detected and corrected on port A
AERR	output	std_logic	Goes high for one clock cycle when an uncorrectable error has been found on port A
BCOR	output	std_logic	Goes high for one clock cycle when an error has been detected and corrected on port A
BERR	output	std_logic	Goes high for one clock cycle when an uncorrectable error has been found on port A
AO(23:0)	output	std_logic_vector	A port output data. See notes on data output width for proper operation
BO(23:0)	output	std_logic_vector	B port output data. See notes on data output width for proper operation
AA(15:0)	input	std_logic_vector	A port address. See notes on physical and logical addresses for proper operation
ACS	input	std_logic	A port chip select (active high)
AWE	input	std_logic	A port write enable (active high)
AR	input	std_logic	A port registers reset (active high)
BA(15:0)	input	std_logic_vector	B port address. See notes on physical and logical addresses for proper operation
BCS	input	std_logic	B port chip select (active high)
BWE	input	std_logic	B port write enable (active high)
BR	input	std_logic	B port registers reset (active high)

Instantiation Example

Code Block

language	vhdl

-- RAM with Fast ECC: 1024 words of 18 bits and 1 read/write port

RAM_0 : NX_RAM 

generic map (

   std_mode => "FAST_2kx18",

   mem_context => (

                  "000000111111111111111111,000000001100110011001100,

                   000000110011001100110011,000000111111111111111111" &

                  "000000111111111111111111000000001100110011001100,

                   000000110011001100110011,000000111111111111111111" &

			    “...”

                  "000000111111000000111001,000000001100110011001100,

                   000000110011001100110011,000000111000111111000110" &

                  "000000111111111111111111,000000001100110011001100,

                   000000110011001100110011,000000111010110011111001" 

		   -- other 2048 words must be also initialized

   )

port map (

      ACK  => CLK,  ACKC => CLK,  ACKD => OPEN, ACKR => OPEN

    , AI1  => DI(0), ... , AI18 => DI(17)

    , AI19 => OPEN,  ... , AI24 => OPEN

    , ACOR => COR,  AERR => ERR

    , AO1  => DO(0), ... , AO18 => DO(17)

    , AO19 => OPEN,  ... , AO24 => OPEN

    , AA1  => AD(0), ... , AA10 => AD(9)

    , AA11 => OPEN,  ... , AA16 => OPEN

    , ACS  => ‘1’, AWE => WE,   AR => OPEN

    , BCK  => OPEN, BCKC => OPEN, BCKD => OPEN, BCKR => OPEN

    , BI1  => OPEN,  ... , BI24 => OPEN

    , BCOR => OPEN, BERR => OPEN

    , BO1  => OPEN,  ... , BO24 => OPEN

    , BA1  => OPEN,  ... , BA16 => OPEN

    , BCS  => OPEN, BWE => OPEN, BR => OPEN

);

Simulation

The NX_RAM VHDL simulation model is included in the NxLibrary (NxPackage.vhd). It allows to simulate any one of the possible configurations, including with ECC in FAST or SLOW modes.

I/O elements

NX_IOB

Description

The NX_IOB component describes a bidirectional port of the design. The behavior is:

...

The NX_IOB can be instantiated anywhere in the design hierarchy. It allows to define buried ports (no signal appears in the ports list).

Anchor

	_Figure21
	_Figure21

...

Generics

Note that the generic assigned to this primitive can be overridden by the addPad or addPads methods in the script file.

...

location => ”IOB12_D4P”,

locked => ‘1’,

Ports

Ports	Direction	Type	Description
I	Input	std_logic	From FPGA fabric
C	Input	std_logic	Tristate control ‘0’: High impedance ‘1’: Enable output
T	Input	std_logic	Termination control ‘0’: No calibration ‘1’: calibration activated
O	output	std_logic	To FPGA fabric
IO	inout	std_logic	External pad

Example

This documentation only provides the instantiation of the component.

Code Block

language	vhdl

IOB_0 : NX_IOB

generic map(

    location             => “IOB12_D07P”,

    standard             => “LVCMOS_2.5V”,

    drive                => “4mA”

    slewRate             => “Fast”,

    turbo                => “true”,

    inputDelayOn      => “true”,

    inputDelayLine      => “10”,

    outputDelayOn      => “true”,

    outputDelayLine      => “17”,

    outputCapacity       => “15”,

    locked               => ‘1’

   )

port map (

      I =>  fromFPGAcore

    , O =>  toFPGAcore

    , C =>  enable

    , T =>  ’0’

    , IO => open     -- A signal name is not required on the external  

                     -- signal

                     -- The pad will take the name of the instance

);

NX_IOB_I

Description

The NX_IOB_I component describes an input port of the design. The behavior is:

...

The NX_IOB can be instantiated anywhere in the design hierarchy. It allows to define buried ports (no signal appears in the ports list).

Anchor

	_Figure22
	_Figure22

...

Generics

Note that the generic assigned to this primitive can be overridden by the addPad or addPads methods in the script file.

...

location => ”IOB12_D4P”,

locked => ‘1’,

Ports

Ports	Direction	Type	Description
C	Input	Std_logic	Not used. Must be left “open” or unconnected
T	Input	std_logic	Termination control ‘0’ : No termination ‘1’ : Input termination activated
O	output	std_logic	From FPGA fabric
IO	Input	std_logic	External pad

Example

This documentation only provides the instantiation of the component.

Code Block

language	vhdl

IOB_0 : NX_IOB_I

generic map(

    location             => “IOB12_D10P”,

    standard             => “LVCMOS_2.5V”,

    drive                => “4mA”

    turbo                => “true”,

    inputDelayOn         => “true”,

    inputDelayLine       => “13”,

    inputSignalSlope     => “8”,

    locked               => ‘1’

   )

port map (

      O =>  toFPGAcore

    , T =>  ’1’

    , IO => open     -- A signal name is not required on the external  

                     -- signal

                     -- The pad will take the name of the instance

   );

NX_IOB_O

Description

The NX_IOB_O component describes an output port of the design. The behavior is:

...

The NX_IOB can be instantiated anywhere in the design hierarchy. It allows to define buried ports (no signal appears in the ports list).

Anchor

	_Figure23
	_Figure23

...

Generics

Note that the generic assigned to this primitive can be overridden by the addPad or addPads methods in the script file.

...

location => ”IOB12_D4P”,

locked => ‘1’,

Ports

Ports	Direction	Type	Description
I	input	std_logic	From FPGA fabric
C	input	std_logic	Tristate control (‘0’ for High Z)
T	input	std_logic	Not used. Must be left “open” or unconnected
IO	output	std_logic	External pad

Example

This documentation only provides the instantiation of the component.

Code Block

language	vhdl

IOB_0 : NX_IOB_O

generic map(

    location             => “IOB12_D10P”,

    standard             => “LVCMOS_2.5V”,

    drive                => “4mA”

    slewRate             => “Fast”,

    outputDelayOn        => “true”,

    outputDelayLine      => “17”,

    outputCapacity       => “15”,

    locked               => ‘1’

   )

port map (

      I =>  fromFPGA

    , C =>  enable

    , IO => open     -- A signal name is not required on the external  

                     -- signal

                     -- The pad will take the name of the instance

   );

SERializers and DESerializers

Introduction

The NG-MEDIUM complex I/O banks provide serializers and deserializer features.

...

All I/O related delay lines have 0 to 63 x 160 ps steps delays.

SERDES architecture overview

The serializers/deserializers architecture contains two main blocks :

...

Anchor

	_Figure24
	_Figure24

...

Anchor

	_Figure25
	_Figure25

...

DPA : Dynamic Phase Adjustment

NG-MEDIUM architecture provides hardware support for Dynamic Phase Adjustment on NX_DES. The following describes how to implement the adjustment procedure.

...

LAUNCH_CALIB (input) : launches the calibration process (on a rising edge)
TRAINING_REQ_OUT (output) : The IP Core requests the transmitter to send the serialized “TrainingValue” to the DESerializer(s).
TRAINING_ACK_IN (input) : The transmitter is ready and sends the serialized “TrainingValue”
TRAINING_REQ_IN (input) : if the IP Core is used as transmitter, the receiver might require a calibration sequence where the transmitter must send the serialized “TrainingValue”. TRAINING_REQ_IN is the request input of the transmitter.
TRAINING_ACK_OUT (output) : When the transmitter receives a request from the receiver, it sends the serialized “TrainingValue” and activates the TRAINING_ACK output to the receiver.
CALIB_DONE (output) : goes high to state that the calibration process is done.
CALIB_ERROR (output) : Active high status bit to state that the calibration was not successful.

Anchor

	_Figure29
	_Figure29

...

NX_DES

Description

The NX_DES is a high performance DESerializer. The complex banks allows to configure the I/Os as DESerializers with deserialization factor from 3 to 5. Higher deserialization factors (6, 7, 8, 9 and 10) can be achieved by combining the two deserializers of a differential IO pair.

Anchor

	_Figure30
	_Figure30

...

Generics

data_size

type integer

default value Undefined (no default value)

...

This generic has no effect on the implementation process, but it’s used by the timing analyzer. The value must be specified in Volts/ns..Example :

inputSignalSlope => ”8”

Ports

Ports	Direction	Type	Description
FCK	In	Std_logic	Fast clock (bit clock)
SCK	In	Std_logic	Slow clock (word clock)
R	In	Std_logic	Active high Reset
IO	In	Std_logic	Input pad
O	Out	Std_logic_vector (data_size-1 downto 0)	Sampled word to FPGA fabric

DCK	In	Std_logic	Delay lines management registers clock
DRL	In	Std_logic	Delay Registers Load
DIG	In	Std_logic	‘0’ for Multicast write (*) ‘1’ for normal operation
DS	In	Std_logic_vector (1 downto 0)	Delay Select : 00 => out & tri-state regs 01 => input delay register 10 => DPA delay register 11 => RESERVED
DRA	In	Std_logic_vector (4 downto 0)	Delay address (0 to 29)
DRI	In	Std_logic_vector (5 downto 0)	Data input to delay registers
DRO	Out (with tri-state)	Std_logic_vector (5 downto 0)	Delay value being read Active when DRA = DID else high impedance
DID	Out	Std_logic_vector (4 downto 0)	Pad address identification
FZ	In	Std_logic	Active low Flags Reset
FLD	Out (with tri-state)	Std_logic	Early capture flag Active when DRA = DID else high impedance
FLG	Out (with tri-state)	Std_logic	Late capture flag Active when DRA = DID else high impedance

...

DIG must be high for normal operation, particularly for delay calibration.

NX _SER

Description

The NX_SER is a high performance SERializer. The complex banks allows to configure the I/Os as SERializers with serialization factor from 3 to 5. Higher serialization factors (6, 7, 8, 9 and 10) can be achieved by combining the two serializers of a differential IO pair.

Anchor

	_Figure31
	_Figure31

...

Generics

data_size

type integer

default value Undefined (no default value)

...

This generic has no effect on the implementation process, but it’s used by the timing analyzer. The value must be specified in ps..Example :

outpuCapacity => “15“

Ports

Ports	Direction	Type	Description
FCK	In	Std_logic	Fast clock (bit clock)
SCK	In	Std_logic	Slow clock (word clock)
R	In	Std_logic	Active high Reset
IO	Out	Std_logic	Input pad
I	In	Std_logic_vector (data_size-1 downto 0)	Data to be serialized from fabric

DCK	In	Std_logic	Delay lines management registers clock
DRL	In	Std_logic	Delay Registers Load
DS	In	Std_logic_vector (1 downto 0)	Delay Select : 00 => out & tri-state regs 01 => input delay register 10 => DPA delay register 11 => RESERVED
DRA	In	Std_logic_vector (4 downto 0)	Delay address (0 to 29)
DRI	In	Std_logic_vector (5 downto 0)	Data input to delay registers
DRO	Out (with tri-state)	Std_logic_vector (5 downto 0)	Delay value being read Active when DRA = DID, else high-impedance)
DID	Out	Std_logic_vector (4 downto 0)	Pad address identifier (0 to 29

Reserved

There are some other components defined in NX library that are reserved for post synthesis and post place & route simulation. These components cannot be instantiated in pre synthesis VHDL.

...

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List of figures

Introduction

Clocks distribution and management

NX_BD

Description

Generics

Ports

Example

NX_CKS

Description

Ports

Example

NX_PLL (NG-MEDIUM)

Description

Generics

Ports

Instantiation Example

Simulation

NX_PLL_L (NG-LARGE)

Description

Generics

Ports

Instantiation Example

Simulation

NX_WFG (NG-MEDIUM)

Description

Generics

Ports

Example

Simulation

NX_WFG_L (NG-LARGE)

Description

Generics

Ports

Example

imulation

Core logic

NX_CY (!)

Description

Generics

Ports

Example

NX_LUT

Description

Generics

Ports

Example

NX_DFF

Description

Generics

Ports

Example

NX_RFB

Description

Generics

Ports

Instantiation Example

NX_DSP (NG-MEDIUM)

Description

Generics

Ports

Instantiation Example

Simulation

NX_DSP_SPLIT

NX_DSP_L (NG-LARGE)

Description

Generics

Ports

Instantiation Example

Simulation

NX_DSP_L_SPLIT

NX_ECC

Description

Ports