Table of Contents |
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Important information
This document applies exclusively to the configuration of the NG-LARGE FPGA referenced NX1H140TSP.
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WARNING: changing MODE value while RST_HARD_N is unasserted is strictly forbidden.
Bitstream size
This NX1H140TSP bitstream size depends on the amount of logic resources used by the application, the number of initialized Flip-flops and the number of user Core RAM and Core Register Files to be initialized.
Maximum user logic configuration (100%) | 24.43Mb |
Medium configuration (70%) | 17.10Mb |
Small configuration (50%) | 12.22Mb |
D-Flip-Flop initialization (1) (129024) | 1b/D-Flip-Flop |
Core RAM initialization (2) (192 instances) | 96.06Kb/RAM block |
Core Register File initialization (2) (672 instances) | 3.03Kb/Register File |
CMIC | 64.15Kb |
Total | 44.53Mb |
In a typical design the user can give – or not - an initial value to Flip-Flops at power-up. Reducing the number of initialized Flip-Flops contributes to reduce the bitstream size.
Core RAM and/or Core Register file can also be initialized – or not - at power-up. Reducing the number of initialized memories contributes to reduce the bitstream size.
Most applications do not require to initialize all memories.
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c. Repair flipped bit
d. Write DATA[BAD @]
In case of error that cannot be corrected, for instance double error, the data is blacklisted in order to not generate definitive TRIGGER/ERROR high level.
For further information, please refer to the NX1H140TSP CMIC Application note.
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RST_HARD_N is a dedicated input pin that allows to reset the configuration engine, and launches the configuration process after RST_HARD_N is released. (It can’t be used to reset the FPGA user’s logic).
MODE [2:0] | Configuration mode |
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000 0x0 | Master Serial SPI |
001 0x1 | Master Serial SPI with VCC control |
010 0x2 | Slave Spacewire |
011 0x3 | JTAG (reserved) |
100 0x4 | Slave Parallel 8-bit |
101 0x5 | Slave Parallel 16-bit |
110 0x6 | Reserved |
111 0x7 | Test mode |
Table: NG-LARGE NX1H140TSP configuration modes
Configuration modes usage
JTAG configuration channel is always active regardless the selected configuration mode. JTAG accesses while the configuration interface is active are not recommended (risk of conflict with the bitstream manager operation and render ineffective the bitstream manager)
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Multiple devices addressing
Thanks to Device ID feature in the Bitstream Manager, it is possible to connect multiple devices on the same bus and load a bitstream only to the desired device.
In broadcast mode (0xFF), all connected devices will load the bitstream in the configuration memory.
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Bitstream Device ID is set during bitstream generation. It is 8 bits large.
Chip Device ID is set by external pins. It is only 4 bits large.
Configuration modes usage
JTAG configuration channel is always active regardless the selected configuration mode. JTAG accesses while the configuration interface is active are not recommended (risk of conflict with the bitstream manager operation and render ineffective the bitstream manager)
In slave modes (SpaceWire, Slave Parallel 8 or Slave Parallel 16), NX1H140TSP chip must be fed its bitstream through the selected interface.
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The next table summarizes the list of pins that can be affected during the configuration process.
Grp | Name | I/O | Description |
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GLOBAL | MODE(2:0) | I | Input pins sampled at power-up. MODE(2:0). They define the configuration mode to be used for NG-LARGE configuration. MODE(2:0) cannot be changed when RST_HARD_N = ‘1’ |
ID(3:0) | I | Device Identification. It must comply with the bitstream device id to allow access bitstream loading. | |
FABRIC_USER(3:0) | I | Additional IO for user. FABRIC_USER[0] can be connected to low-skew network. | |
CLK | I | Always required. Can be routed externally to CLK_OSC 100MHz internal oscillator (except in Master SPI modes) or to an external clock in the range [0MHz;100MHz]. | |
RST_HARD_N | I | Mandatory input. When low, it resets the internal configuration engine. RST_HARD_N must be low at least during 3 microseconds to ensure a proper configuration engine reset. When RST_HARD_N goes high, the configuration starts after up to 3 additional microseconds. | |
RST_SOFT_N | I | It only resets internal configuration registers but does not apply a reset on the configuration memory. | |
READY | O | Goes high when the configuration is complete (the FPGA enters in user’s mode) | |
TRIGGER | O | Generates a high-level pulse (~20 ns or one CLK cycle) each time an error is encountered during the configuration and during design processing. Error is taken into account only if it is not masked by the associated TRIGGER_MASK. | |
ERROR | O | Generates a high-level pulse (~20 ns or one CLK cycle) each time an error is encountered during the configuration and during design processing. Error is taken into account only if it is not masked by the associated ERROR_MASK. | |
POK | O | Goes high when VDD1V2 Core and VDD2VA VDD2V5A Analog Supply are on. | |
Slave Parallel 16/8 | CS | I | Active high Chip Select input. Used in Slave Parallel 16/8 mode. The master can write or read to/from the configuration engine when CS is high during a CLK rising edge. |
TYPE[1:0] | I | 2-bits control input. Used in Slave Parallel 16/8 mode. It indicates the type of access: 0b00: ADDR_DEBUG 0b01: READ_DEBUG 0b10: WRITE_DEBUG 0b11: WRITE_CONF | |
DATA_OE | O | Active high output. Used in Slave Parallel 16/8 mode. It is a data valid signal for reading operations. | |
D(15 :0) | I/O | 16-bit data bus used in Slave Parallel 16/8 mode to write the bitstream and/or read internal NG-LARGE internal state values. In case of Slave Parallel 8, only the first 8 LSB are used. | |
Master Serial SPI | D(8) | O | Used in Master Serial SPI and Master Serial SPI with Vcc control, as CS output to the external SPI Flash memory. |
D(9) | O | Used in Master Serial SPI and Master Serial SPI with Vcc control, as clock output to the external SPI Flash memory. | |
D(10) | I | Used in Master Serial SPI and Master Serial SPI with Vcc control, as data input (MISO) from the external SPI Flash memory. | |
D(11) | O | Used in Master Serial SPI and Master Serial SPI with Vcc control, as data output (MOSI) to the external SPI Flash memory (while writing a new bitstream into the SPI Flash. | |
D(12) | I | Configured as input (with internal Pull-Up) during the configuration. Can be configured as, user’s I/O available after completing the configuration. | |
D(13) | I/O | Configured as input (with internal PullPup) during the configuration in Master Serial SPI Configured as high level output during the configuration in Master Serial SPI with Vcc control. Can be configured as user I/O available after completing the configuration. | |
D(14) | I/O | ||
D(15) | I/O | ||
SpaceWire | DIN_P | I | SpaceWire interface is available after completing the configuration in Master Serial SPI, Master Serial SPI with Vcc control or Slave Parallel 8 o 16-bit modes. If SpaceWire is used for the configuration, it can’t be used for other purpose than the configuration. |
DIN_N | I | ||
SIN_P | I | ||
SIN_N | I | ||
DOUT_P | O | ||
DOUT_N | O | ||
SOUT_P | O | ||
SOUT_N | O | ||
JTAG | TCK | I | JTAG CLK |
TMS | I | JTAG TMS | |
TDI | I | JTAG TDI | |
TRST_HARD_N | I | JTAG TRST_HARD_N | |
TDO | O | JTAG TDO | |
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Prog bank (INTERFACE) pins used and/or impacted by configuration
Group | Pin name | I, O or I/O | User I/O | During configuration | |||||
Required | Impacted | Pin behavior | |||||||
GLOBAL | MODE(2:0) | I | No | Yes | 000 | Input pins sampled at power-up. MODE(2:0). They define the configuration mode to be used for NG-LARGE configuration. MODE(2:0) cannot be changed when RST_HARD_N = ‘1’ | |||
ID(3:0) | I | No | Yes | - | Device Identification. It must comply with the bitstream device id to allow access bitstream loading or the bitstream device id e equal to 0xF (broadcast mode). | ||||
FABRIC_USER(3:0) | I | Yes | No | - | Additional IO for user. FABRIC_USER[0] can be connected to low-skew network. | ||||
CLK | I | No | Yes | - | Always required. Must be routed to an external clock in the range [0MHz;100MHz]. | ||||
RST_HARD_N | I | No | Yes | - | Mandatory input. When low, it resets the internal configuration engine. RST_HARD_N must be low at least during 3 microseconds to ensure a proper configuration engine reset. When RST_HARD_N goes high, the configuration starts after up to 3 additional microseconds. | ||||
RST_SOFT_N | I | No | No | - | It only resets internal configuration registers but does not apply a reset on the configuration memory. | ||||
READY | O | No | No | Yes | Goes high when the configuration is complete (the FPGA enters in user’s mode) | ||||
TRIGGER | O | No | No | Yes | Generates a high-level pulse (~20 ns or one CLK cycle) each time an error is encountered during the configuration and during design processing. Error is taken into account only if it is not masked by the associated TRIGGER_MASK. | ||||
ERROR | O | No | No | Yes | Generates a high-level pulse (~20 ns or one CLK cycle) each time an error is encountered during the configuration and during design processing. Error is taken into account only if it is not masked by the associated ERROR_MASK. | ||||
POK | O | No | No | No | Goes high when VDD1V2 Core and VDD2VA VDD2V5A Analog Supply are on. | ||||
Slave Parallel 8 | CS | I | No | No | Yes | Unused but unavailable. Must be left unconnected | |||
TYPE[1:0] | I | No | No | Yes | Unused but unavailable. Must be left unconnected | ||||
DATA_OE | O | No | No | Yes | Unused but unavailable. Must be left unconnected | ||||
D(7:0) | I | No | No | Yes | Unused but unavailable. Must be left unconnected | ||||
Slave par ext | D(8) | O | No | Yes | - | External memory Chip Select (active Low)Requires a diode + Pull-Up (see diagram) When the bitstream download is completed this pin is driven to ‘1’ | |||
D(9) | O | No | Yes | - | External bitstream memory Clock When the bitstream download is completed this pin is driven to ‘0’ | ||||
D(10) | I | No | Yes | - | MISO (data in from external memory) | ||||
D(11) | O | No | Yes | - | MOSI (data out to external memory) When the bitstream download is completed this pin is driven to ‘0’ | ||||
D(12) | I | Yes | No | No | Available as User’s I/O | ||||
D(13) | I/O | Yes | No | No | Available as User’s I/O | ||||
D(14) | I/O | Yes | No | No | Available as User’s I/O | ||||
D(15) | I/O | Yes | No | No | Available as User’s I/O | ||||
SPACEWIRE | DIN_P | I | Yes(*) | No | No | When Master Serial SPI is selected the SpaceWire internal IP can be used after completing the configuration (*) The SpaceWire internal IP is available for the user’s application. | |||
DIN_N | I | Yes(*) | No | No | |||||
SIN_P | I | Yes(*) | No | No | |||||
SIN_N | I | Yes(*) | No | No | |||||
DOUT_P | O | Yes(*) | No | No | |||||
DOUT_N | O | Yes(*) | No | No | |||||
SOUT_P | O | Yes(*) | No | No | |||||
SOUT_N | O | Yes(*) | No | No | |||||
JTAG | TCK | I | No | No | No | JTAG is available in all modes. Don’t use it while configuration is in progress. | |||
TMS | I | No | No | No | |||||
TDI | I | No | No | No | |||||
TRST_HARD_N | I | No | No | No | |||||
TDO | O | No | No | No | |||||
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Prog bank (INTERFACE) pins used and/or impacted by configuration
Group | Pin name | I, O or I/O | User I/O | During configuration | |||||
Required | Impacted | Pin behavior | |||||||
GLOBAL | MODE(2:0) | I | No | Yes | 001 | Input pins sampled at power-up. MODE(2:0). They define the configuration mode to be used for NG-LARGE configuration. MODE(2:0) cannot be changed when RST_HARD_N = ‘1’ | |||
ID(3:0) | I | No | Yes | - | Device Identification. It must comply with the bitstream device id to allow access bitstream loading. | ||||
FABRIC_USER(3:0) | I | Yes | No | - | Additional IO for user. FABRIC_USER[0] can be connected to low-skew network. | ||||
CLK | I | No | Yes | - | Always required. Must be routed to an external clock in the range [0MHz;100MHz]. | ||||
RST_HARD_N | I | No | Yes | - | Mandatory input. When low, it resets the internal configuration engine. RST_HARD_N must be low at least during 3 microseconds to ensure a proper configuration engine reset. When RST_HARD_N goes high, the configuration starts after up to 3 additional microseconds. | ||||
RST_SOFT_N | I | No | No | - | It only resets internal configuration registers but does not apply a reset on the configuration memory. | ||||
READY | O | No | No | Yes | Goes high when the configuration is complete (the FPGA enters in user’s mode) | ||||
TRIGGER | O | No | No | Yes | Generates a high-level pulse (~20 ns or one CLK cycle) each time an error is encountered during the configuration and during design processing. Error is taken into account only if it is not masked by the associated TRIGGER_MASK. | ||||
ERROR | O | No | No | Yes | Generates a high-level pulse (~20 ns or one CLK cycle) each time an error is encountered during the configuration and during design processing. Error is taken into account only if it is not masked by the associated ERROR_MASK. | ||||
POK | O | No | No | No | Goes high when VDD1V2 Core and VDD2VA VDD2V5A Analog Supply are on. | ||||
Slave Parallel | CS | I | No | No | Yes | Unused but unavailable. Must be left unconnected | |||
TYPE[1:0] | I | No | No | Yes | Unused but unavailable. Must be left unconnected | ||||
DATA_OE | O | No | No | Yes | Unused but unavailable. Must be left unconnected | ||||
D(7:0) | I | No | No | Yes | Unused but unavailable. Must be left unconnected | ||||
Slave Par ext | D(8) | O | No | Yes | - | External memory Chip Select (active Low) Requires a diode + Pull-Up (see diagram) When the bitstream download is completed, this pin is driven to ‘1’ | |||
D(9) | O | No | Yes | - | External bitstream memory Clock When the bitstream download is completed, this pin is driven to ‘0’ | ||||
D(10) | I | No | Yes | - | MISO (data in from external memory) | ||||
D(11) | O | No | Yes | -- | MOSI (data out to external memory) When the bitstream download is completed, this pin is driven to ‘0’ | ||||
D(12) | I | Yes | No | No | Available as User’s I/O | ||||
D(13) | I/O | Yes | Yes | - | To Vcc SPI Flash memory When the bitstream download is completed, this pin is driven to ‘0’ | ||||
D(14) | I/O | Yes | Yes | - | To Vcc SPI Flash memory When the bitstream download is completed, this pin is driven to ‘0’ | ||||
D(15) | I/O | Yes | Yes | - | To Vcc SPI Flash memory When the bitstream download is completed, this pin is driven to ‘0’ | ||||
SPACEWIRE | DIN_P | I | Yes(*) | No | No | When Master Serial SPI with Vcc Control is selected the SpaceWire internal IP can be used after completing the configuration (*) The SpaceWire internal IP is available for the user’s application. | |||
DIN_N | I | Yes(*) | No | No | |||||
SIN_P | I | Yes(*) | No | No | |||||
SIN_N | I | Yes(*) | No | No | |||||
DOUT_P | O | Yes(*) | No | No | |||||
DOUT_N | O | Yes(*) | No | No | |||||
SOUT_P | O | Yes(*) | No | No | |||||
SOUT_N | O | Yes(*) | No | No | |||||
JTAG | TCK | I | No | No | No | JTAG is available in all modes. Don’t use it while configuration is in progress. | |||
TMS | I | No | No | No | |||||
TDI | I | No | No | No | |||||
TRST_HARD_N | I | No | No | No | |||||
TDO | O | No | No | No | |||||
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Prog bank (INTERFACE) pins used and/or impacted by configuration
Group | Pin name | I, O or I/O | User I/O | During configuration | |||||
Required | Impacted | Pin behavior | |||||||
GLOBAL | MODE(2:0) | I | No | Yes | 010 | Input pins sampled at power-up. MODE(2:0). They define the configuration mode to be used for NG-LARGE configuration. MODE(2:0) cannot be changed when RST_HARD_N = ‘1’ | |||
ID(3:0) | I | No | Yes | - | Device Identification. It must comply with the bitstream device id to allow access bitstream loading. | ||||
FABRIC_USER(3:0) | I | Yes | No | - | Additional IO for user. FABRIC_USER[0] can be connected to low-skew network. | ||||
CLK | I | No | Yes | - | Always required. Can be routed externally to CLK_OSC 100MHz internal oscillator or to an external clock in the range [0MHz;100MHz]. | ||||
RST_HARD_N | I | No | Yes | - | Mandatory input. When low, it resets the internal configuration engine. RST_HARD_N must be low at least during 3 microseconds to ensure a proper configuration engine reset. When RST_HARD_N goes high, the configuration starts after up to 3 additional microseconds. | ||||
RST_SOFT_N | I | No | No | - | It only resets internal configuration registers but does not apply a reset on the configuration memory. | ||||
READY | O | No | No | Yes | Goes high when the configuration is complete (the FPGA enters in user’s mode) | ||||
TRIGGER | O | No | No | Yes | Generates a high-level pulse (~20 ns or one CLK cycle) each time an error is encountered during the configuration and during design processing. Error is taken into account only if it is not masked by the associated TRIGGER_MASK. | ||||
ERROR | O | No | No | Yes | Generates a high-level pulse (~20 ns or one CLK cycle) each time an error is encountered during the configuration and during design processing. Error is taken into account only if it is not masked by the associated ERROR_MASK. | ||||
POK | O | No | No | No | Goes high when VDD1V2 Core and VDD2VA VDD2V5A Analog Supply are on. | ||||
Slave Parallel | CS | I | No | No | Yes | Unused but unavailable. Must be left unconnected | |||
TYPE[1:0] | I | No | No | Yes | Unused but unavailable. Must be left unconnected | ||||
DATA_OE | O | No | No | Yes | Unused but unavailable. Must be left unconnected | ||||
D(7:0) | I | No | No | Yes | Unused but unavailable. Must be left unconnected | ||||
Slave Par ext | D(8) | O | No | No | - | Available as User’s I/O | |||
D(9) | O | No | No | - | Available as User’s I/O | ||||
D(10) | I | No | No | - | Available as User’s I/O | ||||
D(11) | O | No | No | - | Available as User’s I/O | ||||
D(12) | I | Yes | No | No | Available as User’s I/O | ||||
D(13) | I/O | Yes | No | - | Available as User’s I/O | ||||
D(14) | I/O | Yes | No | - | Available as User’s I/O | ||||
D(15) | I/O | Yes | No | - | Available as User’s I/O | ||||
SPACEWIRE | DIN_P | I | No | Yes | - | When Slave SpaceWire configuration mode is selected, the SpaceWire IP remains dedicated to configuration monitoring functions. | |||
DIN_N | I | No | Yes | - | |||||
SIN_P | I | No | Yes | - | |||||
SIN_N | I | No | Yes | - | |||||
DOUT_P | O | No | Yes | - | |||||
DOUT_N | O | No | Yes | - | |||||
SOUT_P | O | No | Yes | - | |||||
SOUT_N | O | No | Yes | - | |||||
JTAG | TCK | I | No | No | No | JTAG is available in all modes. Don’t use it while configuration is in progress. | |||
TMS | I | No | No | No | |||||
TDI | I | No | No | No | |||||
TRST_HARD_N | I | No | No | No | |||||
TDO | O | No | No | No | |||||
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Strobe and Data input signals must comply with the following figure focusing on input capacitors and resistors:
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Capacitors are needed in case of signals come from another board not connected to the same ground.
Resistors are needed to center the signal around VDDIO_SPW/2.
Spacewire configuration instructions
The supported SPW instructions by the NG-LARGE FPGA are as stated in the table below.
Command Code | Command |
0x01 | ADDR_DEBUG |
0x02 | READ_DEBUG |
0x04 | WRITE_DEBUG |
0x08 | WRITE_CONF |
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Prog bank (INTERFACE) pins used and/or impacted by configuration
Group | Pin name | I, O or I/O | User I/O | During configuration | |||||
Required | Impacted | Pin behavior | |||||||
GLOBAL | MODE(2:0) | I | No | Yes | PAR8: 100 PAR16: 101 | Input pins sampled at power-up. MODE(2:0). They define the configuration mode to be used for NG-LARGE configuration. MODE(2:0) cannot be changed when RST_HARD_N = ‘1’ | |||
ID(3:0) | I | No | Yes | - | Device Identification. It must comply with the bitstream device id to allow access bitstream loading. | ||||
FABRIC_USER(3:0) | I | Yes | No | - | Additional IO for user. FABRIC_USER[0] can be connected to low-skew network. | ||||
CLK | I | No | Yes | - | Always required. Can be routed externally to CLK_OSC 100MHz internal oscillator or to an external clock in the range [0MHz;100MHz]. | ||||
RST_HARD_N | I | No | Yes | - | Mandatory input. When low, it resets the internal configuration engine. RST_HARD_N must be low at least during 3 microseconds to ensure a proper configuration engine reset. When RST_HARD_N goes high, the configuration starts after up to 3 additional microseconds. | ||||
RST_SOFT_N | I | No | No | - | It only resets internal configuration registers but does not apply a reset on the configuration memory. | ||||
READY | O | No | No | Yes | Goes high when the configuration is complete (the FPGA enters in user’s mode) | ||||
TRIGGER | O | No | No | Yes | Generates a high-level pulse (~20 ns or one CLK cycle) each time an error is encountered during the configuration and during design processing. Error is taken into account only if it is not masked by the associated TRIGGER_MASK. | ||||
ERROR | O | No | No | Yes | Generates a high-level pulse (~20 ns or one CLK cycle) each time an error is encountered during the configuration and during design processing. Error is taken into account only if it is not masked by the associated ERROR_MASK. | ||||
POK | O | No | No | No | Goes high when VDD1V2 Core and VDD2VA VDD2V5A Analog Supply are on. | ||||
Slave Parallel | CS | I | No | Yes | - | Active high Chip Select input | |||
TYPE[1:0] | I | No | Yes | - | 2-bits control input. It indicates the type of access: 0b00: ADDR_DEBUG 0b01: READ_DEBUG 0b10: WRITE_DEBUG 0b11: WRITE_CONF | ||||
DATA_OE | O | No | Yes | - | Active high output. It is a data valid signal for reading operations. | ||||
D(7 :0) | I/O | No | Yes | - | 8-bit data bus (input during the configuration) | ||||
Slave Par ext | D(8) | I/O | Yes | No | No | Slave Parallel 8 : Available as User’s I/O Slave Parallel 16 : | |||
D(9) | I/O | Yes | No | No | |||||
D(10) | I/O | Yes | No | No | |||||
D(11) | I/O | Yes | No | No | |||||
D(12) | I/O | Yes | No | No | |||||
D(13) | I/O | Yes | No | No | |||||
D(14) | I/O | Yes | No | No | |||||
D(15) | I/O | Yes | No | No | |||||
SPACEWIRE | DIN_P | I | Yes(*) | No | No | When Slave Parallel 8 is selected the SpaceWire internal IP can be used after completing the configuration (*) The SpaceWire internal IP is available for the user’s application. | |||
DIN_N | I | Yes(*) | No | No | |||||
SIN_P | I | Yes(*) | No | No | |||||
SIN_N | I | Yes(*) | No | No | |||||
DOUT_P | O | Yes(*) | No | No | |||||
DOUT_N | O | Yes(*) | No | No | |||||
SOUT_P | O | Yes(*) | No | No | |||||
SOUT_N | O | Yes(*) | No | No | |||||
JTAG | TCK | I | No | No | No | JTAG is available in all modes. Don’t use it during configuration | |||
TMS | I | No | No | No | |||||
TDI | I | No | No | No | |||||
TRST_HARD_N | I | No | No | No | |||||
TDO | O | No | No | No | |||||
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The following signals can be used by the fabric and consequently get an impact in the design if needed by users:
Grp | Name | I/O | Description |
---|---|---|---|
GLOBAL | CLK_BSM | I | Always required. Can be routed externally to CLK_OSC 100MHz internal oscillator or to an external clock in the range [0MHz;100MHz]. |
COLD_START | I | Goes high if the FPGA is ready and not reboot because of error occurred. | |
READY | I | Goes high when the configuration is complete (the FPGA enters in user’s mode) | |
TRIGGER | I | Generates a high-level pulse (~20 ns or one CLK cycle) each time an error is encountered during the configuration and during design processing. Error is taken into account only if it is not masked by the associated TRIGGER_MASK. | |
ERROR | I | Generates a high-level pulse (~20 ns or one CLK cycle) each time an error is encountered during the configuration and during design processing. Error is taken into account only if it is not masked by the associated ERROR_MASK. |
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The difference is Bitstream Manager registers write/read accesses are made from the fabric and give the ability to use these control and status registers in the design.
Grp | Name | I/O | Description |
---|---|---|---|
Parallel User | CS | O | Description is the same than Slave Parallel 8 except that for this interface, commands are sent from the fabric. DVAL is equivalent to DATA_OE. |
TYPE[1:0] | O | ||
DI[7:0] | O | ||
DVAL | I | ||
DO[7:0] | I | ||
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NX1H140TSP chips boundary scan instructions are the following:
Hex | Instruction | Function |
---|---|---|
0x0 | EXTEST | Boundary scan external test |
0x1 | SAMPLE | Boundary scan sample |
0x1 | PRELOAD | Boundary scan preload |
0x2 | WR_CONF | Nanoxplore bitstream download |
0x3 | WR_DEBUG | Write debug instruction |
0x4 | RD_DEBUG | Read debug instruction |
0x5 | ADDR_DEBUG | Address debug instruction |
0x6 | INTEST | Boundary scan in internal test |
0x7 | IDCODE | Boundary scan design identification |
0x8 | USRCODE | User design identification register |
0x9 | USER1 | User registers access |
0xA | USER2 | User registers access |
0xC | HIGHZ | Tri-state all device I/Os |
0xF | BYPASS | Single-clock bypass TDI to TDO |
...
In order to write or read a Bitstream Manager register, it needs a ADDR_DEBUG command followed by respectively a WR_DEBUG or RD_DEBUG command. The address is 32 bits long and data are 96 bits long.
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NX1H140TSP boundary scan usage
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Dedicated clock inputs on the COMPLEX banks (2, 5, 9 and 12) are fully functional in boundary scan INTEST.
NG_LARGE register
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ANGIE JTAG adaptator
In order to debug a component, it can be very useful to use ANGIE adaptor and NxBase2 software.
An EEPROM is recommended in order to work in non-OEM mode. In this way, the board will be automatically recognized by the software.
Please refer to NxBase2 User Manual documentation in ANGIE chapter.
NG_LARGE registers
To access a register, the user needs to use the ADDR_DEBUG instruction first, and then the WR_DEBUG or RD_DEBUG instructionsDEBUG instructions.
NG-LARGE is divided in 9 rows with the following set of registers for each row. When addressing a register, address is 32 bits long with the following mapping:
Address | Mapping |
---|---|
[31:16] | Address of the row. 0xff indicates a broadcast mode addressing all rows in the same time. |
[15:0] | Address of register for the corresponding row. |
When generating a bitstream, default values are sent for all registers but it is possible to change these values inside the bitstream. Refer to initRegister NXmap method.
Note all NG-MEDIUM registers are kept in NG-LARGE and get the same addresses.
Address | Register Name | R/W | Description |
---|---|---|---|
0x00 | STATUS | R | Status register |
0x0b | JTAG_IDCODE | R | JTAG identification code |
0x0c | JTAG_USERCODE | RW | JTAG user code |
0x0d | SPI_CTRL | RW | SPI configuration |
0x0e | ERROR1 | R | Error Flags |
0x0f | ERROR1_MASK | RW | Error Mask |
0x10 | ERROR2 | R | Error Flags |
0x11 | ERROR2_MASK | RW | Error Mask |
0x12 | EVENT_CNT1 | R | Event Counter 1 |
0x13 | EVENT_CNT2 | R | Event Counter 2 |
0x14 | MAX_ERROR_CNT | RW | Error counter |
0x15 | DEVICE_ID | R | FPGA Device ID |
0x1a | THSENS_CTRL | RW | Thermal Sensor Configuration |
0x1b | THSENS_DATA | R | Thermal Sensor Data |
0x1c | DUMP_CTRL | RW | DUMP configuration |
0x1d | SPW_CTRL1 | RW | SpaceWire Configuration |
0x1e | SPW_CTRL2 | RW | SpaceWire Configuration |
0x1f | LOADER_CTRL | RW | Loader Controller |
0x22 | ERROR3 | R | Error Flags |
0x23 | ERROR3_MASK | RW | Error Mask |
0x24 | TRIGGER1_MASK | RW | Trigger Mask |
0x25 | TRIGGER2_MASK | RW | Trigger Mask |
0x26 | TRIGGER3_MASK | RW | Trigger Mask |
0x27 | DRIVER_FORCE | RW | Driver Force |
0x28 | PARUSR_CTRL | RW | Parallel User Configuration |
0x29 | PAREXT_CTRL | RW | Parallel External Configuration |
0x2a | SPI_TIMING | RW | SPI Timing |
0x2b | SPI_ADDR | RW | SPI Address |
0x2c | BSM_CTRL | RW | Bitstream Manager Control |
STATUS
Name | Address | Access | Reset Value | Description |
---|---|---|---|---|
STATUS | 0x00 | Read-only | 0x0000 | Status register |
Bits | Field name | Rst | Description |
---|---|---|---|
[18] | flag_ready | 0x0 | 1 when ready is rise |
[17] | had_trigger | 0x0 | 1 when ERRORx contents flags errors (with application of mask vector) |
[16] | status_driver_cmb_bit | 0x0 | 1 when the driver compare bit is set |
[15] | had_error_unmasked | 0x0 | 1 when ERRORx contents flags errors (without application of mask vector) |
[14] | had_error | 0x0 | 1 when ERRORx contents flags errors (with application of mask vector) |
[13] | status_cmic_run | 0x0 | 1 when CMIC is running |
[5] | status_max_error | 0x0 | 1 when the Max Error is reach |
[4] | status_error | 0x0 | 1 when the Error Flag is rise |
[3] | status_download | 0x0 | 1 when the loader downloads a bitstream |
[2] | status_prog | 0x0 | 1 when the Programmation Flag is rise |
[1] | status_cold_start | 0x0 | 1 when the Ready Flag is first run |
[0] | status_ready | 0x0 | 1 when the Ready Flag is rise |
JTAG_IDCODE
Name | Address | Access | Reset Value | Description |
JTAG_IDCODE | 0x0b | Read-only | 0x00000675 | JTAG identification code |
Bits | Field name | Rst | Description |
[31:28] | jtag_idcode_version | 0x0 | Version number |
[27:12] | jtag_idcode_part | 0x0000 | Part number |
[11:1] | jtag_idcode_manufacturer | 0x33a | Manufacturer ID: 11:8 (4bits) bank, 7:1 (7bits) manufacturer id |
[0] | jtag_idcode_one | 0x1 | Constant Always 1 |
JTAG_USERCODE
Name | Address | Access | Reset Value | Description |
JTAG_USERCODE | 0x0c | Read-write | 0xffffffff | JTAG user code |
Bits | Field name | Rst | Description |
---|---|---|---|
[31:0] | jtag_usercode | 0xffffffff | JTAG user code |
SPI_CTRL
Name | Address | Access | Reset Value | Description |
---|---|---|---|---|
SPI_CTRL | 0x0d | Read-write | 0x0038 | SPI configuration |
Bits | Field name | Rst | Description |
[18] | spi_restart | 0x0 | SPI disable for 1 cycle when this bit go to 1 (just 1 cycle) |
[17] | spi_disable | 0x0 | SPI interface is disabled (if disable, then always reset) |
[16] | spi_address_size | 0x0 | SPI Address Size (0 : 24, 1 : 32) |
[14:12] | spi_dummy_cycle | 0x0 | Number of Dummy cycle |
[11:4] | spi_read_code | 0x3 | SPI Read Code |
[3:0] | spi_clk_ratio | 0x8 | SPI Clock frequency is divided by spi_clk_ratio+2 (default : 10Mhz) |
ERROR1
Name | Address | Access | Reset Value | Description |
ERROR1 | 0x0e | Read-only | 0x00000000 | Error Flags |
Bits | Field name | Rst | Description |
[31] | flag_error_spi_sel | 0x0 | SPI selection error flag |
[30] | flag_error_parallel_read_access_ovf | 0x0 | Parallel read access overflow |
[29] | flag_error_parallel_write_access_conflict | 0x0 | Parallel write access conflict |
[28] | flag_error_fifo_serializer_full | 0x0 | FIFO of serializer full |
[27] | flag_error_reg_read_unaccepted | 0x0 | Register read access is rejected |
[26] | flag_error_reg_write_unaccepted | 0x0 | Register write access is rejected |
[25] | flag_error_bl_read_unaccepted | 0x0 | Bootloader read is rejected |
[24] | flag_error_cfgctx_read_unaccepted | 0x0 | CFGCTX read is rejected |
[23] | flag_error_cfgctx_write_unaccepted | 0x0 | CFGCTX write is rejected |
[22] | flag_error_clear_unaccepted | 0x0 | Clear command rejected |
[21] | flag_error_bltest_unaccepted | 0x0 | Bootloader test command is rejected |
[20] | flag_error_reg_read_busy | 0x0 | Register read busy error |
[19] | flag_error_reg_write_busy | 0x0 | Register write busy error |
[18] | flag_error_bl_read_busy | 0x0 | Bootloader read busy error |
[17] | flag_error_cfgctx_read_busy | 0x0 | CFGCTX read busy error |
[16] | flag_error_cfgctx_write_busy | 0x0 | CFGCTX write busy error |
[15] | flag_error_clear_busy | 0x0 | Clear busy error |
[14] | flag_error_bltest_busy | 0x0 | Bootloader test busy error |
[13] | flag_error_invalid_address | 0x0 | Address is invalid |
[12] | flag_error_direct_engine_rsp_busy | 0x0 | Direct engine response is busy |
[11] | flag_error_direct_engine_rsp_conflict | 0x0 | Direct engine response in conflict |
[10] | flag_error_direct_engine_req_invalid_loader | 0x0 | Direct engine request signals invalid loader |
[9] | flag_error_access_write_conflict | 0x0 | Write access conflict detected |
[8] | flag_error_frame_engine_edac_uncorrected | 0x0 | Uncorrected error on frame engine's EDAC |
[7] | flag_error_frame_engine_crc_frame | 0x0 | CRC error detected on frame |
[6] | flag_error_frame_engine_crc_bitstream | 0x0 | CRC error detected on bitstream |
[5] | flag_error_frame_engine_watchdog_timeout | 0x0 | Watchdog's timeout is reached |
[4] | flag_error_frame_engine_unexpected_frame | 0x0 | Frame received but not expected |
[3] | flag_error_frame_engine_req_invalid_loader | 0x0 | Invalid loader error detected on frame request |
[2] | flag_error_frame_access_conflict | 0x0 | Access conflict detected on frame |
[1] | flag_error_direct_access_rsp_conflict | 0x0 | Direct access response conflict detected |
[0] | flag_error_direct_access_req_conflict | 0x0 | Direct access request conflict detected |
ERROR1_MASK
Name | Address | Access | Reset Value | Description |
ERROR1_MASK | 0x0f | Read-write | 0x1FFE000 | Error Mask |
Bits | Field name | Rst | Description |
[31:0] | flag_error1_mask | 0x1FFE000 | Error mask register for ERROR1 |
ERROR2
Name | Address | Access | Reset Value | Description |
ERROR2 | 0x10 | Read-only | 0x00000 | Error Flags |
Bits | Field name | Rst | Description | |||
[19] | error_driver_access_conflict | 0x0 | ||||
[18] | error_driver_rsp_parity | 0x0 | ||||
[17] | error_driver_req_parity | 0x0 | ||||
[16] | flag_error_frame_engine_conflict_io_id_bitstream_i | 0x0 | ||||
[15] | flag_error_frame_engine_conflict_io_id_deserializer_i | 0x0 | ||||
[14] | flag_error_frame_access_invalid_io_id_i | 0x0 | ||||
[13] | flag_error_direct_access_rsp_invalid_io_id_i | 0x0 | ||||
[12] | flag_error_direct_access_req_invalid_io_id_i | 0x0 | ||||
[11] | flag_error_parusr_type_conflict_i | 0x0 | Conflict detected on parusr access | |||
[10] | flag_error_parext_type_conflict_i | 0x0 | Conflict detected on parext access | |||
[9] | flag_error_spw_link_broken | 0x0 | SPW link disconnection error detected | |||
[8] | flag_error_spw_err_int | 0x0 | SPW internal error detected | [7_int | 0x0 | SPW internal error detected |
[7] | flag_error_spw_nom_int | 0x0 | SPW NOM error | |||
[6] | flag_error_cmic_max_run | 0x0 | CMIC max run error | |||
[5] | flag_error_cmic_check_uncorrected | 0x0 | CMIC error is uncorrected | |||
[4] | flag_error_cmic_ref_edac_uncorrected | 0x0 | CMIC reference for EDAC is uncorrected | |||
[3] | flag_error_cmic_spwref_nomaddr_intovf | 0x0SPW NOM error | CMIC reference address overflow detected | |||
[62] | flag_error_cmic_maxaccess_runconflict | 0x0CMIC | max run errorConflict detected on CMIC access | |||
[51] | flag_error_cmicspw_checkunexpected_uncorrectedpacket | 0x0CMIC error is uncorrected | Unexpected SPW packet detected | |||
[40] | flag_error_cmic_ref_edac_uncorrected | 0x0 | CMIC reference for EDAC is uncorrected | [3spw_eep | 0x0 | SPW EEP marker detected |
ERROR2_MASK
Name | Address | Access | Reset Value | Description |
ERROR2_MASK | 0x11 | Read-write | 0xe087c | Error Mask |
Bits | Field name | Rst | Description |
---|---|---|---|
[19:0] | flag_ |
0x0
CMIC reference address overflow detected
[2]
flag_error_cmic_access_conflict
0x0
Conflict detected on CMIC access
[1]
flag_error_spw_unexpected_packet
0x0
Unexpected SPW packet detected
[0]
flag_error_spw_eep
0x0
SPW EEP marker detected
...
error2_mask | 0x000E087C | Error mask register for ERROR2 |
EVENT_CNT1
Name | Address | Access | Reset Value | Description |
---|---|---|---|---|
EVENT_CNT1 | 0x12 | Read | 0x0000 | Event counter 1 |
Bits | Field name | rst | Description |
---|---|---|---|
[15:0] | ERROR_CNT | 0x00 | Number of errors since last hardware reset |
EVENT_CNT2
Name | Address | Access | Reset Value | Description |
---|
EVENT_ |
CNT2 |
0x13 | Read |
0xe087c
Error Mask0x00000000 | Event counter 2 |
Bits | Field name |
---|
Rst
Description
rst | Description | ||
---|---|---|---|
[31:24] | CMIC_CHECK_SIGNATURE_CNT | 0x00 | CMIC signature error counter |
[23:16] | CMIC_CHECK_CORRECTED_CNT | 0x00 | CMIC corrected error counter |
[15:8] | CMIC_REF_EDAC_CORRECT_CNT | 0x00 | Reference EDAC corrected error counter |
[7:0] |
flag_error2_mask
0x000E087C
FRAME_ENGINE_EDAC_CORRECT_CNT | 0x00 | Frame engine EDAC corrected error counter |
MAX_ERROR_CNT
Name | Address | Access | Reset Value | Description |
---|---|---|---|---|
MAX_ERROR_CNT | 0x14 | Read-write | 0xf | Error counter |
Bits | Field name | Rst | Description |
---|---|---|---|
[3:0] | MAX_ERROR_CNT | 0xf | Maximum error count permitted before lighting error led |
DEVICE_ID
Name | Address | Access | Reset Value | Description |
---|---|---|---|---|
DEVICE_ID | 0x15 | Read-only | 0x0 | FPGA Device ID |
Bits | Field name | Rst | Description |
---|---|---|---|
[3:0] | device_id | 0x0 | FPGA device id |
THSENS_CTRL
Name | Address | Access | Reset Value | Description |
---|---|---|---|---|
THSENS_CTRL | 0x1a | Read-write | 0x0000 | Thermal Sensor Configuration |
Bits | Field name | Rst | Description |
---|---|---|---|
[15:6] | thsens_clk_ratio | 0x0 | Clock ratio between bitstream manager and thermal sensor Clock frequency is divided by thsens_clk_ratio+2 |
[5:1] | thsens_dcorrect | 0x0 | Digital code to correct |
[0] | thsens_power_up | 0x0 | Thermal Sensor is powered |
THSENS_DATA
Name | Address | Access | Reset Value | Description |
---|---|---|---|---|
THSENS_DATA | 0x1b | Read-only | 0x000 | Thermal Sensor Data |
Bits | Field name | Rst | Description |
---|---|---|---|
[8:2] | thsens_data | 0x0 | Thermal Sensor Ouput |
[1] | thsens_overflow | 0x0 | Overflow of digital |
[0] | thsens_enable | 0x0 | Thermal Sensor is online |
DUMP_CTRL
Name | Address | Access | Reset Value | Description |
---|---|---|---|---|
DUMP_CTRL | 0x1c | Read-write | 0x8 | DUMP configuration |
Bits | Field name | Rst | Description |
---|---|---|---|
[3:0] | dump_clk_ratio | 0x8 | DUMP Clock frequency is divided by dump_clk_ratio+2 |
SPW_CTRL1
Name | Address | Access | Reset Value | Description |
---|---|---|---|---|
SPW_CTRL1 | 0x1d | Read-write | 0x00009 | SpaceWire Configuration |
Bits | Field name | Rst | Description |
---|---|---|---|
[19] | spw_user | 0x0 | In bitstream manager mode : support of USER Packet |
[18:16] | spw_freq_user_ratio | 0x0 | Divider ratio (N+2) |
[15:8] | spw_freq_run | 0x0 | frequency used in run state Clock frequency divided by (spw_freq_run+1) |
[7:0] | spw_freq_init | 0x9 | frequency used in init state Clock frequency divided by (spw_freq_init+1) |
SPW_CTRL2
Name | Address | Access | Reset Value | Description |
---|---|---|---|---|
SPW_CTRL2 | 0x1e | Read-write | 0x28055 | SpaceWire Configuration |
Bits | Field name | Rst | Description |
[17:8] | spw_delay_prg | 0x280 | delay of 6.4 us Number of clock cycles needed for 6.4 us |
[7:0] | spw_DisCntLim | 0x55 | Disconnect time limit (850ns) |
LOADER_CTRL
Name | Address | Access | Reset Value | Description |
---|---|---|---|---|
LOADER_CTRL | 0x01 | Read-write | 0x01 | Loader Controller |
Bits | Field name | Rst | Description |
---|---|---|---|
[6] | cold_start_we_disable | 0x0 | Don't write in cold_start counter |
[5] | ready_init_on_error | 0x0 | Ready is reset on error |
[4] | ready_init_on_rst | 0x0 | Ready is reset on soft rst (always rst on rst_hard) |
[3] | config_force | 0x0 | Force configuration (force bitstream load) |
[2] | ready_force | 0x0 | Force ready flag |
[1] | ready | 0x0 | Set ready flag when postamble frame occurs |
[0] | cmic_enable | 0x1 | CMIC Feature Enable |
ERROR3
Name | Address | Access | Reset Value | Description |
---|---|---|---|---|
ERROR3 | 0x22 | Read-only | 0x00 | Error Flags |
Bits | Field name | Rst | Description |
---|---|---|---|
[3] | flag_error_cmic_check_signature | 0x0 | TBD |
[2] | flag_error_cmic_check_corrected | 0x0 | TBD |
[1] | flag_error_cmic_ref_edac_corrected | 0x0 | TBD |
[0] | flag_error_frame_engine_edac_corrected | 0x0 | TBD |
ERROR3_MASK
Name | Address | Access | Reset Value | Description |
---|---|---|---|---|
ERROR3_MASK | 0x23 | Read-write | 0xf | Error Mask |
Bits | Field name | Rst | Description |
---|---|---|---|
[3:0] | flag_error3_mask | 0xf | Error mask register for ERROR3 |
TRIGGER1_MASK
Name | Address | Access | Reset Value | Description |
---|---|---|---|---|
TRIGGER1_MASK | 0x24 | Read-write | 0x1fffe000 | Trigger Mask |
Bits | Field name | Rst | Description |
---|---|---|---|
[31:0] | flag_trigger1_mask | 0x1fffe000 | Trigger mask register for ERROR1 |
TRIGGER2_MASK
Name | Address | Access | Reset Value | Description |
---|---|---|---|---|
TRIGGER2_MASK | 0x25 | Read-write | 0xe087c | Trigger Mask |
Bits | Field name | Rst | Description |
---|---|---|---|
[31:0] | flag_trigger2_mask | 0xe087c | Trigger mask register for ERROR2 |
TRIGGER3_MASK
Name | Address | Access | Reset Value | Description |
---|---|---|---|---|
TRIGGER3_MASK | 0x26 | Read-write | 0xf | Trigger Mask |
Bits | Field name | Rst | Description |
---|---|---|---|
[3:0] | flag_trigger3_mask | 0xf | Trigger mask register for ERROR3 |
PARUSR_CTRL
Name | Address | Access | Reset Value | Description |
---|---|---|---|---|
PARUSR_CTRL | 0x28 | Read-write | 0x0 | Parallel User Configuration |
Bits | Field name | Rst | Description |
---|---|---|---|
[0] | parusr_enable | 0x0 | Parallel User enable (Under reset if disabled) |
PAREXT_CTRL
Name | Address | Access | Reset Value | Description |
---|---|---|---|---|
PAREXT_CTRL | 0x29 | Read-write | 0x0 | Parallel External Configuration |
Bits | Field name | Rst | Description |
---|---|---|---|
[0] | parext_data_latency | 0x0 | Latency between DATA_OE and DATA. Data is delayed |
SPI_TIMING
Name | Address | Access | Reset Value | Description |
---|---|---|---|---|
SPI_TIMING | 0x2a | Read-write | 0x00650bb8 | SPI Timing |
Bits | Field name | Rst | Description |
---|---|---|---|
[31:16] | spi_powerdown_cycle | 0x0065 | PowerDown duration (needs 10 us) |
[15:0] | spi_powerup_cycle | 0x0bb8 | PowerUp duration (needs 300 us) |
SPI_ADDR
Name | Address | Access | Reset Value | Description |
---|---|---|---|---|
SPI_ADDR | 0x2b | Read-write | 0x00000000 | SPI Address |
Bits | Field name | Rst | Description |
---|---|---|---|
[31:0] | spi_address | 0x0 | SPI access address |
BSM_CTRL
Name | Address | Access | Reset Value | Description |
---|---|---|---|---|
BSM_CTRL | 0x2c | Read-write | 0x10 | BSM Control Code |
Bits | Field name | Rst | Description |
---|---|---|---|
[6:3] | clk_osc_ratio | 0x2 | CLK_OSC is divided by (clk_ratio+2) |
[2:0] | clk_osc_disable | 0x0 | CLK_OSC is disabled |
...