000 0x0

Master Serial SPI

001 0x1

Master Serial SPI with VCC control

010 0x2

Slave Spacewire

011 0x3

JTAG (reserved)

100 0x4

Slave Parallel 8-bit

101 0x5

Slave Parallel 16-bit

110 0x6

Reserved

111 0x7

Test mode

GLOBAL

MODE(2:0)

I

Input pins sampled at power-up. MODE(2:0). They define the configuration mode to be used for NG-LARGE configuration.

MODE(2:0) cannot be changed when RST_HARD_N = ‘1’

ID(3:0)

I

Device Identification. It must comply with the bitstream device id to allow access bitstream loading.

FABRIC_USER(3:0)

I

Additional IO for user. FABRIC_USER[0] can be connected to low-skew network.

CLK

I

Always required. Can be routed externally to CLK_OSC 100MHz internal oscillator (except in Master SPI modes) or to an external clock in the range [0MHz;100MHz].

RST_HARD_N

I

Mandatory input. When low, it resets the internal configuration engine. RST_HARD_N must be low at least during 3 microseconds to ensure a proper configuration engine reset. When RST_HARD_N goes high, the configuration starts after up to 3 additional microseconds.

RST_SOFT_N

I

It only resets internal configuration registers but does not apply a reset on the configuration memory.

READY

O

Goes high when the configuration is complete (the FPGA enters in user’s mode)

TRIGGER

O

Generates a high-level pulse (~20 ns or one CLK cycle) each time an error is encountered during the configuration and during design processing. Error is taken into account only if it is not masked by the associated TRIGGER_MASK.

ERROR

O

Generates a high-level pulse (~20 ns or one CLK cycle) each time an error is encountered during the configuration and during design processing. Error is taken into account only if it is not masked by the associated ERROR_MASK.

POK

O

Goes high when VDD1V2 Core and VDD2VA Analog Supply are on.

Slave Parallel 16/8

CS

I

Active high Chip Select input. Used in Slave Parallel 16/8 mode. The master can write or read to/from the configuration engine when CS is high during a CLK rising edge.

TYPE[1:0]

I

2-bits control input. Used in Slave Parallel 16/8 mode. It indicates the type of access:

0b00: ADDR_DEBUG

0b01: READ_DEBUG

0b10: WRITE_DEBUG

0b11: WRITE_CONF

DATA_OE

O

Active high output. Used in Slave Parallel 16/8 mode. It is a data valid signal for reading operations.

D(15 :0)

I/O

16-bit data bus used in Slave Parallel 16/8 mode to write the bitstream and/or read internal NG-LARGE internal state values. In case of Slave Parallel 8, only the first 8 LSB are used.

Master Serial SPI

D(8)

O

Used in Master Serial SPI and Master Serial SPI with Vcc control, as CS output to the external SPI Flash memory.

D(9)

O

Used in Master Serial SPI and Master Serial SPI with Vcc control, as clock output to the external SPI Flash memory.

D(10)

I

Used in Master Serial SPI and Master Serial SPI with Vcc control, as data input (MISO) from the external SPI Flash memory.

D(11)

O

Used in Master Serial SPI and Master Serial SPI with Vcc control, as data output (MOSI) to the external SPI Flash memory (while writing a new bitstream into the SPI Flash.

D(12)

I

Configured as input (with internal Pull-Up) during the configuration. Can be configured as, user’s I/O available after completing the configuration.

D(13)

I/O

Configured as input (with internal PullPup) during the configuration in Master Serial SPI

Configured as high level output during the configuration in Master Serial SPI with Vcc control.

Can be configured as user I/O available after completing the configuration.

D(14)

I/O

D(15)

I/O

SpaceWire

DIN_P

I

SpaceWire interface is available after completing the configuration in Master Serial SPI, Master Serial SPI with Vcc control or Slave Parallel 8 o 16-bit modes.

If SpaceWire is used for the configuration, it can’t be used for other purpose than the configuration.

DIN_N

I

SIN_P

I

SIN_N

I

DOUT_P

O

DOUT_N

O

SOUT_P

O

SOUT_N

O

JTAG

TCK

I

JTAG CLK

TMS

I

JTAG TMS

TDI

I

JTAG TDI

TRST_HARD_N

I

JTAG TRST_HARD_N

TDO

O

JTAG TDO

Group

Pin name

I, O or I/O

User I/O

During configuration

Required

Impacted

Pin behavior

GLOBAL

MODE(2:0)

I

No

Yes

000

Input pins sampled at power-up. MODE(2:0). They define the configuration mode to be used for NG-LARGE configuration.

MODE(2:0) cannot be changed when RST_HARD_N = ‘1’

ID(3:0)

I

No

Yes

-

Device Identification. It must comply with the bitstream device id to allow access bitstream loading or the bitstream device id e equal to 0xF (broadcast mode).

FABRIC_USER(3:0)

I

Yes

No

-

Additional IO for user. FABRIC_USER[0] can be connected to low-skew network.

CLK

I

No

Yes

-

Always required. Must be routed to an external clock in the range [0MHz;100MHz].

RST_HARD_N

I

No

Yes

-

Mandatory input. When low, it resets the internal configuration engine. RST_HARD_N must be low at least during 3 microseconds to ensure a proper configuration engine reset. When RST_HARD_N goes high, the configuration starts after up to 3 additional microseconds.

RST_SOFT_N

I

No

No

-

It only resets internal configuration registers but does not apply a reset on the configuration memory.

READY

O

No

No

Yes

Goes high when the configuration is complete (the FPGA enters in user’s mode)

TRIGGER

O

No

No

Yes

Generates a high-level pulse (~20 ns or one CLK cycle) each time an error is encountered during the configuration and during design processing. Error is taken into account only if it is not masked by the associated TRIGGER_MASK.

ERROR

O

No

No

Yes

Generates a high-level pulse (~20 ns or one CLK cycle) each time an error is encountered during the configuration and during design processing. Error is taken into account only if it is not masked by the associated ERROR_MASK.

POK

O

No

No

No

Goes high when VDD1V2 Core and VDD2VA Analog Supply are on.

Slave Parallel 8

CS

I

No

No

Yes

Unused but unavailable. Must be left unconnected

TYPE[1:0]

I

No

No

Yes

Unused but unavailable. Must be left unconnected

DATA_OE

O

No

No

Yes

Unused but unavailable. Must be left unconnected

D(7:0)

I

No

No

Yes

Unused but unavailable. Must be left unconnected

Slave par ext

D(8)

O

No

Yes

-

External memory Chip Select (active Low)

Requires a diode + Pull-Up (see diagram)

When the bitstream download is completed this pin is driven to ‘1’

D(9)

O

No

Yes

-

External bitstream memory Clock

When the bitstream download is completed this pin is driven to ‘0’

D(10)

I

No

Yes

-

MISO (data in from external memory)

D(11)

O

No

Yes

-

MOSI (data out to external memory)

When the bitstream download is completed this pin is driven to ‘0’

D(12)

I

Yes

No

No

Available as User’s I/O

D(13)

I/O

Yes

No

No

Available as User’s I/O

D(14)

I/O

Yes

No

No

Available as User’s I/O

D(15)

I/O

Yes

No

No

Available as User’s I/O

SPACEWIRE

DIN_P

I

Yes(*)

No

No

When Master Serial SPI is selected the SpaceWire internal IP can be used after completing the configuration

(*) The SpaceWire internal IP is available for the user’s application.

DIN_N

I

Yes(*)

No

No

SIN_P

I

Yes(*)

No

No

SIN_N

I

Yes(*)

No

No

DOUT_P

O

Yes(*)

No

No

DOUT_N

O

Yes(*)

No

No

SOUT_P

O

Yes(*)

No

No

SOUT_N

O

Yes(*)

No

No

JTAG

TCK

I

No

No

No

JTAG is available in all modes.

Don’t use it while configuration is in progress.

TMS

I

No

No

No

TDI

I

No

No

No

TRST_HARD_N

I

No

No

No

TDO

O

No

No

No

Group

Pin name

I, O or I/O

User I/O

During configuration

Required

Impacted

Pin behavior

GLOBAL

MODE(2:0)

I

No

Yes

001

Input pins sampled at power-up. MODE(2:0). They define the configuration mode to be used for NG-LARGE configuration.

MODE(2:0) cannot be changed when RST_HARD_N = ‘1’

ID(3:0)

I

No

Yes

-

Device Identification. It must comply with the bitstream device id to allow access bitstream loading.

FABRIC_USER(3:0)

I

Yes

No

-

Additional IO for user. FABRIC_USER[0] can be connected to low-skew network.

CLK

I

No

Yes

-

Always required. Must be routed to an external clock in the range [0MHz;100MHz].

RST_HARD_N

I

No

Yes

-

Mandatory input. When low, it resets the internal configuration engine. RST_HARD_N must be low at least during 3 microseconds to ensure a proper configuration engine reset. When RST_HARD_N goes high, the configuration starts after up to 3 additional microseconds.

RST_SOFT_N

I

No

No

-

It only resets internal configuration registers but does not apply a reset on the configuration memory.

READY

O

No

No

Yes

Goes high when the configuration is complete (the FPGA enters in user’s mode)

TRIGGER

O

No

No

Yes

Generates a high-level pulse (~20 ns or one CLK cycle) each time an error is encountered during the configuration and during design processing. Error is taken into account only if it is not masked by the associated TRIGGER_MASK.

ERROR

O

No

No

Yes

Generates a high-level pulse (~20 ns or one CLK cycle) each time an error is encountered during the configuration and during design processing. Error is taken into account only if it is not masked by the associated ERROR_MASK.

POK

O

No

No

No

Goes high when VDD1V2 Core and VDD2VA Analog Supply are on.

Slave Parallel

CS

I

No

No

Yes

Unused but unavailable. Must be left unconnected

TYPE[1:0]

I

No

No

Yes

Unused but unavailable. Must be left unconnected

DATA_OE

O

No

No

Yes

Unused but unavailable. Must be left unconnected

D(7:0)

I

No

No

Yes

Unused but unavailable. Must be left unconnected

Slave Par ext

D(8)

O

No

Yes

-

External memory Chip Select (active Low)

When the bitstream download is completed, this pin is driven to ‘1’

D(9)

O

No

Yes

-

External bitstream memory Clock

When the bitstream download is completed, this pin is driven to ‘0’

D(10)

I

No

Yes

-

MISO (data in from external memory)

D(11)

O

No

Yes

--

MOSI (data out to external memory)

When the bitstream download is completed, this pin is driven to ‘0’

D(12)

I

Yes

No

No

Available as User’s I/O

D(13)

I/O

Yes

Yes

-

To Vcc SPI Flash memory

When the bitstream download is completed, this pin is driven to ‘0’

D(14)

I/O

Yes

Yes

-

To Vcc SPI Flash memory

When the bitstream download is completed, this pin is driven to ‘0’

D(15)

I/O

Yes

Yes

-

To Vcc SPI Flash memory

When the bitstream download is completed, this pin is driven to ‘0’

SPACEWIRE

DIN_P

I

Yes(*)

No

No

When Master Serial SPI with Vcc Control is selected the SpaceWire internal IP can be used after completing the configuration

(*) The SpaceWire internal IP is available for the user’s application.

DIN_N

I

Yes(*)

No

No

SIN_P

I

Yes(*)

No

No

SIN_N

I

Yes(*)

No

No

DOUT_P

O

Yes(*)

No

No

DOUT_N

O

Yes(*)

No

No

SOUT_P

O

Yes(*)

No

No

SOUT_N

O

Yes(*)

No

No

JTAG

TCK

I

No

No

No

JTAG is available in all modes. Don’t use it while configuration is in progress.

TMS

I

No

No

No

TDI

I

No

No

No

TRST_HARD_N

I

No

No

No

TDO

O

No

No

No

Group

Pin name

I, O or I/O

User I/O

During configuration

Required

Impacted

Pin behavior

GLOBAL

MODE(2:0)

I

No

Yes

010

Input pins sampled at power-up. MODE(2:0). They define the configuration mode to be used for NG-LARGE configuration.

MODE(2:0) cannot be changed when RST_HARD_N = ‘1’

ID(3:0)

I

No

Yes

-

Device Identification. It must comply with the bitstream device id to allow access bitstream loading.

FABRIC_USER(3:0)

I

Yes

No

-

Additional IO for user. FABRIC_USER[0] can be connected to low-skew network.

CLK

I

No

Yes

-

Always required. Can be routed externally to CLK_OSC 100MHz internal oscillator or to an external clock in the range [0MHz;100MHz].

RST_HARD_N

I

No

Yes

-

Mandatory input. When low, it resets the internal configuration engine. RST_HARD_N must be low at least during 3 microseconds to ensure a proper configuration engine reset. When RST_HARD_N goes high, the configuration starts after up to 3 additional microseconds.

RST_SOFT_N

I

No

No

-

It only resets internal configuration registers but does not apply a reset on the configuration memory.

READY

O

No

No

Yes

Goes high when the configuration is complete (the FPGA enters in user’s mode)

TRIGGER

O

No

No

Yes

Generates a high-level pulse (~20 ns or one CLK cycle) each time an error is encountered during the configuration and during design processing. Error is taken into account only if it is not masked by the associated TRIGGER_MASK.

ERROR

O

No

No

Yes

Generates a high-level pulse (~20 ns or one CLK cycle) each time an error is encountered during the configuration and during design processing. Error is taken into account only if it is not masked by the associated ERROR_MASK.

POK

O

No

No

No

Goes high when VDD1V2 Core and VDD2VA Analog Supply are on.

Slave Parallel

CS

I

No

No

Yes

Unused but unavailable. Must be left unconnected

TYPE[1:0]

I

No

No

Yes

Unused but unavailable. Must be left unconnected

DATA_OE

O

No

No

Yes

Unused but unavailable. Must be left unconnected

D(7:0)

I

No

No

Yes

Unused but unavailable. Must be left unconnected

Slave Par ext

D(8)

O

No

No

-

Available as User’s I/O

D(9)

O

No

No

-

Available as User’s I/O

D(10)

I

No

No

-

Available as User’s I/O

D(11)

O

No

No

-

Available as User’s I/O

D(12)

I

Yes

No

No

Available as User’s I/O

D(13)

I/O

Yes

No

-

Available as User’s I/O

D(14)

I/O

Yes

No

-

Available as User’s I/O

D(15)

I/O

Yes

No

-

Available as User’s I/O

SPACEWIRE

DIN_P

I

No

Yes

-

When Slave SpaceWire configuration mode is selected, the SpaceWire IP remains dedicated to configuration monitoring functions.

DIN_N

I

No

Yes

-

SIN_P

I

No

Yes

-

SIN_N

I

No

Yes

-

DOUT_P

O

No

Yes

-

DOUT_N

O

No

Yes

-

SOUT_P

O

No

Yes

-

SOUT_N

O

No

Yes

-

JTAG

TCK

I

No

No

No

JTAG is available in all modes. Don’t use it while configuration is in progress.

TMS

I

No

No

No

TDI

I

No

No

No

TRST_HARD_N

I

No

No

No

TDO

O

No

No

No

Command Code

Command

0x01

ADDR_DEBUG

0x02

READ_DEBUG

0x04

WRITE_DEBUG

0x08

WRITE_CONF

Group

Pin name

I, O or I/O

User I/O

During configuration

Required

Impacted

Pin behavior

GLOBAL

MODE(2:0)

I

No

Yes

PAR8: 100

PAR16: 101

Input pins sampled at power-up. MODE(2:0). They define the configuration mode to be used for NG-LARGE configuration.

MODE(2:0) cannot be changed when RST_HARD_N = ‘1’

ID(3:0)

I

No

Yes

-

Device Identification. It must comply with the bitstream device id to allow access bitstream loading.

FABRIC_USER(3:0)

I

Yes

No

-

Additional IO for user. FABRIC_USER[0] can be connected to low-skew network.

CLK

I

No

Yes

-

Always required. Can be routed externally to CLK_OSC 100MHz internal oscillator or to an external clock in the range [0MHz;100MHz].

RST_HARD_N

I

No

Yes

-

Mandatory input. When low, it resets the internal configuration engine. RST_HARD_N must be low at least during 3 microseconds to ensure a proper configuration engine reset. When RST_HARD_N goes high, the configuration starts after up to 3 additional microseconds.

RST_SOFT_N

I

No

No

-

It only resets internal configuration registers but does not apply a reset on the configuration memory.

READY

O

No

No

Yes

Goes high when the configuration is complete (the FPGA enters in user’s mode)

TRIGGER

O

No

No

Yes

Generates a high-level pulse (~20 ns or one CLK cycle) each time an error is encountered during the configuration and during design processing. Error is taken into account only if it is not masked by the associated TRIGGER_MASK.

ERROR

O

No

No

Yes

Generates a high-level pulse (~20 ns or one CLK cycle) each time an error is encountered during the configuration and during design processing. Error is taken into account only if it is not masked by the associated ERROR_MASK.

POK

O

No

No

No

Goes high when VDD1V2 Core and VDD2VA Analog Supply are on.

Slave Parallel

CS

I

No

Yes

-

Active high

Chip Select input

TYPE[1:0]

I

No

Yes

-

2-bits control input. It indicates the type of access:

0b00: ADDR_DEBUG

0b01: READ_DEBUG

0b10: WRITE_DEBUG

0b11: WRITE_CONF

DATA_OE

O

No

Yes

-

Active high output. It is a data valid signal for reading operations.

D(7 :0)

I/O

No

Yes

-

8-bit data bus (input during the configuration)

Slave Par ext

D(8)

I/O

Yes

No

No

Slave Parallel 8 :

Available as User’s I/O

Slave Parallel 16 :

D(9)

I/O

Yes

No

No

D(10)

I/O

Yes

No

No

D(11)

I/O

Yes

No

No

D(12)

I/O

Yes

No

No

D(13)

I/O

Yes

No

No

D(14)

I/O

Yes

No

No

D(15)

I/O

Yes

No

No

SPACEWIRE

DIN_P

I

Yes(*)

No

No

When Slave Parallel 8 is selected the SpaceWire internal IP can be used after completing the configuration

(*) The SpaceWire internal IP is available for the user’s application.

DIN_N

I

Yes(*)

No

No

SIN_P

I

Yes(*)

No

No

SIN_N

I

Yes(*)

No

No

DOUT_P

O

Yes(*)

No

No

DOUT_N

O

Yes(*)

No

No

SOUT_P

O

Yes(*)

No

No

SOUT_N

O

Yes(*)

No

No

JTAG

TCK

I

No

No

No

JTAG is available in all modes.

Don’t use it during configuration

TMS

I

No

No

No

TDI

I

No

No

No

TRST_HARD_N

I

No

No

No

TDO

O

No

No

No

GLOBAL

CLK_BSM

I

Always required. Can be routed externally to CLK_OSC 100MHz internal oscillator or to an external clock in the range [0MHz;100MHz].

COLD_START

I

Goes high if the FPGA is ready and not reboot because of error occurred.

READY

I

Goes high when the configuration is complete (the FPGA enters in user’s mode)

TRIGGER

I

Generates a high-level pulse (~20 ns or one CLK cycle) each time an error is encountered during the configuration and during design processing. Error is taken into account only if it is not masked by the associated TRIGGER_MASK.

ERROR

I

Generates a high-level pulse (~20 ns or one CLK cycle) each time an error is encountered during the configuration and during design processing. Error is taken into account only if it is not masked by the associated ERROR_MASK.

Parallel User

CS

O

Description is the same than Slave Parallel 8 except that for this interface, commands are sent from the fabric.

DVAL is equivalent to DATA_OE.

TYPE[1:0]

O

DI[7:0]

O

DVAL

I

DO[7:0]

I

0x0

EXTEST

Boundary scan external test

0x1

SAMPLE

Boundary scan sample

0x1

PRELOAD

Boundary scan preload

0x2

WR_CONF

Nanoxplore bitstream download

0x3

WR_DEBUG

Write debug instruction

0x4

RD_DEBUG

Read debug instruction

0x5

ADDR_DEBUG

Address debug instruction

0x6

INTEST

Boundary scan in internal test

0x7

IDCODE

Boundary scan design identification

0x8

USRCODE

User design identification register

0x9

USER1

User registers access

0xA

USER2

User registers access

0xC

HIGHZ

Tri-state all device I/Os

0xF

BYPASS

Single-clock bypass TDI to TDO

[6:3]

clk_osc_ratio

0x2

CLK_OSC is divided by (clk_ratio+2)

[2:0]

clk_osc_disable

0x0

CLK_OSC is disabled