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It is recommended to only add the nxpackage in the work library and not component declarations as they are already declared in the package.
Net Network
Basically, there are 2 kind of net networks in NX chips :
Common: Used to connect data like signal, most of the time signals with a low fanout
System: Used to connect clock/reset signal, most of the time signals with a high fanout. This network is composed of 2 sub categories:
Global low-skew network is used to spread signals through the whole fabric with a low skew between all paths
Local low-skew network is used to spread signals through a TILE with a low skew between all paths
There are instances to go from one world to the other one :
CSC: Common to System Converter
SCC : System to Common Converter
Depending on the chip, CSC are implemented in different kind of primitives.
Each instance in the design has:
Pins with net coming from the Common network OR/AND
Pins with net coming from the System network OR/AND
Pins with net coming from either Common network or System network
For example, a NX_DFF has the following pins and associated connected networks:
Pin | Common | System |
CK | No | Yes |
R | Yes | Yes |
L | Yes | Yes |
D | Yes | No |
Q | Yes | No |
| Note |
|---|
|
Clock management
NanoXplore FPGAs contain a low-skew network in order to spread signal with high fanout like clock, reset and load signals.
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