Versions Compared

Old Version 1

changes.mady.by.user Julia DAUMAL (Unlicensed)

Saved on

compared with

New Version 2

changes.mady.by.user Julia DAUMAL (Unlicensed)

Saved on

Key

  • This line was added.
  • This line was removed.
  • Formatting was changed.
Comment: - Suppression numéros de figures
- Mise en page
Table of Contents

...

List of figures

NXScope capture process

 Figure 2: NXscope generator GUI

Figure 3: file name

Figure 4: NXBoard GUI

Figure 5: NXBoard GUI scope menu

Figure 6: example 1 functional block diagram

Figure 7: example 2 functional block diagram

Figure 8: example 3 functional block diagram

Figure 9: display caused by an erroneous sample

...

The captured samples are read by “nxbase2” or “nxboard” software, via ANGIE USB-JTAG adapter. Note that the JTAG pins are buried in the NXscope IP Core. No need for the user to directly refer to JTAG pins.

...

With nxbase2 software:

Loading the bitstream :

Code Block
>> nxbase2_cli –I –s /bitstream_path/bitstream_name.nxb

Launching a capture :

Code Block
>> nanoxscope capture dump.txt 50E6 immediate=0 (for .txt format/ModelSim)

or

Code Block
>> nanoxscope capture dump.vcd 50E6 immediate=0 (for .vcd format/GTKwave)

Where 50E6 is the estimated frequency of the sample frequency for this example (50 * 10**6 = 50 MHz in this case).

...

At the prompt, launch the following command:

Code Block
>>nxboard

NXboard GUI appears:

Anchor
_Figure4
_Figure4
 

...

A new capture can then be started if required.Important

Note

...

If the trigger condition is not met, the acquisition never resumes, and the software (nxbase2 or nxboard) stays waiting indefinitely.

In order to prevent such situation, it’s possible to use the optional input pin of the NXscope IP Core “TRIGGER_IMMEDIATE”. This pin must be tied to low state in normal situation. When it goes high, an immediate acquisition is started, ignoring the trigger condition(s).

...

Have a look on the following example :

Code Block
languagevhdl
library ieee;


use ieee.std_logic_1164.ALL;


library STD;


use STD.textio.all;


use ieee.std_logic_textio.all;


 


entity TB_NXscope is


end TB_NXscope;


 


architecture TB_ARCHI of TB_NXscope is


 


signal CLK        : std_logic;


signal SAMPLES: std_logic_vector(25+1 downto 0);


 


signal DIN : std_logic_vector(10 downto 0);


signal DIN_VALID  : std_logic;


signal DOUT : std_logic_vector(11 downto 0);


signal DOUT_VALID : std_logic;


 


signal TRIG_PLS   : std_logic;

 

Libraries declarations

 

 

Testbench entity

 

 

Signals declaration

Code Block
languagevhdl
begin


 


process


file RESULT       : text;


variable LINE_VAR : line;


variable DVAR : std_logic_vector(25+1 downto 0);


begin


   file_open(RESULT, "dump.txt", read_mode);


   while not(endfile(RESULT))  loop


      wait until rising_edge(CLK);


      readline(RESULT, LINE_VAR);


      read(LINE_VAR, DVAR);


      SAMPLES <= DVAR;


   end loop;


   file_close(RESULT);


   wait;


end process;

 

 

Main process reading the “dump.txt” result file

 

Values read are assigned to the “SAMPLES” signal

Code Block
languagevhdl
process  begin


   CLK <= '0';  wait for 10 ns;


   CLK <= '1';  wait for 10 ns;


end process; 


 


DIN        <= SAMPLES(10 downto 0);


DIN_VALID  <= SAMPLES(11);


DOUT       <= SAMPLES(23 downto 12);


DOUT_VALID <= SAMPLES(24);


 


TRIG_PLS   <= SAMPLES(25);


 


end TB_ARCHI;

 

Clock waveform

 

“SAMPLES” is split to several signals to restore the original ones

...

The following figure shows an example of the display artifact caused by this erroneous sample in the captured stream.

 

Anchor
_Figure9
_Figure9

 

...

    

NanoXplore is working to correct this problem as soon as possible.

...