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It is recommended to only add the nxpackage in the work library and not component declarations as they are already declared in the package.
Net Network
Basically, there are 2 kind of net networks in NX chips :
Common: Used to connect data like signal, most of the time signals with a low fanout
System: Used to connect clock/reset signal, most of the time signals with a high fanout. This network is composed of 2 sub categories:
Global low-skew network is used to spread signals through the whole fabric with a low skew between all paths
Local low-skew network is used to spread signals through a TILE with a low skew between all paths
There are instances to go from one world to the other one :
CSC: Common to System Converter
SCC : System to Common Converter
Depending on the chip, CSC are implemented in different kinds of primitives.
Each instance in the design has:
Pins with net coming from the Common network OR/AND
Pins with net coming from the System network OR/AND
Pins with net coming from either Common network or System network
For example, a NX_DFF has the following pins and associated connected networks:
Pin | Common | System |
CK | No | Yes |
R | Yes | Yes |
L | Yes | Yes |
D | Yes | No |
Q | Yes | No |
| Note |
|---|
|
Clock management
NanoXplore FPGAs contain a low-skew network in order to spread signal with high fanout like clock, reset and load signals.
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In order to get complexity module by module without confining it in a region, it is possible to use addModule method described in NxDesignSuite 23.5 NxPython Specification NXPython User Manual.
Refer to #Floor_planning_Complexity for more details.
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Please refer to createClock and createGeneratedClock described in NxDesignSuite 23.5 NxPython NXPython Specification .
If a PLL is used, PLL output clock frequencies are automatically computed by the software.
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Please refer to addFalsePath and addMultiCyclePath in NxDesignSuite 23.5 NxPython NXPython Specification .
Clock groups can be created if clock domains are completely unrelated.
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It is possible to map this operators in LUT, Carry or DSP using addMappingDirective method described in NxDesignSuite 23.5 NxPython NXPython Specification .
By default, adders are mapped into Carry and Multipliers in DSP. But it can sometimes be interesting to modify default mapping directives.
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Memories can be mapped into logic elements (LUT/DFF), register files (RF), Memory Blocks (RAM) or Memory Blocks protected by EDAC correction using addMappingDirective method described in NxDesignSuite 23.5 NxPython NXPython Specification .
By default, small memories (equal or less than 64x16) will be mapped into RF and bigger ones mapped into RAM. But it can sometimes be interesting to modify default mapping directives.
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Define a floorplan for the design depending on module relationships and pinout.
Apply the floorplan to your Impulse project using constrainModule described in NxDesignSuite 23.5 NxPython NXPython Specification . Check #Floor_planning_Constrain_module for information about constraint setting.
If needed, repeat this process going deeper and deeper in the design hierarchy.
For last most critical paths, use constrainPath described in NxDesignSuite 23.5 NxPython NXPython Specification in order to create a region with only a few elements contained into the specified path. Check #Floor_planning_Constrain_path_between_registers for information about constraint setting.
It can also have a very positive impact to create unitary projects and reuse the routed projects as a blackbox in your final top project using addBlackBox described in NxDesignSuite 23.5 NxPython NXPython Specification .
It is also possible to place manually instances in a specified using the following NXpython methods all described in NxDesignSuite 23.5 NxPython NXPython Specification :
addPLLLocation for PLL instance in a CKG. Check #Instance_placing_Ring_placing for information about constraint setting.
addWFGLocation for WFG instance in a CKG and a WFG spot. Check #Instance_placing_Ring_placing for information about constraint setting.
addRAMLocation for RAM instance in a CGB. Check #Instance_placing_Ram_placing for information about constraint setting.
addDSPLocation for DSP instance in a CGB and a DSP spot. Check #Instance_placing_Dsp_placing for information about constraint setting.
setSite for LUT/DFF/CY in a TILE. Check #Instance_placing_Tile_placing for information about constraint setting.
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Increasing efforts may optimize placing for STA.
Check NxDesignSuite 23.5 NxPython NXPython Specification for more details about these options.
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The logic depth of a design must be controlled. the method reportDesignComplexity and reportHierarchyComplexity are very helpful to have an overview.
Please have a look at NxDesignSuite 23.5 NxPython NXPython Specification reportDesignComplexity and reportHierarchyComplexity methods.
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