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All NanoXplore primitives are listed in nxLibrary-<variant_name>.vhdp available in the release archive. A documentation is also available in order to get information about all generics and io in Impulse NxDesignSuite 23.3 5 Library Guide .
It is recommended to only add the nxpackage in the work library and not component declarations as they are already declared in the package.
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Use a pad directly connected to the closest CKG (these pads are suffixed by _CLK). Either the user instantiates a PLL or a WFG in the design or the tool instantiates automatically a WFG in bypass mode.
MEDIUM/LARGE: Use a common pad or internal logic and use a buffer NX_BD in global_lowskew mode.
ULTRA: Use a common pad or internal logic and use a NX_GCK_U in Common to System Converter CSC mode.
Please have a look at Impulse NxDesignSuite 23.3 5 Training Package : Application Note Design/LowskewManagement project.
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Clock Gating:
MEDIUM/LARGE: Use a NX_CKS to gate a clock system signals with a command common signal.
ULTRA: Use a NX_GCK_U in Clock Switch CKS mode to gate a clock system signals with a command common signal.
Clock MUX:
ULTRA: Use a NX_GCK_U in Clock MUX MUX mode to switch between 2 clock system signals with a command common signal.
Please have a look at Impulse NxDesignSuite 23.3 5 Training Package : Application Note Component/ClockSwitch project.
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It is recommended to rather use python method addMemoryInitialization described in Impulse NxDesignSuite 23.3 5 NxPython Specification as it is compliant with inferred and instantiated memories.
Please have a look at Impulse NxDesignSuite 23.3 5 Training Package : Application Note Init/Ram project.
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In order to infer a memory instead of instantiating a NanoXplore primitive (advantage is the user can choose with the same RTL code to map this memory in RF, RAM, RAM_ECC, … thanks to NXpython constraints), it is recommended to follow TrainingPackage Design/MemInfer examples providing inference for ROM, SRAM, DPRAM with and without ECC.
Please have a look at Impulse NxDesignSuite 23.3 5 Training Package : Application Note Design/MemInfer project.
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In order to get complexity module by module without confining it in a region, it is possible to use addModule method described in Impulse NxDesignSuite 23.3 5 NxPython Specification.
Refer to #Floor_planning_Complexity for more details.
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Please refer to createClock and createGeneratedClock described in Impulse NxDesignSuite 23.3 5 NxPython Specification .
If a PLL is used, PLL output clock frequencies are automatically computed by the software.
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Please refer to addFalsePath and addMultiCyclePath in Impulse NxDesignSuite 23.3 5 NxPython Specification .
Clock groups can be created if clock domains are completely unrelated.
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It is possible to map this operators in LUT, Carry or DSP using addMappingDirective method described in Impulse NxDesignSuite 23.3 5 NxPython Specification .
By default, adders are mapped into Carry and Multipliers in DSP. But it can sometimes be interesting to modify default mapping directives.
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Memories can be mapped into logic elements (LUT/DFF), register files (RF), Memory Blocks (RAM) or Memory Blocks protected by EDAC correction using addMappingDirective method described in Impulse NxDesignSuite 23.3 5 NxPython Specification .
By default, small memories (equal or less than 64x16) will be mapped into RF and bigger ones mapped into RAM. But it can sometimes be interesting to modify default mapping directives.
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Check #Mapping_Directive_Memory for information about constraint setting.
Placing
Placing Constraint
In order to improve the maximum clock frequency for each clock domain, it is advised to follow the following steps:
Define a floorplan for the design depending on module relationships and pinout.
Apply the floorplan to your Impulse project using confineModule constrainModule described in Impulse NxDesignSuite 23.3 5 NxPython Specification . Check #Floor_planning_Constrain_module for information about constraint setting.
If needed, repeat this process going deeper and deeper in the design hierarchy.
For last most critical paths, use constrainPath described in Impulse NxDesignSuite 23.3 5 NxPython Specification in order to create a region with only a few elements contained into the specified path. Check #Floor_planning_Constrain_path_between_registers for information about constraint setting.
It can also have a very positive impact to create unitary projects and reuse the routed projects as a blackbox in your final top project using addBlackBox described in Impulse NxDesignSuite 23.3 5 NxPython Specification .
It is also possible to place manually instances in a specified using the following NXpython methods all described in Impulse NxDesignSuite 23.3 5 NxPython Specification :
addPLLLocation for PLL instance in a CKG. Check #Instance_placing_Ring_placing for information about constraint setting.
addWFGLocation for WFG instance in a CKG and a WFG spot. Check #Instance_placing_Ring_placing for information about constraint setting.
addRAMLocation for RAM instance in a CGB. Check #Instance_placing_Ram_placing for information about constraint setting.
addDSPLocation for DSP instance in a CGB and a DSP spot. Check #Instance_placing_Dsp_placing for information about constraint setting.
setSite for LUT/DFF/CY in a TILE. Check #Instance_placing_Tile_placing_Tile_placing for information about constraint settingplacing for information about constraint setting.
Placing Option
Some options impact the placing and consequently the routing. In the end, STA performances are directly affected. The following options are concerned:
DensityEffort
CongestionEffort
PolishingEffort
Increasing efforts may optimize placing for STA.
Check NxDesignSuite 23.5 NxPython Specification for more details about these options.
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Optimizing placing options for STA can lead to congestion errors. It is usually a trade-off to balance these options. |
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The logic depth of a design must be controlled. the method reportDesignComplexity and reportHierarchyComplexity are very helpful to have an overview.
Please have a look at Impulse NxDesignSuite 23.3 5 NxPython Specification reportDesignComplexity and reportHierarchyComplexity methods.
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Launch your design for the first time without constraint.
Grab the operator model or instance in operators.rpt report. For instance, “ | Operator 'add_3u_3u' | : add_L25 (line 25 in …”, model name is “add_3u_3u” and instance name is “add_L25”.
Add the constraint specifying instance to map the operator, for instance “ p.addMappingDirective('getModels(add_3u_3u)','ADD','DSP')” or p.addMappingDirective('getInstances(add_L25)','ADD','DSP')”, and relaunch the project.
Check in operators.rpt report the constraint matched with the desired instance.
Please have a look at Impulse NxDesignSuite 23.3 5 Training Package : Application Note MappingDirective/Operator project.
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Launch your design for the first time without constraint.
Grab the memory model in memories.rpt report. For instance, “ | Ram 'RAM_s_mem' Analysis:”, model name is “RAM_s_mem”.
Add the constraint specifying instance to map the operator, for instance “ p.addMappingDirective('getModels(RAM_s_mem)','RAM','RAM_ECC')”, and relaunch the project.
Check in memories.rpt report the constraint matched with the desired instance.
Please have a look at Impulse NxDesignSuite 23.3 5 Training Package : Application Note MappingDirective/Memory project.
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In case of direct primitive instance of the DSP, DSP name is the path to the DSP. For instance, p.addDSPLocation('module0|submodule1|DSP_INST_0','CGB[28x4]:L'). |
Please have a look at Impulse NxDesignSuite 23.3 5 Training Package : Application Note PlacingConstraint/DspLocation project.
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In case of direct primitive instance of the RAM, RAM name is the path to the RAM. For instance, p.addRAMLocation('module0|submodule1|ram','CGB[28x4]'). |
Please have a look at Impulse NxDesignSuite 23.3 5 Training Package : Application Note PlacingConstraint/RamLocation project.
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In order to place manually a WFG, location must comply with WFG type that is to say Core WFG (WFG_Cx) or Ring WFG (WFG_Rx). Mix WFG (WFG_Mx) can be chosen for either a Core or a Ring signal. |
Please have a look at Impulse NxDesignSuite 23.3 5 Training Package : Application Note PlacingConstraint/RingLocation project.
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Launch your design for the first time without constraint.
Grab the register name in RegisterSummary.rpt report or in timing files. For instance, i_cpt_0|s_cpt_out_reg[5]”.
Add the constraint specifying TILE spot (TILE coordinates), for instance “p.setSite('i_cpt_0|s_cpt_out_reg[0]','TILE[2x2]'”, and relaunch the project.
Check in preplaced.rpt report the constraint matched with the desired instance.
Please have a look at Impulse NxDesignSuite 23.3 5 Training Package : Application Note PlacingConstraint/Site project.
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Launch your design for the first time without constraint.
Grab the module name in hierarchy.rpt report. For instance, “| ~ |-> row_col_pipe(X212B9C19) [ GEN_HIER0 ]”, name is “|-> row_col_pipe(X212B9C19) [ GEN_HIER0 ]”.
Add the constraint specifying area coordinates, for instance “p.constrainModule('|-> row_col_pipe(X212B9C19) [ GEN_HIER0 ]','GEN_HIER0_ROW_M','Soft',9,6,2,3,'GEN_HIER0_ROW_R',False)”, and relaunch the project.
Check in hierarchy.rpt report the constraint matched with the desired instance.
Please have a look at Impulse NxDesignSuite 23.3 5 Training Package : Application Note PlacingConstraint/Region project.
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Launch your design for the first time without constraint.
Grab the source and target register in DOMAIN_<clk1>_to_<clk2>_<progress_step>_<conditions>.timing. For instance, “module0|submodule0|pipe_reg[0].CK” and “module0|submodule0|pipe_reg[1].CK” , names are “module0|submodule0|pipe_reg[0]” and “module0|submodule0|pipe_reg[1]”.
Add the constraint specifying area coordinates, for instance “p.constrainPath('|-> row_col_pipe(X212B9C19) [ GEN_HIER0 ]','PIPE_REG_M','Soft',9,6,2,3,'PIPE_REG_R',False)”, and relaunch the project.
Check in hierarchy.rpt report the constraint matched with the desired instance.
Please have a look at Impulse NxDesignSuite 23.3 5 Training Package : Application Note PlacingConstraint/ConstrainPath project.
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Define the macro IP as the top cell.
Define a minimum aperture and all needed constraints as it was a global project to reach specifications. Save the project file after routed steps.
Run the project until Placing 3/5 step and use saveIP method to save the preplaced IP.
Do not declare the macro IP entity file in the global project. Instead, add the macro IP as a blackbox, specifying coordinates of the top left corner of the macro IP aperture in the global project, for instance “
p.addBlackBox('switch_counter',IP','../switch_counter_preplaced.json','g_inst.i_switch_counter_0:1x8')”.Check in log the constraint matched.
Please have a look at Impulse NxDesignSuite 23.3 5 Training Package : Application Note PlacingConstraint/Preplace project.
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developCKGs method is active by default, Impulse computes automatically PLL and WFG required frequencies if input clock is declared.
Please have a look at Impulse NxDesignSuite 23.3 5 Training Package : Application Note StaConstraint/GeneratedClock project.
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Grab the clock name getting the hierarchy path to the generated clock.
Add the constraint specifying clock parameters, for instance “p.createGeneratedClock(getClock('clk_main'),getRegisterClock('i_clock_0|counter_reg[0]'), 'clk_fabric',{'DivideBy': 2})”.
Check timing files are created for this new clock domain.
Please have a look at Impulse NxDesignSuite 23.3 5 Training Package : Application Note StaConstraint/GeneratedClock project.
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Launch your design for the first time without constraint.
Grab the source and target register in DOMAIN_<clk1>_to_<clk2>_<progress_step>_<conditions>.timing. For instance, “module0|submodule0|pipe_reg[0].CK” and “module0|submodule0|pipe_reg[1].CK” , names are “module0|submodule0|pipe_reg[0]” and “module0|submodule0|pipe_reg[1]”.
Add the constraint specifying area coordinates, for instance “p.addFalsePath('getRegisters(module0|submodule0|pipe_reg[0])','getRegisters(module0|submodule0|pipe_reg[0])')”, and relaunch the project.
Check in DOMAIN_<clk1>_to_<clk2>_<progress_step>_<conditions>.timingt report the path no longer appears.
Please have a look at Impulse NxDesignSuite 23.3 5 Training Package : Application Note StaConstraint/FalsePath project.
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