| Table of Contents |
|---|
create_clock
Creates a clock and defines its waveform.
...
| Note |
|---|
Please note that virtual clocks are not handled by Nxmap. |
create_generated_clock
Creates a new clock signal from the clock waveform of a given pin in the design.
...
| Code Block |
|---|
create_generated_clock –divide_by 3 –multiply_by 4 -source [get_ports {clock}] [get_nets {ck}] |
set_clock_groups
Specifies the groups of clocks between which timing analysis will not be done.
...
| Code Block |
|---|
create_clock -period 10 -name "clk1" [get_ports clk_1] create_clock -period 12 -name "clk2" [get_ports clk_2] create_clock -period 15 -name "clk3" [get_ports clk_3] set_clock_groups -asynchronous -group [get_clocks clk1] -group [get_clocks clk2] set_clock_groups -exclusive -group [get_clocks clk1] -group [get_clocks clk3] |
set_false_path
Identifies false paths in a design, and breaks or disables specific instance timing arcs in a design resulting in them not being timed.
...
| Code Block |
|---|
set_false_path -from [get_ports cpt_in*] -to [get_clocks clk2]
set_false_path -from [get_registers {cpt_in_p_reg[0]}] -to [get_registers {i_cpt_0|s_cpt_out_reg[0]}]
set_false_path -from [get_ports {cpt_in[0]}] -to [get_registers {cpt_in_p_reg[0]}] |
set_input_delay
Constrains input and in/out (bidirectional) ports, port busses, and pins (that are valid start points) within the design relative to a clock edge. If you omit both the -min and -max options, the delay is assumed to apply for both setup and hold analysis.
...
| Code Block |
|---|
set_input_delay -clock [get_clocks CLK_MAIN] -clock_fall -min 4.0 [get_ports {cpt_in*}] |
set_output_delay
Constrains output and in/out (bidirectional) ports, port busses, and pins (that are valid start points) within the design relative to a clock edge. If you omit both the -min and -max options, the delay is assumed to apply for both setup and hold analysis.
...
| Code Block |
|---|
set_output_delay -clock [get_clocks CLK_MAIN] -clock_fall -min 4.0 [get_ports {cpt_out*}] |
set_min_delay
Specifies a minimum delay exception for a given path.
...
| Code Block |
|---|
set_min_delay -from [get_registers {i_cpt_0|s_cpt_out_reg[0]}] -to [get_registers {i_cpt_1|s_cpt_out_reg[1]}] 8000
set_min_delay -from [get_ports {cpt_in[0]}] -to [get_registers {i_cpt_1|s_cpt_out_reg[1]}] 2000
set_min_delay -from [get_ports {cpt_in*}] -to [get_registers {i_cpt_1|s_cpt_out_reg[1]}] 1000 |
set_max_delay
Specifies a maximum delay exception for a given path.
...
| Code Block |
|---|
set_max_delay -from [get_registers {i_cpt_0|s_cpt_out_reg[0]}] -to [get_registers {i_cpt_1|s_cpt_out_reg[1]}] 8000
set_max_delay -from [get_ports {cpt_in[0]}] -to [get_registers {i_cpt_1|s_cpt_out_reg[1]}] 2000
set_max_delay -from [get_ports {cpt_in*}] -to [get_registers {i_cpt_1|s_cpt_out_reg[1]}] 1000 |
set_multicycle_path
Specifies a multicycle exception for a given set of paths.
...