Introduction
The aim of this document is to explain how to simulate a design dedicated to NanoXplore targets under Questa/Modelsim tools.
The needed minimum version is modelsim 10.6d
Design simulation
Simulation
The user design may include NX primitives with files calling nxpackage as follow in a VHDL file:
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#Compile nx file vlib nx vcom -work nx -2008 nxmap-dbg-22.1.0.1/share/modelsim/nxLibrary-Medium.vhdp #Compile design file vlib work vcom -work work -2008 sub_module1.vhd vcom -work work -2008 sub_module2.vhd vcom -work work -2008 top.vhd #Compile testbench vcom -work work -2008 tb_top.vhd #Simulate vsim -t 1ps -lib work work.tb_top |
Netlist simulation
It can be useful to simulate a design with the output netlist generated after synthesis. Indeed, it give the ability to check NXmap synthesis tool mapped correctly the design into a flattened design containing only NX primitives even after optimizations.
Netlist generation
The netlist must be generated using NXmap tool in the NXmap flow as follows:
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from nxmap import *
#Project creation
p=createProject('')
p.setVariantName("NG-MEDIUM")
p.setTopCellName("work", "top")
p.addFile('work','sub_module1.vhd')
p.addFile('work','sub_module2.vhd')
p.addFile('work','top.vhd.vhd')
#Project steps
p.synthesize()
p.place()
p.route()
p.save('top_routed.vhd') |
Simulation
Then, in the simulation script, netlist must be compiled instead of all design files as follows:
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#Compile nx file vlib nx vcom -work nx -2008 nxmap-dbg-22.1.0.1/share/modelsim/nxLibrary-Medium.vhdp #Compile design file vlib work vcom -work work -2008 top_routed.vhd #Compile testbench vcom -work work -2008 tb_top.vhd #Simulate vsim -t 1ps -lib work work.tb_top |
Backannoted simulation
Backannoted simulation is a simulation with the output netlist but taking account of timing delays between and inside NX primitives.
It can be useful in order to detect a timing violation in the design and it consequence.
Netlist and SDF generation
In addition of the netlist, a Standard Delay Format (SDF) output file must be generated using NXmap tool in the NXmap flow as follows:
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NanoXplore SDF file contain only minimum and maximum values so only -sdfmin and -sdfmax arguments are allowed. |
Simulation
Instead of the modelsim file, the backannoted file must be compile.
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#Compile nx file vlib nx vcom -work nx -2008 nxmap-dbg-22.1.0.1/share/backannoted/nxLibrary-Medium.vhdp #Compile design file vlib work vcom -work work -2008 top_routed.vhd #Compile testbench vcom -work work -2008 tb_top.vhd #Simulate vsim -t 1ps -lib work work.tb_top -sdfmax sim/:tb_top:i_top_0=top_routed.sdf |
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Path to module depends on PathSeparator and DatasetSeparator variables in modelsim.ini This example is given with the following variables: PathSeparator = : DatasetSeparator= / |