Introduction

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The NX_GCK_U can be used exclusively by instantiation. The current version of NXmap3 does not yet support inference for this device.

Generics

inv_in

type bit

default value ‘0’

This generic select wether to invert (inv_in = ‘1’) or not both clock inputs pins SI1 and SI2.

inv_out

type bit

default value ‘0’

This generic select wether to invert (inv_out = ‘1’) or not the clock output pin SO.

std_mode

type string

default value “BYPASS”

Select the configuration mode of the NX_GCK_U. NX_GCK_U can be configured into the following modes:

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The NX_CKS can be used exclusively by instantiation. The current version of NXmap does not yet support inference for this device.

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Figure 1: CKS chronograms

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Figure 2: NG-ULTRA CKG block diagram

The next figure shows a block diagram of the NX_PLL_U and the user’s settings (in yellow).

Figure 3: Simplified NG-ULTRA PLL block diagram

Generics

location

type string

default value “”

This generic allows to define the NX_PLL_U location directly in the source code (instead of using the nxpython addPLLLocation method).

Example : location => “CKG2.PLL1”

use_pll

type bit

default value 0

Set to 1 to enable the PLL. When set to 0, the PLL is bypassed with Fvco = Frefo.

pll_odf

type bit_vector (1 downto 0)

default value others => ‘0’

Define the output division factor of the PLL (factors: 1, 2, 5 and 10).

pll_lock

type bit_vector (1 downto 0)

default value others => ‘0’

Configure the frequency lock.

ref_intdiv

type bit_vector (4 downto 0)

default value others => ‘0’

The REFerence frequency can be divided by factors ranging from 1 to 32 before reaching the VCO input. This allows to give more flexibility of the PLL generated output frequency, and increase the PLL input frequency range.

For VCO expected at 400MHz, ref_intdiv value must be set to 8 with a REF input frequency range between 45 and 450 Mhz.

ref_osc_on

type bit

default value ‘0’

This generic configures the source of the PLL reference.

If ref_osc_on is set to ‘0’, the input reference of the pll is the REF input pin.

If set to ‘1’, the internal oscillator is used as reference of the PLL.

ext_fbk_on

type bit

default value ‘0’

When ‘0’, the internal feedback path is selected. The output of the FBK_INTDIV divider is used as feedback source. The VCO output frequency is divided by (fbk_intdiv + 1)

When ‘1’, the external feedback path is selected. This is particularly useful for “zero delay” clock generation.

fbk_intdiv

type bit_vector (6 downto 0)

default value others => ‘0’

Internal feedback divider of N+1 ratio (with division from 1 to 128).

fbk_delay_on

type bit

default value ‘0’

This generic configures whether the delay of the feedback path is active (‘1’) or not (‘0’).

fbk_delay

type bit_vector (5 downto 0)

default value others => ‘0’

The number of delay taps on the feedback path (internal or external) can be adjusted to meet the required phase on the VCO outputs. When using external feedback, it can be used to compensate the delay on the reference clock input to the REF pin of the PLL via the semi-dedicated clock input pin and associated direct routing.

The delay can be selected or not (see fbk_delay_on). When selected, it can be adjusted from 340 ps (fbk_delay = 0) to 10580 ps (fbk_delay = 63) by steps of 160 ps.

clk_outdiv1 : applies to CLK_DIV1

type bit_vector (2 downto 0)

default value others => ‘0’

...

CLK_DIV1 = Fpll/(2*7+3) = Fpll / 17

clk_outdiv2 : applies to CLK_DIV2

type bit_vector (2 downto 0)

default value others => ‘0’

...

CLK_DIV2 = Fpll/(2*7+5) = Fpll / 19

clk_outdiv3 : applies to CLK_DIV3

type bit_vector (2 downto 0)

default value others => ‘0’

...

CLK_DIV3 = Fpll/(2*0+5) = Fpll / 7

If clk_outdiv3 = 7

CLK_DIV3 = Fpll/(2*7+5) = Fpll / 21

clk_outdiv4 : applies to CLK_DIV4

type bit_vector (2 downto 0)

default value others => ‘0’

...

CLK_DIV4 = Fpll/(2*0+5) = Fpll / 9

If clk_outdiv4 = 7

CLK_DIV4 = Fpll/(2*7+5) = Fpll / 23

clk_outdivd* : applies to CLK_DIVD*

type bit_vector (3 downto 0)

default value others => ‘0’

...

This generic allows to define the divider value of the CLK_DIVD* output. There are 16 possible values:

* clk_outdivd1/2/3/4/5 respectively apply to CLK_DIVD1/2/3/4/5

use_cal

type bit

default value ‘0’

When set to 0, the calibration module is bypassed. When set to 1, the calibration module is activated with cal_div and cal_delay generics used to define divide and delay values of the calibration engine.

clk_cal_sel

type bit_vector (1 downto 0)

default value “01”

Select the clock used for internal calibration.

cal_div

type bit_vector (3 downto 0)

default value “0111”

Set the division factor of the calibration engine.

cal_delay

type bit_vector (5 downto 0)

default value “011011”

Set the delay value of the calibration engine.

Notes about user’s adjustable delays on NG-ULTRA:

The PLL has a user’s selectable and adjustable delay line (no delay or 0 to 63 x 100 ps +/- 5% delay taps) on the feedback path. A similar delay chain is available in each WFGs. Finally, the IO banks have input, output and tri-state command 64-tap delay chains.

All the delay chain taps are calibrated with the same automatic process and hardware resources.

The procedure is transparent to the user.

The delays calibration system uses the PLL 400 MHz oscillator output as reference clock to calibrate all delays: feedback path in the PLL itself, WFG delays and calibration delay in same CKG), and IO delays in the neighboring complex IO banks:

• CKG1 oscillator calibrates the delays in CKG1 (PLL + CAL+ WFGs)

  • Banks 11 to 13

• CKG2 oscillator calibrates the delays in CKG2 (PLL + CAL + WFGs)

  • Banks 2 to 3

• CKG3 oscillator calibrates the delays in CKG3 (PLL + CAL + WFGs)

• CKG4 oscillator calibrates the delays in CKG4 (PLL + CAL + WFGs)

  • Banks 4 to 5

• CKG5 oscillator calibrates the delays in CKG5 (PLL + CAL+ WFGs)

Banks 8 to 10

• CKG6 oscillator calibrates the delays in CKG6 (PLL + CAL+ WFGs)

  • Banks 8 to 10

• CKG7 oscillator calibrates the delays in CKG7 (PLL + CAL+ WFGs)

  • Banks 11 to 13

The calibration procedure takes about 10 µs at startup. The “CAL_LOCKED” output goes high when the delay calibration process is complete. Can be used as status bit.

Ports

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Figure 4: NX_WFG_U diagram

Generics

location

type string

default value “” (no location constraint)

This generic allows to define the NX_WFG_L location directly in the source code (with the addWFGLocation method)

Example : location => “CKG2.WFG_C2”,

delay

type integer

default value 0

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The NX_ADD is composed of 4 stages numbered from 1 to 4 where 1 represents the LSB.

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Figure 6: NX_ADD diagram

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The NX_LUT component describes a 4-input LUT as part of a functional element (FE) as shown in the following diagram:

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Figure 7: NX_LUT diagram

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The nxmap nxLibrary-Ultra.vhdp defines several dedicated NX IP models, instantiating NX_RFB_U component, for each of the above configurations.

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Figure 9: 32x18 RF implemented in a TILE of NG-Ultra

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Figure 12: DSP 24x32 bits unsigned multiplication

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Figure 13: DSP 24x36 bits unsigned multiplication

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The following is the declaration of the component NX_DSP_U_SPLIT, included in the nxLibrary-Ultra.vhdp package.

component NX_DSP_U_SPLIT

generic (

-------------------------------------------------------------------------

...

-------------------------------------------------------------------------

SIGNED_MODE : bit := '0';

INV_WE : bit := '0';

INV_WEZ : bit := '0';

INV_RST: bit := '0';

INV_RSTZ : bit := '0';

ALU_DYNAMIC_OP : bit_vector(1 downto 0) := B"00"; -- '00' for Static,

-- '-1' for Dynamic control from C

-- '10' for Dynamic control from D

SATURATION_RANK : bit_vector(5 downto 0) := B"000000"; -- Weight of useful MSB on Z and CZO result

-- (to define saturation and overflow)

ENABLE_SATURATION : bit := '0'; -- '0' for Disable, '1' for Enable

MUX_CCO : bit := '0'; -- '0' for CCO = ALU(42), '1' for CCO = ALU(56)

MUX_Z : bit := '0'; -- Select Z output. '0' for Y, '1' Saturation / ALU

MUX_CZ : bit := '0'; -- Select MUX_X input. '0' for CZI, '1' for CZO

MUX_Y : bit := '0'; -- Select ALU's Y input. '0' for MULT output, '1' for (B & A)

MUX_X : bit_vector(2 downto 0) := B"000"; -- Select MUX_X operation

...

-- "110" for MUX_X >> 17

-- "111" for MUX_X >> 18

MUX_CCI : bit := '0'; -- Select '1' input of CI mux. '0' for CCI, '1' for CO_feddback

MUX_CI : bit := '0'; -- Select input carry of ALU. '0' for CI, '1' for CCI/CO_feedback mux

MUX_P : bit := '0'; -- '0' for PRE_ADDER, '0' for B input

MUX_B : bit := '0'; -- '0' = B input, '1' = CBI input

MUX_A : bit := '0'; -- '0' = A input, '1' = CAI input

PRE_ADDER_OP : bit := '0'; -- '0' = Add, '1' = Sub

-------------------------------------------------------------------------

...

-------------------------------------------------------------------------

PR_WE_MUX : bit := '0'; -- '0' for No pipe reg, '1' for 1 pipe reg

PR_WEZ_MUX : bit := '0'; -- '0' for No pipe reg, '1' for 1 pipe reg

PR_RST_MUX : bit := '0'; -- '0' for No pipe reg, '1' for 1 pipe reg

PR_RSTZ_MUX : bit := '0'; -- '0' for No pipe reg, '1' for 1 pipe reg

PR_OV_MUX : bit := '0'; -- '0' for No pipe reg, '1' for 1 pipe reg

PR_CO_MUX : bit := '0'; -- Registered carry out (CO42 & CO56)

PR_CCO_MUX : bit := '0'; -- Registered cascade carry out

PR_Z_MUX : bit := '0'; -- Registered output

PR_CZ_MUX : bit := '0'; -- Registered Cascade output

PR_Y_MUX : bit := '0'; -- '0' for No pipe reg, '1' for 1 pipe reg

PR_X_MUX : bit := '0'; -- '0' for No pipe reg, '1' for 1 pipe reg

PR_CI_MUX : bit := '0'; -- '0' for No pipe reg, '1' for 1 pipe reg

PR_MULT_MUX : bit := '0'; -- No pipe reg -- Register inside MULT

PR_P_MUX : bit := '0'; -- '0' for No pipe reg, '1' for 1 pipe reg (Pre-adder)

PR_D_MUX : bit := '0'; -- '0' for No pipe reg, '1' for 1 pipe reg

PR_C_MUX : bit := '0'; -- '0' for No pipe reg, '1' for 1 pipe reg

PR_B_CASCADE_MUX : bit_vector(1 downto 0) := "00"; -- Number of pipe reg levels for CAO output. "-0" for 0 level, "01" for 1 level, "11" for 2 levels

PR_B_MUX : bit_vector(1 downto 0) := "00"; -- Number of pipe reg levels on B input. "-0" for 0 level, "01" for 1 level, "11" for 2 levels

PR_A_CASCADE_MUX : bit_vector(1 downto 0) := "00"; -- Number of pipe reg levels for CAO output. "-0" for 0 level, "01" for 1 level, "11" for 2 levels

PR_A_MUX : bit_vector(1 downto 0) := "00"; -- Number of pipe reg levels on A input. "-0" for 0 level, "01" for 1 level, "11" for 2 levels

...

-------------------------------------------------------------------------

ENABLE_PR_OV_RST : bit := '1'; -- '0' for Disable, '1' for Enable

ENABLE_PR_CO_RST : bit := '1'; -- '0' for Disable, '1' for Enable

ENABLE_PR_CCO_RST : bit := '1'; -- '0' for Disable, '1' for Enable

ENABLE_PR_Z_RST : bit := '1'; -- '0' for Disable, '1' for Enable

ENABLE_PR_CZ_RST : bit := '1'; -- '0' for Disable, '1' for Enable

ENABLE_PR_Y_RST : bit := '1'; -- '0' for Disable, '1' for Enable

ENABLE_PR_X_RST : bit := '1'; -- '0' for Disable, '1' for Enable

ENABLE_PR_CI_RST : bit := '1'; -- '0' for Disable, '1' for Enable

ENABLE_PR_MULT_RST : bit := '1'; -- '0' for Disable, '1' for Enable

ENABLE_PR_P_RST : bit := '1'; -- '0' for Disable, '1' for Enable

ENABLE_PR_D_RST : bit := '1'; -- '0' for Disable, '1' for Enable

ENABLE_PR_C_RST : bit := '1'; -- '0' for Disable, '1' for Enable

ENABLE_PR_B_RST : bit := '1'; -- '0' for Disable, '1' for Enable

ENABLE_PR_A_RST : bit := '1'; -- '0' for Disable, '1' for Enable

-- PR_CZ_INIT : bit_vector(5 downto 0) := B"000000"; -- Value of CZ's pipe register on reset

...

-------------------------------------------------------------------------

ALU_OP : bit_vector(2 downto 0) := B"000"; -- ALU operation

-- x+y+c = "000"

...

-- -x+y-c = "110"

-- -x-y+c-2 = "111"

);

port(

CK : IN std_logic;

R : IN std_logic;

RZ : IN std_logic;

WE : IN std_logic;

WEZ : IN std_logic;

CI : IN std_logic;

A : IN std_logic_vector(23 downto 0);

B : IN std_logic_vector(17 downto 0);

C : IN std_logic_vector(35 downto 0);

D : IN std_logic_vector(17 downto 0);

CAI : IN std_logic_vector(23 downto 0);

CBI : IN std_logic_vector(17 downto 0);

CZI : IN std_logic_vector(55 downto 0);

CCI : IN std_logic;

Z : out std_logic_vector(55 downto 0);

CO42 : OUT std_logic;

CO56 : OUT std_logic;

OVF : OUT std_logic;

CAO : OUT std_logic_vector(23 downto 0);

CBO : OUT std_logic_vector(17 downto 0);

CZO : OUT std_logic_vector(55 downto 0);

CCO : OUT std_logic

);

end component

NX_DSP_U_WRAP

Description

The NX_DSP_U_WRAP component provides a wrapper around NX_DSPU IP for user convenience, concatening bits into vector interfaces. The generics are the same as NX_DSP_U, check the associated section for detail explanations.

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However, simultaneous write access on both ports at the same physical address, or write access simultaneous with a read access at the same physical address are not allowed.

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Figure 17: RAM diagram

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The following array list the clock, reset and config (interruptions, trigger, hold) signals exchanged between the fabric and the SOC.

AXI Master requests

The Network interconnect of the SoC (NIC) handles different protocols for different interfaces, including two set of AXI master interfaces connected to the fabric.

* : valid for M1 and M2 AXI Master requests

...

The Network interconnect of the SoC (NIC) handles different protocols for different interfaces, including two set of AXI slave interfaces connected to the fabric.

* : valid for S1 and S2 slave requests

...

The Network interconnect of the SoC (NIC) handles different protocols for different interfaces, including a FPGA DDR interface through which the fabric can send requests to the DDR controller in the SoC.

LLPP requests

The Network interconnect of the SoC (NIC) handles different protocols for different interfaces, including four Low Latency Parallel Port (LLPP) interfaces through which R52 cores of the SoC can send requests directly to the fabric.

* : valid for llpp0, llpp1, llpp2 and llpp3 requests

...

The SoC provides several services and error management & monitoring functionalities which are connected to the NIC and can be available through the fabric with the following interface.

SERVICE

NX_SERVICE_U_WRAP

Description

The NX_SERVICE_U_WRAP component describes the complete set of signals transiting between the Service bank) and the fabric of NG-Ultra.

Generics

bsm_config

type bit_vector(31 downto 0)

default value B"00000000000000000000000000000000"

This generic specifies the configuration for the bitstream functionalities.

ahb_config

type bit_vector(31 downto 0)

default value B"00000000000000000000000000000000"

This generic specifies the configuration for the ahb interface.

Ports

Lowskew

BSM

Debug

OTP User

Mrepair OTP

Mrepair

I/O elements

NX_IOB

Description

The NX_IOB component describes a bidirectional port of the design. The behavior is:

...

The NX_IOB can be instantiated anywhere in the design hierarchy. It allows to define buried ports (no signal appears in the ports list).

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Figure 22: IOB diagram

Generics

Note that the generic assigned to this primitive can be overridden by the addPad or addPads methods in the script file.

...

location => ”IO_B2_D01_P_SWDO”,

locked => ‘1’

Ports

...

-- The pad will take the name of the instance

);

NX_IOB_I

Description

The NX_IOB_I component describes an input port of the design. The behavior is:

...

...

Figure 23: IOB_I diagram

Generics

Note that the generic assigned to this primitive can be overridden by the addPad or addPads methods used in nxpython script file.

...

location => ”IO_B2_D01_P_SWDO”,

locked => ‘1’

Ports

...

IOB_0 : NX_IOB_I

generic map(

    location             => “IO_B12_D10_N”,

    standard             => “LVCMOS“,

    drive                => “4mA“,

    turbo                => “True”,

    inputDelayOn         => ‘1’,

    inputDelayLine       => “13”,

    inputSignalSlope     => “8”,

    locked               => ‘1’

   )

port map (

      O =>  toFPGAcore

    , T =>  ’1’

    , IO => open     -- A signal name is not required on the external  

                     -- signal

                     -- The pad will take the name of the instance

   );

NX_IOB_O

Description

The NX_IOB_O component describes an output port of the design. The behavior is:

...

The NX_IOB can be instantiated anywhere in the design hierarchy. It allows to define buried ports (no signal appears in the ports list).

...

...

Figure 24: IOB_O diagram

Generics

Note that the generic assigned to this primitive can be overridden by the addPad or addPads methods in the script file.

...

Figure 30: SER_DES IP Core simplified diagram

NX_DES

Description

The NX_DES is a high performance DESerializer. The complex banks allows to configure the I/Os as DESerializers with deserialization factor from 2 to 5. Higher deserialization factors (6, 7, 8, 9 and 10) can be achieved by combining the two deserializers of a differential IO pair.

...

Figure 31 NX_DES primitive

Generics

data_size

type integer (range 2 to 10)

...

Example :

dpath_dynamic => ‘1’

Ports

...

DIG must be high for normal operation, particularly for delay calibration.

NX _SER

Description

The NX_SER is a high performance SERializer. The complex banks allows to configure the I/Os as SERializers with serialization factor from 2 to 5. Higher serialization factors (6, 7, 8, 9 and 10) can be achieved by combining the two serializers of a differential IO pair.

...

Figure 32: NX_SER primitive

Generics

data_size

type integer

default value Undefined (no default value)

...

Example :

dpath_dynamic => ‘1’

Ports