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All NanoXplore primitives are listed in nxLibrary-<variant_name>.vhdp available in the release archive. A documentation is also available in order to get information about all generics and io in Library guide.
It is recommended to only add the nxpackage in the work library and not component declarations as they are already declared in the package.
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Use a pad directly connected to the closest CKG (these pads are suffixed by _CLK). Either the user instantiates a PLL or a WFG in the design or the tool instantiates automatically a WFG in bypass mode.
Use a common pad and use a buffer NX_BD in global_lowskew mode.
Please have a look at Training Package : Application Note Design/LowskewManagement project.
Global signals management
There are some signals with high fan out can be mapped into low-skew network and introduced some important delays. It could be the problem with synchronous signals load, set, reset, …
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Clock gating and switch
NanoXplore FPGAs get clock switch primitive NX_CKS in order to gate a clock with a dedicated techno dependent cell.
In addition, NG-ULTRA family FPGAs get a clock mux pritmitive, NX_GCK_U in MUX mode in order to switch between clocks with a dedicated techno dependent cell. For NG-MEDIUM and NG-LARGE family, mux must be done with 2 NX_CKS.
Please have a look at Training Package : Application Note Component/ClockSwitch project.
For NG-ULTRA family, NX_CKS is a NX_GCK_U in CKS mode.
Reset management
It is recommended to make global design reset going through the low-skew network. As clocks, they can come from an IO pad and be inserted in the low-skew network thanks to a WFG or if generated internally be guided to the low-skew network with a buffer.
All NanoXplore primitives are reset high sensitive but can manage either synchronous or asynchronous reset.
Thus, it is a better way to use directly active high reset in the design.
In case of active low reset for design processes, it is recommended to invert the input reset signal before low-skew insertion.
Global signals management
There are some signals with high fan out can be mapped into low-skew network and introduced some important delays. It could be the problem with synchronous signals load, set, reset, …
In order to avoid this problem, use rejectLowskew method.
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p.rejectLowskew('inst1|reset_sync') |
Memory initialization
There are several ways to initialize a memory (attribute, generic, python method).It is recommended to rather use python method addMemoryInitialization described in /wiki/spaces/~814749387/pages/48660481 as it is compliant with inferred and instantiated memoriesways to initialize a memory (attribute, generic, python method).
It is recommended to rather use python method addMemoryInitialization described in /wiki/spaces/~814749387/pages/48660481 as it is compliant with inferred and instantiated memories.
Please have a look at Training Package : Application Note Init/Ram project.
Memory Inference
In order to infer a memory instead of instantiating a NanoXplore primitive (advantage is the user can choose with the same RTL code to map this memory in RF, RAM, RAM_ECC, … thanks to NXpython constraints), it is recommended to follow TrainingPackage Design/MemInfer examples providing inference for ROM, SRAM, DPRAM with and without ECC.
Please have a look at Training Package : Application Note Init Design/Ram MemInfer project.
Memory Inference
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Avoid optimization of a signal
Because of instance optimization, the synthesis tool can merge or delete some design signals.
For some reasons, a user can ask the tool for avoiding this kind of optimization adding attributes in the RTL code.
syn_preserve attribute is dedicated to registers.
syn_keep/syn_noprune are equivalent and dedicated to logic signals.
Please have a look at Training Package : Application Note Design/MemInfer project Attribute/SynKeep and Attribute/SynPreserve projects.
Hierarchy
It is recommended to divide the design in well sized modules depending on the function they are responsible for.
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Launch your design for the first time without constraint.
Grab the operator model or instance in operators.rpt report. For instance, “ | Operator 'add_3u_3u' | : add_L25 (line 25 in …”, model name is “add_3u_3u” and instance name is “add_L25”.
Add the constraint specifying instance to map the operator, for instance “ p.addMappingDirective('getModels(add_3u_3u)','ADD','DSP')” or p.addMappingDirective('getInstances(add_L25)','ADD','DSP')”, and relaunch the project.
Check in operators.rpt report the constraint matched with the desired instance.
Please have a look at Training Package : Application Note MappingDirective/Operator project.
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Launch your design for the first time without constraint.
Grab the memory model in memories.rpt report. For instance, “ | Ram 'RAM_s_mem' Analysis:”, model name is “RAM_s_mem”.
Add the constraint specifying instance to map the operator, for instance “ p.addMappingDirective('getModels(RAM_s_mem)','RAM','RAM_ECC')”, and relaunch the project.
Check in memories.rpt report the constraint matched with the desired instance.
Please have a look at Training Package : Application Note MappingDirective/Memory project.
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In case of direct primitive instance of the DSP, DSP name is the path to the DSP. For instance, p.addDSPLocation('module0|submodule1|DSP_INST_0','CGB[28x4]:L'). |
Please have a look at Training Package : Application Note PlacingConstraint/DspLocation project.
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In case of direct primitive instance of the RAM, RAM name is the path to the RAM. For instance, p.addRAMLocation('module0|submodule1|ram','CGB[28x4]'). |
Please have a look at Training Package : Application Note PlacingConstraint/RamLocation project.
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| Note |
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In order to place manually a WFG, location must comply with WFG type that is to say Core WFG (WFG_Cx) or Ring WFG (WFG_Rx). Mix WFG (WFG_Mx) can be chosen for either a Core or a Ring signal. |
Please have a look at Training Package : Application Note PlacingConstraint/RingLocation project.
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Launch your design for the first time without constraint.
Grab the register name in RegisterSummary.rpt report or in timing files. For instance, i_cpt_0|s_cpt_out_reg[5]”.
Add the constraint specifying TILE spot (TILE coordinates), for instance “p.setSite('i_cpt_0|s_cpt_out_reg[0]','TILE[2x2]'”, and relaunch the project.
Check in preplaced.rpt report the constraint matched with the desired instance.
Please have a look at Training Package : Application Note PlacingConstraint/Site project.
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Launch your design for the first time without constraint.
Grab the module and instance name in hierarchy.rpt report. For instance, “| |-> timing_pipe(X2A98C8C6) [ GEN_HIER0|GEN_ROW[0].ROW_PIPE ]”, module name is timing_pipe(X2A98C8C6)” and instance name is “[ GEN_HIER0|GEN_ROW[0].ROW_PIPE ]”.
Add the constraint for instance “p.addModule('timing_pipe(X2A98C8C6)', 'GEN_HIER0.GEN_ROW[0].ROW_PIPE', 'GEN_HIER0_ROW-%')”, and relaunch the project.
Check in hierarchy.rpt report the constraint matched with the desired instance.
Please have a look at Training Package : Application Note PlacingConstraint/Region project.
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Launch your design for the first time without constraint.
Grab the module name in hierarchy.rpt report. For instance, “| ~ |-> row_col_pipe(X212B9C19) [ GEN_HIER0 ]”, name is “|-> row_col_pipe(X212B9C19) [ GEN_HIER0 ]”.
Add the constraint specifying area coordinates, for instance “p.constrainModule('|-> row_col_pipe(X212B9C19) [ GEN_HIER0 ]','GEN_HIER0_ROW_M','Soft',9,6,2,3,'GEN_HIER0_ROW_R',False)”, and relaunch the project.
Check in hierarchy.rpt report the constraint matched with the desired instance.
Please have a look at Training Package : Application Note PlacingConstraint/Region project.
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Define the macro IP as the top cell.
Define a minimum aperture and all needed constraints as it was a global project to reach specifications. Save the project file after routed steps.
Do not declare the macro IP entity file in the global project. Instead, add the macro IP as a blackbox, specifying coordinates of the top left corner of the macro IP aperture in the global project, for instance “
p.addBlackBox('switch_counter',IP','../switch_counter_preplaced.nym','g_inst.i_switch_counter_0:1x8')”.Check in synthesize.log llog the constraint matched.
Please have a look at Training Package : Application Note PlacingConstraint/Preplace project.
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developCKGs method is active by default, NXmap compute automatically PLL and WFG required frequencies if input clock is declared.
Please have a look at Training Package : Application Note StaConstraint/GeneratedClock project.
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Grab the clock name getting the hierarchy path to the generated clock.
Add the constraint specifying clock parameters, for instance “p.createGeneratedClock(getClock('clk_main'),getRegisterClock('i_clock_0|counter_reg[0]'), 'clk_fabric',{'DivideBy': 2})”.
Check timing files are created for this new clock domain.
Please have a look at Training Package : Application Note StaConstraint/GeneratedClock project.
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Launch your design for the first time without constraint.
Grab the source and target register in DOMAIN_<clk1>_to_<clk2>_<progress_step>_<conditions>.timing. For instance, “module0|submodule0|pipe_reg[0].CK” and “module0|submodule0|pipe_reg[1].CK” , names are “module0|submodule0|pipe_reg[0]” and “module0|submodule0|pipe_reg[1]”.
Add the constraint specifying area coordinates, for instance “p.addFalsePath('getRegisters(module0|submodule0|pipe_reg[0])','getRegisters(module0|submodule0|pipe_reg[0])')”, and relaunch the project.
Check in DOMAIN_<clk1>_to_<clk2>_<progress_step>_<conditions>.timingt report the path no longer appears.
Please have a look at Training Package : Application Note StaConstraint/FalsePath project.
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