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Comment: add CompareProjects (compareInstances+compareSta)

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Code Block
breakoutModewide
$ make wfg_calculator_interface
wfg_calculator_interface
What is the input clock frequency in MHz ?
100
What is the output clock frequency in MHz. It has to be input clock frequency divided by power of 2 in the range [6.25;100.0]?
25
For how many input clock cycles do you want to shift output clock in the range [0;2] ?
1
On which edge of input clock do you want to generate output clock ?
 1 - Rising edge 
 2 - Falling edge
1

//////////WFG parameters//////////
mode             => '1'                                             ,
wfg_edge         => '1'                                             ,
pattern          => "0110011001100110"                              ,
pattern_end      => 15   

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constrainModules

constrainModules

Code Block
breakoutModewide
$ make constrain_modules HIERARCHY_FILE=~/fae/tool/tool/hierarchy.rpt HIERARCHY_LEVEL_MAX=2 EXCLUSIVE=False
constrain_modules HIERARCHY_FILE=/home/users/kchopier/fae/tool/tool/hierarchy.rpt HIERARCHY_LEVEL_MAX=2 EXCLUSIVE=False

#New sub-module
p.addModule('RAM(X6AAF88E9)','g_loop_depth4[0].i_RAM_example','RAM(X6AAF88E9)_MOD0-%')
#New sub-module
p.addModule('RAM(X6AAF88E9)','g_loop_depth4[1].i_RAM_example','RAM(X6AAF88E9)_MOD1-%')
#New sub-module
p.addModule('RAM(X5A5D25DC)','g_loop_depth8[0].i_RAM_example','RAM(X5A5D25DC)_MOD0-%')
#New sub-module
p.addModule('RAM(X5A5D25DC)','g_loop_depth8[1].i_RAM_example','RAM(X5A5D25DC)_MOD1-%')

p.createRegion('RAM(X6AAF88E9)_REG0',,,,,False)
p.createRegion('RAM(X6AAF88E9)_REG1',,,,,False)
p.createRegion('RAM(X5A5D25DC)_REG0',,,,,False)
p.createRegion('RAM(X5A5D25DC)_REG1',,,,,False)

p.confineModule('RAM(X6AAF88E9)_MOD0-0','RAM(X6AAF88E9)_REG0')
p.confineModule('RAM(X6AAF88E9)_MOD1-0','RAM(X6AAF88E9)_REG1')
p.confineModule('RAM(X5A5D25DC)_MOD0-0','RAM(X5A5D25DC)_REG0')
p.confineModule('RAM(X5A5D25DC)_MOD1-0','RAM(X5A5D25DC)_REG1')

...

Code Block
$ make stat_modules HIERARCHY_FILE=~/fae/tool/tool/hierarchy.rpt
stat_modules HIERARCHY_FILE=/home/users/kchopier/fae/tool/tool/hierarchy.rpt

////////// GEN_HIER0_COL-0 //////////
// TILE //
{'LUT': 0.0, 'DFF': 0.01, 'XLUT': 0.0, 'CY': 0.0, 'RFB': 0.0}
// CGB //
{'DSP': 0.0, 'RAM': 0.0}

////////// GEN_HIER0_ROW-0 //////////
// TILE //
{'LUT': 0.0, 'DFF': 0.01, 'XLUT': 0.0, 'CY': 0.0, 'RFB': 0.0}
// CGB //
{'DSP': 0.0, 'RAM': 0.0}

////////// GEN_HIER1_COL_0 //////////
// TILE //
{'LUT': 0.0, 'DFF': 0.01, 'XLUT': 0.0, 'CY': 0.0, 'RFB': 0.0}
// CGB //
{'DSP': 0.0, 'RAM': 0.0}

////////// GEN_HIER1_ROW_0 //////////
// TILE //
{'LUT': 0.0, 'DFF': 0.01, 'XLUT': 0.0, 'CY': 0.0, 'RFB': 0.0}
// CGB //
{'DSP': 0.0, 'RAM': 0.0}

////////// GEN_HIER1_ROW_1 //////////
// TILE //
{'LUT': 0.0, 'DFF': 0.01, 'XLUT': 0.0, 'CY': 0.0, 'RFB': 0.0}
// CGB //
{'DSP': 0.0, 'RAM': 0.0}

////////// GEN_HIER2_COUNTER0-0 //////////
// TILE //
{'LUT': 0.01, 'DFF': 0.01, 'XLUT': 0.0, 'CY': 0.0, 'RFB': 0.0}
// CGB //
{'DSP': 0.0, 'RAM': 0.0}

////////// GEN_HIER2_COUNTER1-0 //////////
// TILE //
{'LUT': 0.0, 'DFF': 0.11, 'XLUT': 0.0, 'CY': 0.0, 'RFB': 0.0}
// CGB //
{'DSP': 0.0, 'RAM': 0.0}


////////// SUMMARY //////////
|Module                          |TILE    |CGB     |
|--------------------------------|--------|--------|
|GEN_HIER0_COL-0                 |1       |0       |
|GEN_HIER0_ROW-0                 |1       |0       |
|GEN_HIER1_COL_0                 |1       |0       |
|GEN_HIER1_ROW_0                 |1       |0       |
|GEN_HIER1_ROW_1                 |1       |0       |
|GEN_HIER2_COUNTER0-0            |1       |0       |
|GEN_HIER2_COUNTER1-0            |1       |0       |

compareProjects

compareInstances

Code Block
$ make compare_instances PROJECT_PATH=/home/users/kchopier/fae/tool/tool/top
compare_instances PROJECT_PATH=/home/users/kchopier/fae/tool/tool/top
Instance,4-LUT,DFF,XLUT,1-bit CY,RFB,CDC,CB,CS,DSP,RAM,WFG,PLL
/home/users/kchopier/fae/tool/tool/top_logic_NG-MEDIUM,13,0,0,0,0,0,0,0,0,0,0,0
/home/users/kchopier/fae/tool/tool/top_RAM_NG-MEDIUM,20,0,0,8,1,0,0,0,0,1,0,0

compareSta

Code Block
breakoutModewide
$ make compare_sta PROJECT_PATH=/home/users/kchopier/fae/tool/tool/test_2 STEP=Routed CONDITION=worstcase
compare_sta PROJECT_PATH=/home/users/kchopier/fae/tool/tool/test_2 STEP=Routed CONDITION=worstcase
Source,i_core_0|clk_core_1M (Rising),CLK_140M (Rising),rg~CLK_p (Rising),rg~i_core_0|clk_core_70M (Rising)
Target,i_core_0|clk_core_1M (Rising),CLK_140M (Rising),rg~CLK_p (Rising),rg~i_core_0|clk_core_70M (Rising)
Required,2.187 MHz,139.978 MHz,34.994 MHz,69.989 MHz
/home/users/kchopier/fae/tool/tool/test_22,29.657 MHz,130.924 MHz,28.395 MHz,74.789 MHz
/home/users/kchopier/fae/tool/tool/test_21,31.386 MHz,130.702 MHz,28.913 MHz,73.025 MHz
/home/users/kchopier/fae/tool/tool/test_20,33.485 MHz,130.924 MHz,31.586 MHz,72.312 MHz