tool_22.1.0.1-v0: https://files.nanoxplore.com/f/603188918fce48dfb748/?dl=1
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Introduction
NanoXplore provides a tool in order to compute:
NX_PLL parameters : Generate parameters to set when instantiate NX_PLL in VHDL code
NX_WFG parameters : Generate parameters constrainModule constraintsto set when instantiate NX_PLL in VHDL code
confineModule constraints: Generate constraints to set to create and confine modules
Examples
NX_PLL
User needed PLL
...
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$ make wfg_calculator_interface wfg_calculator_interface What is the input clock frequency in MHz ? 100 What is the output clock frequency in MHz. It has to be input clock frequency divided by power of 2 in the range [6.25;100.0]? 25 For how many input clock cycles do you want to shift output clock in the range [0;2] ? 1 On which edge of input clock do you want to generate output clock ? 1 - Rising edge 2 - Falling edge 1 //////////WFG parameters////////// mode => '1' , wfg_edge => '1' , pattern => "0110011001100110" , pattern_end => 15 |
confineModules
constrainModules
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$ make constrain_modules HIERARCHY_FILE=~/fae/tool/tool/hierarchy.rpt HIERARCHY_LEVEL_MAX=2 EXCLUSIVE=False
constrain_modules HIERARCHY_FILE=/home/users/kchopier/fae/tool/tool/hierarchy.rpt HIERARCHY_LEVEL_MAX=2 EXCLUSIVE=False
#New sub-module
p.addModule('RAM(X6AAF88E9)','g_loop_depth4[0].i_RAM_example','RAM(X6AAF88E9)_MOD0-%')
#New sub-module
p.addModule('RAM(X6AAF88E9)','g_loop_depth4[1].i_RAM_example','RAM(X6AAF88E9)_MOD1-%')
#New sub-module
p.addModule('RAM(X5A5D25DC)','g_loop_depth8[0].i_RAM_example','RAM(X5A5D25DC)_MOD0-%')
#New sub-module
p.addModule('RAM(X5A5D25DC)','g_loop_depth8[1].i_RAM_example','RAM(X5A5D25DC)_MOD1-%')
p.createRegion('RAM(X6AAF88E9)_REG0',,,,,False)
p.createRegion('RAM(X6AAF88E9)_REG1',,,,,False)
p.createRegion('RAM(X5A5D25DC)_REG0',,,,,False)
p.createRegion('RAM(X5A5D25DC)_REG1',,,,,False)
p.confineModule('RAM(X6AAF88E9)_MOD0-0','RAM(X6AAF88E9)_REG0')
p.confineModule('RAM(X6AAF88E9)_MOD1-0','RAM(X6AAF88E9)_REG1')
p.confineModule('RAM(X5A5D25DC)_MOD0-0','RAM(X5A5D25DC)_REG0')
p.confineModule('RAM(X5A5D25DC)_MOD1-0','RAM(X5A5D25DC)_REG1') |
statModules
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$ make stat_modules HIERARCHY_FILE=~/fae/tool/tool/hierarchy.rpt
stat_modules HIERARCHY_FILE=/home/users/kchopier/fae/tool/tool/hierarchy.rpt
////////// GEN_HIER0_COL-0 //////////
// TILE //
{'LUT': 0.0, 'DFF': 0.01, 'XLUT': 0.0, 'CY': 0.0, 'RFB': 0.0}
// CGB //
{'DSP': 0.0, 'RAM': 0.0}
////////// GEN_HIER0_ROW-0 //////////
// TILE //
{'LUT': 0.0, 'DFF': 0.01, 'XLUT': 0.0, 'CY': 0.0, 'RFB': 0.0}
// CGB //
{'DSP': 0.0, 'RAM': 0.0}
////////// GEN_HIER1_COL_0 //////////
// TILE //
{'LUT': 0.0, 'DFF': 0.01, 'XLUT': 0.0, 'CY': 0.0, 'RFB': 0.0}
// CGB //
{'DSP': 0.0, 'RAM': 0.0}
////////// GEN_HIER1_ROW_0 //////////
// TILE //
{'LUT': 0.0, 'DFF': 0.01, 'XLUT': 0.0, 'CY': 0.0, 'RFB': 0.0}
// CGB //
{'DSP': 0.0, 'RAM': 0.0}
////////// GEN_HIER1_ROW_1 //////////
// TILE //
{'LUT': 0.0, 'DFF': 0.01, 'XLUT': 0.0, 'CY': 0.0, 'RFB': 0.0}
// CGB //
{'DSP': 0.0, 'RAM': 0.0}
////////// GEN_HIER2_COUNTER0-0 //////////
// TILE //
{'LUT': 0.01, 'DFF': 0.01, 'XLUT': 0.0, 'CY': 0.0, 'RFB': 0.0}
// CGB //
{'DSP': 0.0, 'RAM': 0.0}
////////// GEN_HIER2_COUNTER1-0 //////////
// TILE //
{'LUT': 0.0, 'DFF': 0.11, 'XLUT': 0.0, 'CY': 0.0, 'RFB': 0.0}
// CGB //
{'DSP': 0.0, 'RAM': 0.0}
////////// SUMMARY //////////
|Module |TILE |CGB |
|--------------------------------|--------|--------|
|GEN_HIER0_COL-0 |1 |0 |
|GEN_HIER0_ROW-0 |1 |0 |
|GEN_HIER1_COL_0 |1 |0 |
|GEN_HIER1_ROW_0 |1 |0 |
|GEN_HIER1_ROW_1 |1 |0 |
|GEN_HIER2_COUNTER0-0 |1 |0 |
|GEN_HIER2_COUNTER1-0 |1 |0 | |