Link V1.0 /Nxmap22.tool_22.1.0.1-v0: https://files.nanoxplore.com/f/3709351814f24326a310603188918fce48dfb748/?dl=1
Introduction
NanoXplore provides a tool in order to compute:
NX_PLL parameters
NX_WFG parameters
constrainModule constraints
Examples
NX_PLL
User needed PLL
| Code Block |
|---|
$ make pll_calculator_interface
pll_calculator_interface
Please set the variant ?
1 - NG-MEDIUM
2 - NG-LARGE
3 - NG-ULTRA
3
How the reference clock is generated ?
1 - External
2 - Internal (internal oscillator)
1
What is the reference clock frequency in MHz ?
50
Do you want to set a VCO frequency or let the tool research automatically ?
1 - Set VCO frequency
2 - Automatical research with 1st output clk
2
How many output clocks do you want to generate in the range [0;9] ?
2
What is the frequency of the output clock 0 in MHz ?
400
What is the frequency of the output clock 1 in MHz ?
200
//////////PLL setting//////////
|Signal |Frequency (MHz)|
|------ |-------------- |
|Ref |50.0 |
|Ref_int|50.0 |
|VCO |800.0 |
|------ |-------------- |
|DIVD5 |400.0 |
|DIVD4 |200.0 |
//////////PLL parameters//////////
ref_osc_on => '0' ,
ref_intdiv => 0 ,
fbk_int_div => 7 ,
clk_outdiv1 => to_bitvector(conv_std_logic_vector(0,3)) ,
clk_outdiv2 => to_bitvector(conv_std_logic_vector(0,3)) ,
clk_outdiv3 => to_bitvector(conv_std_logic_vector(0,3)) ,
clk_outdiv4 => to_bitvector(conv_std_logic_vector(0,3)) ,
clk_outdivd1 => to_bitvector(conv_std_logic_vector(0,4)) ,
clk_outdivd2 => to_bitvector(conv_std_logic_vector(0,4)) ,
clk_outdivd3 => to_bitvector(conv_std_logic_vector(0,4)) ,
clk_outdivd4 => to_bitvector(conv_std_logic_vector(1,4)) ,
clk_outdivd5 => to_bitvector(conv_std_logic_vector(0,4)) |
All available PLL
| Code Block |
|---|
$ make pll_all_values_interface
pll_all_values_interface
Please set the variant ?
1 - NG-MEDIUM
2 - NG-LARGE
3 - NG-ULTRA
2
How the reference clock is generated ?
1 - External
2 - Internal (internal oscillator)
1
What is the reference clock frequency in MHz ?
50
//////////PLL Output Values//////////
CLK (MHz),VCO (MHz),CLK name,ref_osc_on,ref_intdiv,fbk_int_div,clk_outdivp1,clk_outdivp2,clk_outdivp3o2,clk_outdivo1
0.390625,200.0,DIVP3,'0',0,0,0,0,7,0
0.390625,200.0,DIVP3,'0',1,2,0,0,7,0
0.48828125,250.0,DIVP3,'0',1,3,0,0,7,0
0.5859375,300.0,DIVP3,'0',0,1,0,0,7,0
0.5859375,300.0,DIVP3,'0',1,4,0,0,7,0
0.68359375,350.0,DIVP3,'0',1,5,0,0,7,0
0.78125,400.0,DIVP3,'0',0,2,0,0,7,0
0.78125,400.0,DIVP3,'0',1,6,0,0,7,0
0.78125,200.0,DIVP3,'0',0,0,0,0,6,0
0.78125,200.0,DIVP2,'0',0,0,0,7,0,0
0.78125,200.0,DIVP3,'0',1,2,0,0,6,0
0.78125,200.0,DIVP2,'0',1,2,0,7,0,0
|
WFG
| Code Block | ||
|---|---|---|
| ||
$ make wfg_calculator_interface wfg_calculator_interface What is the input clock frequency in MHz ? 100 What is the output clock frequency in MHz. It has to be input clock frequency divided by power of 2 in the range [6.25;100.0]? 25 For how many input clock cycles do you want to shift output clock in the range [0;2] ? 1 On which edge of input clock do you want to generate output clock ? 1 - Rising edge 2 - Falling edge 1 //////////WFG parameters////////// mode => '1' , wfg_edge => '1' , pattern => "0110011001100110" , pattern_end => 15 |
...