...
In order to match with all registers, it is possible to specify empty string ('') for parameters from_list or to_list.
-from and -to options apply the constraint to both the rising and falling edges
setFalsePath(source = ‘source', target = 'target’)
...
In order to match with all registers, source or target can be set to empty.
-from and -to options apply the constraint to both the rising and falling edges
setInputDelay(clock, clock_mode, minimum_delay, maximum_delay, port_list)
...
| Code Block | ||
|---|---|---|
| ||
project = createProject()
project.load('routed.nym')
project.setCaseAnalysis(value = '1', netList = 'getNet(sel)') |
addReportTimingPath(source = ‘source_reg', target = 'target_reg’)
This method gives the shortest and the longest delays of a path. This constraint is used by timing driven algorithms and static timing analysis.
Arguments:
Name | Type | Description |
|---|---|---|
source_reg | string | Specifies the starting points of the timing paths to be analyzed. A valid argument can only be a register : |
target_reg | string | Specifies the ending points or destination objects of timing paths to be analyzed. A valid argument can be: |
Example:
This method should be launched after creating an Analyzer, as follow :
| Code Block |
|---|
Timing_analysis = p.createAnalyzer()
Timing_analysis.addReportTimingPath(source = 'getRegister(i_cpt_0|s_cpt_out_reg[1])', target ='getRegister(i_cpt_1|s_cpt_out_reg[2])')
Timing_analysis.launch() |