This document aims to list all the the nxpython methods available to apply timing constraints on a design.
createClock( ) / ! \ DEPRECATED / ! \
Please use createClock(target = ‘target', name = ‘name’, period = ]0, ], rising = [0,period[, falling = ]rising, rising+period]) instead. This method is described immediately below.
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project = createProject()
project.load('routed.nym')
project.createClock('getRegisterClock(reg1)', 'clk', 10)
or
project.createClock('getPort(Clk)', 'clk', 10)
or
project.createClock('getClockNet(Clk)', 'clk', 10, 0, 5) |
createClock( target = ‘target', name = ‘name’, period = ]0, ], rising = [0,period[, falling = ]rising, rising+period] )
This method is used to create a clock constraint at a timing point. This constraint is used by timing driven algorithms and static timing analysis. Depending on the unit defined in the project, timings are in ns or ps.
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project = createProject()
project.load('routed.nym')
project.createClock(target = 'getRegisterClock(reg1)', name = 'Clk', period = 10)
or
project.createClock(target = 'getPort(Clk)', name = 'Clk', period = 10)
or
project.createClock(target = 'getClockNet(Clk)', name = 'Clk', period = 10, rising = 0, falling = 5) |
createGeneratedClock(source, target, name, relationship)
/ ! \ DEPRECATED / ! \ Please use createGeneratedClock(source = ‘source', target = ‘target’, name = 'name', key = value) instead. This method is described immediately below.
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The diagram of the above command would be:
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createGeneratedClock(source = ‘source', target = ‘target’, name = 'name', key = value)
This method is used to create an internal generated clock constraint at a timing point. This constraint is used by timing driven algorithms and static timing analysis.
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The diagram of the above command would be:
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setClockGroup(group1_list, group2_list, option)
/ ! \ DEPRECATED / ! \ Please use setClockGroup(group1 = ‘group1’, group2 = ‘group2', option = 'option’) instead. This method is described immediately below.
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project = createProject()
project.load('routed.nym')
project.createClock('getRegister(UUT1\|Gen_seq[2].seq_i\|temp_reg[13])', 'clk1', 2.7)
project.createClock('getClockNet(CLOCK[2])', 'clk2', 5, 0, 2)
project.setClockGroup('getClock(clk1)', 'getClock(clk2)', 'exclusive') |
setClockGroup(group1 = ‘group1', group2= ‘group2’, option = 'option’)
This method is used to specify which clocks are not related. This constraint is used by timing driven algorithms and static timing analysis.
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project = createProject()
project.load('routed.nym')
project.createClock(name ='clk1', period = 2.7, target= 'getRegister(UUT1\|Gen_seq[2].seq_i\|temp_reg[13])')
project.createClock(name = 'clk2', period = 5, rising = 0, falling = 2, target= 'getClockNet(CLOCK[2])')
project.setClockGroup(group1 = 'getClock(clk1)', group2 = 'getClock(clk2)', option = 'exclusive') |
addMaxDelayPath(from_list, to_list, delay)
/ ! \ DEPRECATED / ! \ Please use setMaxDelay instead, with the same key arguments. This method is described immediately below.
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project = createProject()
project.load('routed.nym')
project.addMaxDelayPath('getRegister('UUT1\|Gen_seq[3].seq_i\|temp_reg[1]')', 'getRegister('UUT2\|dout_reg[61]')', 3.9)
project.addMaxDelayPath('getPort(cpt_in[0])', 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', 8.0)
project.addMaxDelayPath('getRegister(i_cpt_0\|s_cpt_out_reg[0])','getRegister(i_cpt_1\|s_cpt_out_reg[1])', 4.0)
project.addMaxDelayPath('getPorts("cpt_in[`[1-3]`]")','getRegister(i_cpt_1\|s_cpt_out_reg[1])', 8.0)
project.addMaxDelayPath('getRegisters("i_cpt_0\|s_cpt_out_reg[`[1-3]`]")', 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', 8.0) |
setMaxDelay(source = ‘source', target = ‘target’, delay = 'delay’)
This method is used to specify the maximum delay path for the timing paths. It is used by timing driven algorithms and static timing analysis.
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project = createProject()
project.load('routed.nym')
project.setMaxDelay(source = 'getRegister('UUT1\|Gen_seq[3].seq_i\|temp_reg[1]')', target = 'getRegister('UUT2\|dout_reg[61]')', delay = 3.9)
project.setMaxDelay(source = 'getPort(cpt_in[0])', target = 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', delay = 8.0)
project.setMaxDelay(source = 'getRegister(i_cpt_0\|s_cpt_out_reg[0])', target = 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', delay = 4.0)
project.setMaxDelay(source = 'getPorts("cpt_in[`[1-3]`]")', target = 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', delay = 8.0)
project.setMaxDelay(source = 'getRegisters("i_cpt_0\|s_cpt_out_reg[`[1-3]`]")', target = 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', delay = 8.0) |
addMinDelayPath(from_list, to_list, delay)
/ ! \ DEPRECATED / ! \ Please use setMinDelay instead, with the same key arguments. This method is described immediately below.
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project = createProject()
project.load('routed.nym')
project.addMinDelayPath('getRegister('UUT1\|Gen_seq[3].seq_i\|temp_reg[23]')', 'getRegister('UUT1\|Gen_seq[3].seq_i\|temp_reg[22]')', 1.2)
project.addMinDelayPath('getPort(cpt_in[0])', 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', 8.0)
project.addMinDelayPath('getRegister(i_cpt_0\|s_cpt_out_reg[0])', 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', 8.0)
project.addMinDelayPath('getPorts("cpt_in[`[1-3]`]")', 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', 8.0)
project.addMinDelayPath('getRegisters("i_cpt_0\|s_cpt_out_reg[`[1-3]`]")', 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', 8.0) |
setMinDelay(source = ‘source', target = ‘target’, delay = 'delay’)
This method is used to specify the minimum delay path for the timing paths. It is used by timing driven algorithms and static timing analysis.
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project = createProject()
project.load('routed.nym')
project.setMinDelay(source = 'getRegister('UUT1\|Gen_seq[3].seq_i\|temp_reg[23]')', target = 'getRegister('UUT1\|Gen_seq[3].seq_i\|temp_reg[22]')', delay = 1.2)
project.setMinDelay(source = 'getPort(cpt_in[0])', target = 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', delay = 8.0)
project.setMinDelay(source = 'getRegister(i_cpt_0\|s_cpt_out_reg[0])', target = 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', delay = 8.0)
project.setMinDelay(source = 'getPorts("cpt_in[`[1-3]`]")', target = 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', delay = 8.0)
project.setMinDelay(source = 'getRegisters("i_cpt_0\|s_cpt_out_reg[`[1-3]`]")', target = 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', delay = 8.0) |
addMulticyclePath(from_list, to_list, cycle_count)
/ ! \ DEPRECATED / ! \ Please use setMulticyclePath instead, with the same key arguments. This method is described immediately below.
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This method is only available for path(s) whose source and target registers are clocked by the same clock! |
setMulticyclePath(source = 'source', target = 'target', pathMultiplier = 'pathMultiplier')
This method is used to specify the multicycle path for the timing paths. It is used by timing driven algorithms and static timing analysis.
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This method is only available for path(s) whose source and target registers are clocked by the same clock! |
addFalsePath(from_list, to_list)
/ ! \ DEPRECATED / ! \ Please use setFalsePath instead, with the same key arguments. This method is described immediately below.
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-from and -to options apply the constraint to both the rising and falling edges
setFalsePath(source = ‘source', target = 'target’)
This method is used to specify the false path for the timing paths. This constraint is used by timing driven algorithms and static timing analysis.
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-from and -to options apply the constraint to both the rising and falling edges
setInputDelay(clock, clock_mode, minimum_delay, maximum_delay, port_list)
/ ! \ DEPRECATED / ! \ Please use setInputDelay(clock = ‘clock', clockMode = ‘clockMode’, min = ‘min’, max = ‘max’, ports = 'ports’) instead. This method is described immediately below.
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project = createProject()
project.load('routed.nym')
project.createClock(getClockNet('CLK'),'CLK',8)
project.setInputDelay(getClock('CLK'),'rise', 1, 1.5, getPort('RST')) |
setInputDelay(clock = ‘clock', clockMode = ‘clockMode’, min = ‘min’, max = ‘max’, ports = 'ports’)
This method specifies the data arrival times at the specified input ports relative to the clock. The clock must refer to a clock name in the design. This constraint is used by timing driven algorithms and static timing analysis. Depending on the unit define in the project, timings are in ns or ps.
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project = createProject()
project.load('routed.nym')
project.createClock(target = 'getClockNet(CLK)', name = 'clock',period = 8)
project.setInputDelay(clock = 'getClock(clock)', clockMode = 'rise', min = 1, max = 1.5, ports = 'getPort(RST)') |
setOutputDelay(clock, clock_mode, minimum_delay, maximum_delay, port_list)
/ ! \ DEPRECATED / ! \ Please use setOutputDelay(clock = ‘clock', clockMode = ‘clockMode’, min = ‘min’, max = ‘max’, ports = 'ports’) instead. This method is described immediately below.
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project = createProject()
project.load('routed.nym')
project.createClock(getClockNet('CLK'),'CLK',8)
project.setOutputDelay(getClock('CLK'),'rise', 1.0, 1.5, getPorts('dataout[`[0−5]`]')) |
setOutputDelay(clock = ‘clock', clockMode = ‘clockMode’, min = ‘min’, max = ‘max’, ports = 'ports’)
This command specifies the data required times at the specified output ports relative to the clock. The clock must refer to a clock defined in the design. This constraint is used by timing driven algorithms and static timing analysis. Depending on the unit defined in the project, timings could be in ns or ps.
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project = createProject()
project.load('routed.nym')
project.createClock(target = 'getClockNet('CLK')', name = 'CLK', period = 8)
project.setOutputDelay(clock = 'getClock(clock)', clockMode = 'rise', min = 1, max = 1.5, ports = 'getPort(RST)') |
developCKGs()
This method automatically creates a generated clock constraint on each output of the PLLs and WFGs in current project. This constraint is used by timing driven algorithms and static timing analysis.
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project = createProject()
project.load('routed.nym')
project.createClock(target = 'getClockNet(CLK)', name ='clk', period = 8, rising = 0, falling = 4)
project.developCKGs()
project.createGeneratedClock(source = 'getWFGOutput(wfg_clk[1])', target= 'getRegister(data_reg[0])', name='clk1_div2', divideBy = 2) |
setAnalysisConditions(conditions)
/ ! \ DEPRECATED / ! \ Please use setAnalysisConditions(conditions = 'conditions') instead.
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project.setAnalysisConditions(WorstCase) |
setAnalysisConditions(conditions = 'conditions')
This method is used to specify the chip conditions for the static timing analysis. This constraint is used by timing driven algorithms and static timing analysis.
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project.setAnalysisConditions(conditions = 'worstcase') |
setCaseAnalysis(value, net_list)
/ ! \ DEPRECATED / ! \ Please use setCaseAnalysis(value = ‘value', netList = 'netList’) instead. This method is described immediately below.
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project = createProject()
project.load('routed.nym')
project.setCaseAnalysis(1, 'getNet(sel)') |
setCaseAnalysis(value = ‘value', netList = 'netList’)
This method is used to specify a constant logic value to the given tests. This constraint is used by timing driven algorithms and static timing analysis.
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